first commit

.cproject

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+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<?fileVersion 4.0.0?><cproject storage_type_id="org.eclipse.cdt.core.XmlProjectDescriptionStorage">
+	<storageModule moduleId="org.eclipse.cdt.core.settings">
+		<cconfiguration id="com.st.stm32cube.ide.mcu.gnu.managedbuild.config.exe.debug.314677694">
+			<storageModule buildSystemId="org.eclipse.cdt.managedbuilder.core.configurationDataProvider" id="com.st.stm32cube.ide.mcu.gnu.managedbuild.config.exe.debug.314677694" moduleId="org.eclipse.cdt.core.settings" name="Debug">
+				<externalSettings/>
+				<extensions>
+					<extension id="org.eclipse.cdt.core.ELF" point="org.eclipse.cdt.core.BinaryParser"/>
+					<extension id="org.eclipse.cdt.core.GASErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+					<extension id="org.eclipse.cdt.core.GmakeErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+					<extension id="org.eclipse.cdt.core.GLDErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+					<extension id="org.eclipse.cdt.core.CWDLocator" point="org.eclipse.cdt.core.ErrorParser"/>
+					<extension id="org.eclipse.cdt.core.GCCErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+				</extensions>
+			</storageModule>
+			<storageModule moduleId="cdtBuildSystem" version="4.0.0">
+				<configuration artifactExtension="elf" artifactName="${ProjName}" buildArtefactType="org.eclipse.cdt.build.core.buildArtefactType.exe" buildProperties="org.eclipse.cdt.build.core.buildArtefactType=org.eclipse.cdt.build.core.buildArtefactType.exe,org.eclipse.cdt.build.core.buildType=org.eclipse.cdt.build.core.buildType.debug" cleanCommand="rm -rf" description="" id="com.st.stm32cube.ide.mcu.gnu.managedbuild.config.exe.debug.314677694" name="Debug" parent="com.st.stm32cube.ide.mcu.gnu.managedbuild.config.exe.debug">
+					<folderInfo id="com.st.stm32cube.ide.mcu.gnu.managedbuild.config.exe.debug.314677694." name="/" resourcePath="">
+						<toolChain id="com.st.stm32cube.ide.mcu.gnu.managedbuild.toolchain.exe.debug.1989521580" name="MCU ARM GCC" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.toolchain.exe.debug">
+							<option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.target_mcu.752421150" name="MCU" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.target_mcu" useByScannerDiscovery="true" value="STM32F405RGTx" valueType="string"/>
+							<option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.target_cpuid.820956425" name="CPU" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.target_cpuid" useByScannerDiscovery="false" value="0" valueType="string"/>
+							<option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.target_coreid.1465694889" name="Core" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.target_coreid" useByScannerDiscovery="false" value="0" valueType="string"/>
+							<option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.fpu.880312495" name="Floating-point unit" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.fpu" useByScannerDiscovery="true" value="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.fpu.value.fpv4-sp-d16" valueType="enumerated"/>
+							<option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.floatabi.1507179498" name="Floating-point ABI" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.floatabi" useByScannerDiscovery="true" value="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.floatabi.value.hard" valueType="enumerated"/>
+							<option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.target_board.501173091" name="Board" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.target_board" useByScannerDiscovery="false" value="genericBoard" valueType="string"/>
+							<option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.defaults.583349906" name="Defaults" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.defaults" useByScannerDiscovery="false" value="com.st.stm32cube.ide.common.services.build.inputs.revA.1.0.6 || Debug || true || Executable || com.st.stm32cube.ide.mcu.gnu.managedbuild.option.toolchain.value.workspace || STM32F405RGTx || 0 || 0 || arm-none-eabi- || ${gnu_tools_for_stm32_compiler_path} || ../Core/Inc | ../Drivers/STM32F4xx_HAL_Driver/Inc | ../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy | ../Drivers/CMSIS/Device/ST/STM32F4xx/Include | ../Drivers/CMSIS/Include ||  ||  || USE_HAL_DRIVER | STM32F405xx ||  || Drivers | Core/Startup | Core ||  ||  || ${workspace_loc:/${ProjName}/STM32F405RGTX_FLASH.ld} || true || NonSecure ||  || secure_nsclib.o ||  || None ||  ||  || " valueType="string"/>
+							<option id="com.st.stm32cube.ide.mcu.debug.option.cpuclock.372554506" name="Cpu clock frequence" superClass="com.st.stm32cube.ide.mcu.debug.option.cpuclock" useByScannerDiscovery="false" value="168" valueType="string"/>
+							<option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.converthex.680016835" name="Convert to Intel Hex file (-O ihex)" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.converthex" useByScannerDiscovery="false" value="true" valueType="boolean"/>
+							<targetPlatform archList="all" binaryParser="org.eclipse.cdt.core.ELF" id="com.st.stm32cube.ide.mcu.gnu.managedbuild.targetplatform.1411976801" isAbstract="false" osList="all" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.targetplatform"/>
+							<builder buildPath="${workspace_loc:/stm32f405_boot}/Debug" id="com.st.stm32cube.ide.mcu.gnu.managedbuild.builder.1019591460" keepEnvironmentInBuildfile="false" managedBuildOn="true" name="Gnu Make Builder" parallelBuildOn="true" parallelizationNumber="optimal" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.builder"/>
+							<tool id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.assembler.963551019" name="MCU/MPU GCC Assembler" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.assembler">
+								<option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.assembler.option.debuglevel.1841213271" name="Debug level" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.assembler.option.debuglevel" value="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.assembler.option.debuglevel.value.g3" valueType="enumerated"/>
+								<option IS_BUILTIN_EMPTY="false" IS_VALUE_EMPTY="false" id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.assembler.option.definedsymbols.1967568841" name="Define symbols (-D)" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.assembler.option.definedsymbols" valueType="definedSymbols">
+									<listOptionValue builtIn="false" value="DEBUG"/>
+								</option>
+								<inputType id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.assembler.input.1385679469" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.assembler.input"/>
+							</tool>
+							<tool id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.776680924" name="MCU/MPU GCC Compiler" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler">
+								<option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.option.debuglevel.1236253442" name="Debug level" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.option.debuglevel" useByScannerDiscovery="false" value="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.option.debuglevel.value.g3" valueType="enumerated"/>
+								<option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.option.optimization.level.1774190064" name="Optimization level" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.option.optimization.level" useByScannerDiscovery="false" value="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.option.optimization.level.value.o0" valueType="enumerated"/>
+								<option IS_BUILTIN_EMPTY="false" IS_VALUE_EMPTY="false" id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.option.definedsymbols.2125854748" name="Define symbols (-D)" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.option.definedsymbols" useByScannerDiscovery="false" valueType="definedSymbols">
+									<listOptionValue builtIn="false" value="DEBUG"/>
+									<listOptionValue builtIn="false" value="USE_HAL_DRIVER"/>
+									<listOptionValue builtIn="false" value="STM32F405xx"/>
+								</option>
+								<option IS_BUILTIN_EMPTY="false" IS_VALUE_EMPTY="false" id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.option.includepaths.157787730" name="Include paths (-I)" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.option.includepaths" useByScannerDiscovery="false" valueType="includePath">
+									<listOptionValue builtIn="false" value="../Core/Inc"/>
+									<listOptionValue builtIn="false" value="../Drivers/STM32F4xx_HAL_Driver/Inc"/>
+									<listOptionValue builtIn="false" value="../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy"/>
+									<listOptionValue builtIn="false" value="../Drivers/CMSIS/Device/ST/STM32F4xx/Include"/>
+									<listOptionValue builtIn="false" value="../Drivers/CMSIS/Include"/>
+									<listOptionValue builtIn="false" value="&quot;${workspace_loc:/${ProjName}/Core/can_tp}&quot;"/>
+								</option>
+								<inputType id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.input.c.703420091" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.input.c"/>
+							</tool>
+							<tool id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.cpp.compiler.1403424928" name="MCU/MPU G++ Compiler" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.cpp.compiler">
+								<option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.cpp.compiler.option.debuglevel.782228718" name="Debug level" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.cpp.compiler.option.debuglevel" useByScannerDiscovery="false" value="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.cpp.compiler.option.debuglevel.value.g3" valueType="enumerated"/>
+								<option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.cpp.compiler.option.optimization.level.923391811" name="Optimization level" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.cpp.compiler.option.optimization.level" useByScannerDiscovery="false"/>
+							</tool>
+							<tool id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.linker.226507234" name="MCU/MPU GCC Linker" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.linker">
+								<option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.linker.option.script.2118087127" name="Linker Script (-T)" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.linker.option.script" value="${workspace_loc:/${ProjName}/STM32F405RGTX_FLASH.ld}" valueType="string"/>
+								<inputType id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.linker.input.1822350531" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.linker.input">
+									<additionalInput kind="additionalinputdependency" paths="$(USER_OBJS)"/>
+									<additionalInput kind="additionalinput" paths="$(LIBS)"/>
+								</inputType>
+							</tool>
+							<tool id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.cpp.linker.171779174" name="MCU/MPU G++ Linker" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.cpp.linker"/>
+							<tool id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.archiver.1361348285" name="MCU/MPU GCC Archiver" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.archiver"/>
+							<tool id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.size.1093897917" name="MCU Size" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.size"/>
+							<tool id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.objdump.listfile.257997389" name="MCU Output Converter list file" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.objdump.listfile"/>
+							<tool id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.objcopy.hex.1151987205" name="MCU Output Converter Hex" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.objcopy.hex"/>
+							<tool id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.objcopy.binary.1618741417" name="MCU Output Converter Binary" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.objcopy.binary"/>
+							<tool id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.objcopy.verilog.346031568" name="MCU Output Converter Verilog" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.objcopy.verilog"/>
+							<tool id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.objcopy.srec.1455616712" name="MCU Output Converter Motorola S-rec" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.objcopy.srec"/>
+							<tool id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.objcopy.symbolsrec.1124941094" name="MCU Output Converter Motorola S-rec with symbols" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.objcopy.symbolsrec"/>
+						</toolChain>
+					</folderInfo>
+					<sourceEntries>
+						<entry flags="VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name="Core"/>
+						<entry flags="VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name="Drivers"/>
+					</sourceEntries>
+				</configuration>
+			</storageModule>
+			<storageModule moduleId="org.eclipse.cdt.core.externalSettings"/>
+		</cconfiguration>
+		<cconfiguration id="com.st.stm32cube.ide.mcu.gnu.managedbuild.config.exe.release.1081983597">
+			<storageModule buildSystemId="org.eclipse.cdt.managedbuilder.core.configurationDataProvider" id="com.st.stm32cube.ide.mcu.gnu.managedbuild.config.exe.release.1081983597" moduleId="org.eclipse.cdt.core.settings" name="Release">
+				<externalSettings/>
+				<extensions>
+					<extension id="org.eclipse.cdt.core.ELF" point="org.eclipse.cdt.core.BinaryParser"/>
+					<extension id="org.eclipse.cdt.core.GASErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+					<extension id="org.eclipse.cdt.core.GmakeErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+					<extension id="org.eclipse.cdt.core.GLDErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+					<extension id="org.eclipse.cdt.core.CWDLocator" point="org.eclipse.cdt.core.ErrorParser"/>
+					<extension id="org.eclipse.cdt.core.GCCErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+				</extensions>
+			</storageModule>
+			<storageModule moduleId="cdtBuildSystem" version="4.0.0">
+				<configuration artifactExtension="elf" artifactName="${ProjName}" buildArtefactType="org.eclipse.cdt.build.core.buildArtefactType.exe" buildProperties="org.eclipse.cdt.build.core.buildArtefactType=org.eclipse.cdt.build.core.buildArtefactType.exe,org.eclipse.cdt.build.core.buildType=org.eclipse.cdt.build.core.buildType.release" cleanCommand="rm -rf" description="" id="com.st.stm32cube.ide.mcu.gnu.managedbuild.config.exe.release.1081983597" name="Release" parent="com.st.stm32cube.ide.mcu.gnu.managedbuild.config.exe.release">
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+									<listOptionValue builtIn="false" value="../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy"/>
+									<listOptionValue builtIn="false" value="../Drivers/CMSIS/Device/ST/STM32F4xx/Include"/>
+									<listOptionValue builtIn="false" value="../Drivers/CMSIS/Include"/>
+								</option>
+								<inputType id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.input.c.1204606034" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.input.c"/>
+							</tool>
+							<tool id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.cpp.compiler.1159097118" name="MCU/MPU G++ Compiler" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.cpp.compiler">
+								<option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.cpp.compiler.option.debuglevel.1406306526" name="Debug level" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.cpp.compiler.option.debuglevel" useByScannerDiscovery="false" value="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.cpp.compiler.option.debuglevel.value.g0" valueType="enumerated"/>
+								<option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.cpp.compiler.option.optimization.level.295895275" name="Optimization level" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.cpp.compiler.option.optimization.level" useByScannerDiscovery="false" value="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.cpp.compiler.option.optimization.level.value.os" valueType="enumerated"/>
+							</tool>
+							<tool id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.linker.1823184670" name="MCU/MPU GCC Linker" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.linker">
+								<option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.linker.option.script.1007955321" name="Linker Script (-T)" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.linker.option.script" value="${workspace_loc:/${ProjName}/STM32F405RGTX_FLASH.ld}" valueType="string"/>
+								<inputType id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.linker.input.2112574891" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.linker.input">
+									<additionalInput kind="additionalinputdependency" paths="$(USER_OBJS)"/>
+									<additionalInput kind="additionalinput" paths="$(LIBS)"/>
+								</inputType>
+							</tool>
+							<tool id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.cpp.linker.1417251800" name="MCU/MPU G++ Linker" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.cpp.linker"/>
+							<tool id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.archiver.1315317616" name="MCU/MPU GCC Archiver" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.archiver"/>
+							<tool id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.size.456766410" name="MCU Size" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.size"/>
+							<tool id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.objdump.listfile.904876690" name="MCU Output Converter list file" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.objdump.listfile"/>
+							<tool id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.objcopy.hex.794067146" name="MCU Output Converter Hex" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.objcopy.hex"/>
+							<tool id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.objcopy.binary.1524239521" name="MCU Output Converter Binary" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.objcopy.binary"/>
+							<tool id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.objcopy.verilog.1752872671" name="MCU Output Converter Verilog" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.objcopy.verilog"/>
+							<tool id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.objcopy.srec.23692569" name="MCU Output Converter Motorola S-rec" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.objcopy.srec"/>
+							<tool id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.objcopy.symbolsrec.1283041" name="MCU Output Converter Motorola S-rec with symbols" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.objcopy.symbolsrec"/>
+						</toolChain>
+					</folderInfo>
+					<sourceEntries>
+						<entry flags="VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name="Core"/>
+						<entry flags="VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name="Drivers"/>
+					</sourceEntries>
+				</configuration>
+			</storageModule>
+			<storageModule moduleId="org.eclipse.cdt.core.externalSettings"/>
+		</cconfiguration>
+	</storageModule>
+	<storageModule moduleId="org.eclipse.cdt.core.pathentry"/>
+	<storageModule moduleId="cdtBuildSystem" version="4.0.0">
+		<project id="stm32f405_boot.null.1301663876" name="stm32f405_boot"/>
+	</storageModule>
+	<storageModule moduleId="org.eclipse.cdt.core.LanguageSettingsProviders"/>
+	<storageModule moduleId="scannerConfiguration">
+		<autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId=""/>
+		<scannerConfigBuildInfo instanceId="com.st.stm32cube.ide.mcu.gnu.managedbuild.config.exe.debug.314677694;com.st.stm32cube.ide.mcu.gnu.managedbuild.config.exe.debug.314677694.;com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.776680924;com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.input.c.703420091">
+			<autodiscovery enabled="false" problemReportingEnabled="true" selectedProfileId=""/>
+		</scannerConfigBuildInfo>
+		<scannerConfigBuildInfo instanceId="com.st.stm32cube.ide.mcu.gnu.managedbuild.config.exe.release.1081983597;com.st.stm32cube.ide.mcu.gnu.managedbuild.config.exe.release.1081983597.;com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.2015809620;com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.input.c.1204606034">
+			<autodiscovery enabled="false" problemReportingEnabled="true" selectedProfileId=""/>
+		</scannerConfigBuildInfo>
+	</storageModule>
+	<storageModule moduleId="org.eclipse.cdt.make.core.buildtargets"/>
+	<storageModule moduleId="refreshScope" versionNumber="2">
+		<configuration configurationName="Debug">
+			<resource resourceType="PROJECT" workspacePath="/stm32f405_boot"/>
+		</configuration>
+		<configuration configurationName="Release">
+			<resource resourceType="PROJECT" workspacePath="/stm32f405_boot"/>
+		</configuration>
+	</storageModule>
+</cproject>

.project

@@ -0,0 +1,32 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<projectDescription>
+	<name>stm32f405_boot</name>
+	<comment></comment>
+	<projects>
+	</projects>
+	<buildSpec>
+		<buildCommand>
+			<name>org.eclipse.cdt.managedbuilder.core.genmakebuilder</name>
+			<triggers>clean,full,incremental,</triggers>
+			<arguments>
+			</arguments>
+		</buildCommand>
+		<buildCommand>
+			<name>org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder</name>
+			<triggers>full,incremental,</triggers>
+			<arguments>
+			</arguments>
+		</buildCommand>
+	</buildSpec>
+	<natures>
+		<nature>com.st.stm32cube.ide.mcu.MCUProjectNature</nature>
+		<nature>org.eclipse.cdt.core.cnature</nature>
+		<nature>com.st.stm32cube.ide.mcu.MCUCubeIdeServicesRevAev2ProjectNature</nature>
+		<nature>com.st.stm32cube.ide.mcu.MCUCubeProjectNature</nature>
+		<nature>com.st.stm32cube.ide.mcu.MCUAdvancedStructureProjectNature</nature>
+		<nature>com.st.stm32cube.ide.mcu.MCUSingleCpuProjectNature</nature>
+		<nature>com.st.stm32cube.ide.mcu.MCURootProjectNature</nature>
+		<nature>org.eclipse.cdt.managedbuilder.core.managedBuildNature</nature>
+		<nature>org.eclipse.cdt.managedbuilder.core.ScannerConfigNature</nature>
+	</natures>
+</projectDescription>

.settings/com.st.stm32cube.ide.mcu.sfrview.prefs

@@ -0,0 +1,2 @@
+eclipse.preferences.version=1
+sfrviewstate={"fFavorites"\:{"fLists"\:{}},"fProperties"\:{"fNodeProperties"\:{}}}

.settings/language.settings.xml

@@ -0,0 +1,25 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<project>
+	<configuration id="com.st.stm32cube.ide.mcu.gnu.managedbuild.config.exe.debug.314677694" name="Debug">
+		<extension point="org.eclipse.cdt.core.LanguageSettingsProvider">
+			<provider-reference id="org.eclipse.cdt.ui.UserLanguageSettingsProvider" ref="shared-provider"/>
+			<provider-reference id="org.eclipse.cdt.core.ReferencedProjectsLanguageSettingsProvider" ref="shared-provider"/>
+			<provider-reference id="org.eclipse.cdt.managedbuilder.core.MBSLanguageSettingsProvider" ref="shared-provider"/>
+			<provider class="com.st.stm32cube.ide.mcu.toolchain.armnone.setup.CrossBuiltinSpecsDetector" console="false" env-hash="1547178201051311674" id="com.st.stm32cube.ide.mcu.toolchain.armnone.setup.CrossBuiltinSpecsDetector" keep-relative-paths="false" name="MCU ARM GCC Built-in Compiler Settings" parameter="${COMMAND} ${FLAGS} -E -P -v -dD &quot;${INPUTS}&quot;" prefer-non-shared="true">
+				<language-scope id="org.eclipse.cdt.core.gcc"/>
+				<language-scope id="org.eclipse.cdt.core.g++"/>
+			</provider>
+		</extension>
+	</configuration>
+	<configuration id="com.st.stm32cube.ide.mcu.gnu.managedbuild.config.exe.release.1081983597" name="Release">
+		<extension point="org.eclipse.cdt.core.LanguageSettingsProvider">
+			<provider-reference id="org.eclipse.cdt.ui.UserLanguageSettingsProvider" ref="shared-provider"/>
+			<provider-reference id="org.eclipse.cdt.core.ReferencedProjectsLanguageSettingsProvider" ref="shared-provider"/>
+			<provider-reference id="org.eclipse.cdt.managedbuilder.core.MBSLanguageSettingsProvider" ref="shared-provider"/>
+			<provider class="com.st.stm32cube.ide.mcu.toolchain.armnone.setup.CrossBuiltinSpecsDetector" console="false" env-hash="1547178201051311674" id="com.st.stm32cube.ide.mcu.toolchain.armnone.setup.CrossBuiltinSpecsDetector" keep-relative-paths="false" name="MCU ARM GCC Built-in Compiler Settings" parameter="${COMMAND} ${FLAGS} -E -P -v -dD &quot;${INPUTS}&quot;" prefer-non-shared="true">
+				<language-scope id="org.eclipse.cdt.core.gcc"/>
+				<language-scope id="org.eclipse.cdt.core.g++"/>
+			</provider>
+		</extension>
+	</configuration>
+</project>

.settings/org.eclipse.cdt.core.prefs

@@ -0,0 +1,6 @@
+doxygen/doxygen_new_line_after_brief=true
+doxygen/doxygen_use_brief_tag=false
+doxygen/doxygen_use_javadoc_tags=true
+doxygen/doxygen_use_pre_tag=false
+doxygen/doxygen_use_structural_commands=false
+eclipse.preferences.version=1

.settings/stm32cubeide.project.prefs

@@ -0,0 +1,4 @@
+2F62501ED4689FB349E356AB974DBE57=881FE7AA511113830F9800930850DB99
+8DF89ED150041C4CBC7CB9A9CAA90856=881FE7AA511113830F9800930850DB99
+DC22A860405A8BF2F2C095E5B6529F12=CBFEBD1BB4AE28C6197E95EA477EADDC
+eclipse.preferences.version=1

Core/Inc/can.h

@@ -0,0 +1,57 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    can.h
+  * @brief   This file contains all the function prototypes for
+  *          the can.c file
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2025 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __CAN_H__
+#define __CAN_H__
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "main.h"
+
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+extern CAN_HandleTypeDef hcan1;
+
+/* USER CODE BEGIN Private defines */
+
+/* USER CODE END Private defines */
+
+void MX_CAN1_Init(void);
+
+/* USER CODE BEGIN Prototypes */
+void CAN_Filter_config(void);
+void CAN_SendData(uint8_t canCom, uint32_t mailbox, uint32_t messageId, uint8_t * data, uint32_t len);
+
+extern CAN_TxHeaderTypeDef	TxHeader;      //发送
+extern CAN_RxHeaderTypeDef	RxHeader;      //接收
+
+/* USER CODE END Prototypes */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CAN_H__ */
+

Core/Inc/flash.h

@@ -0,0 +1,21 @@
+#ifndef INC_FLASH_H_
+#define INC_FLASH_H_
+
+/* Includes ------------------------------------------------------------------*/
+#include <stdint.h>
+#include <stdbool.h>
+#include "stm32f4xx_board.h"
+
+
+int flash_erase_page(uint32_t address);
+int flash_erase_pages(uint32_t address, uint32_t size);
+int flash_erase_app(uint8_t app_num);
+void app_status_set(uint8_t app_num,bool status);
+int flash_write_page(uint32_t target_addr, uint8_t *data, uint32_t length, bool erase);
+int flash_test(void);
+void app1_copy_to_app2(void);
+void app2_copy_to_app1(void);
+void jump_to_app(uint32_t app_addr);
+
+
+#endif /* INC_FLASH_H_ */

Core/Inc/gpio.h

@@ -0,0 +1,55 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    gpio.h
+  * @brief   This file contains all the function prototypes for
+  *          the gpio.c file
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2025 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __GPIO_H__
+#define __GPIO_H__
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "main.h"
+
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+/* USER CODE BEGIN Private defines */
+
+/* USER CODE END Private defines */
+
+void MX_GPIO_Init(void);
+
+/* USER CODE BEGIN Prototypes */
+#define BRAKE_R_SET_0 	HAL_GPIO_WritePin(GPIOB,GPIO_PIN_3,GPIO_PIN_RESET);
+#define BRAKE_L_SET_0 	HAL_GPIO_WritePin(GPIOC,GPIO_PIN_4,GPIO_PIN_RESET);
+#define BRAKE_R_SET_1 	HAL_GPIO_WritePin(GPIOB,GPIO_PIN_3,GPIO_PIN_SET);
+#define BRAKE_L_SET_1 	HAL_GPIO_WritePin(GPIOC,GPIO_PIN_4,GPIO_PIN_SET);
+
+#define BRAKE_R 		HAL_GPIO_ReadPin(GPIOA,GPIO_PIN_2)
+#define BRAKE_L	 		HAL_GPIO_ReadPin(GPIOA,GPIO_PIN_3)
+/* USER CODE END Prototypes */
+
+#ifdef __cplusplus
+}
+#endif
+#endif /*__ GPIO_H__ */
+

Core/Inc/main.h

@@ -0,0 +1,69 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file           : main.h
+  * @brief          : Header for main.c file.
+  *                   This file contains the common defines of the application.
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2025 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __MAIN_H
+#define __MAIN_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_hal.h"
+
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+/* Exported types ------------------------------------------------------------*/
+/* USER CODE BEGIN ET */
+
+/* USER CODE END ET */
+
+/* Exported constants --------------------------------------------------------*/
+/* USER CODE BEGIN EC */
+
+/* USER CODE END EC */
+
+/* Exported macro ------------------------------------------------------------*/
+/* USER CODE BEGIN EM */
+
+/* USER CODE END EM */
+
+/* Exported functions prototypes ---------------------------------------------*/
+void Error_Handler(void);
+
+/* USER CODE BEGIN EFP */
+
+/* USER CODE END EFP */
+
+/* Private defines -----------------------------------------------------------*/
+
+/* USER CODE BEGIN Private defines */
+
+/* USER CODE END Private defines */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __MAIN_H */

Core/Inc/stm32f4xx_board.h

@@ -0,0 +1,40 @@
+#ifndef INC_STM32F4XX_BOARD_H_
+#define INC_STM32F4XX_BOARD_H_
+#include "stm32f4xx.h"
+#include "stm32f4xx_hal.h"
+
+#define REG32(addr)                  (*(volatile uint32_t *)(uint32_t)(addr))
+#define REG16(addr)                  (*(volatile uint16_t *)(uint32_t)(addr))
+#define REG8(addr)                   (*(volatile uint8_t *)(uint32_t)(addr))
+
+#define BIT(x)        				 ((uint32_t)((uint32_t)0x01U<<(x)))
+#define BITS(start, end)             ((0xFFFFFFFFUL << (start)) & (0xFFFFFFFFUL >> (31U - (uint32_t)(end))))
+
+// Base address of the Flash sectors
+#define ADDR_FLASH_SECTOR_0     ((uint32_t)0x08000000) /* Base @ of Sector 0, 16 Kbytes */
+#define ADDR_FLASH_SECTOR_1     ((uint32_t)0x08004000) /* Base @ of Sector 1, 16 Kbytes */
+#define ADDR_FLASH_SECTOR_2     ((uint32_t)0x08008000) /* Base @ of Sector 2, 16 Kbytes */
+#define ADDR_FLASH_SECTOR_3     ((uint32_t)0x0800C000) /* Base @ of Sector 3, 16 Kbytes */
+#define ADDR_FLASH_SECTOR_4     ((uint32_t)0x08010000) /* Base @ of Sector 4, 64 Kbytes */
+#define ADDR_FLASH_SECTOR_5     ((uint32_t)0x08020000) /* Base @ of Sector 5, 128 Kbytes */
+#define ADDR_FLASH_SECTOR_6     ((uint32_t)0x08040000) /* Base @ of Sector 6, 128 Kbytes */
+#define ADDR_FLASH_SECTOR_7     ((uint32_t)0x08060000) /* Base @ of Sector 7, 128 Kbytes */
+#define ADDR_FLASH_SECTOR_8     ((uint32_t)0x08080000) /* Base @ of Sector 8, 128 Kbytes */
+#define ADDR_FLASH_SECTOR_9     ((uint32_t)0x080A0000) /* Base @ of Sector 9, 128 Kbytes */
+#define ADDR_FLASH_SECTOR_10    ((uint32_t)0x080C0000) /* Base @ of Sector 10, 128 Kbytes */
+#define ADDR_FLASH_SECTOR_11    ((uint32_t)0x080E0000) /* Base @ of Sector 11, 128 Kbytes */
+
+#define FLASH_END_ADDRESS       ((uint32_t)0x080EFFFF)
+
+#define APP1_ADDRESS			    ADDR_FLASH_SECTOR_3	//16+64+128+128 = 336k
+#define APP2_ADDRESS			    ADDR_FLASH_SECTOR_7	//128*3 = 384k
+
+#define CONFIG_IAP_INFO_SECTOR  FLASH_SECTOR_2
+#define CONFIG_IAP_INFO_ADDR    ADDR_FLASH_SECTOR_2
+
+#define CONFIG_NVM0_ADDRESS     ADDR_FLASH_SECTOR_10
+#define CONFIG_NVM1_ADDRESS     ADDR_FLASH_SECTOR_11
+#define CONFIG_NVM_SIZE         (2*128*1024)
+
+
+#endif /* INC_STM32F4XX_BOARD_H_ */

Core/Inc/stm32f4xx_hal_conf.h

@@ -0,0 +1,495 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    stm32f4xx_hal_conf_template.h
+  * @author  MCD Application Team
+  * @brief   HAL configuration template file.
+  *          This file should be copied to the application folder and renamed
+  *          to stm32f4xx_hal_conf.h.
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F4xx_HAL_CONF_H
+#define __STM32F4xx_HAL_CONF_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+
+/* ########################## Module Selection ############################## */
+/**
+  * @brief This is the list of modules to be used in the HAL driver
+  */
+#define HAL_MODULE_ENABLED
+
+  /* #define HAL_CRYP_MODULE_ENABLED */
+/* #define HAL_ADC_MODULE_ENABLED */
+#define HAL_CAN_MODULE_ENABLED
+/* #define HAL_CRC_MODULE_ENABLED */
+/* #define HAL_CAN_LEGACY_MODULE_ENABLED */
+/* #define HAL_DAC_MODULE_ENABLED */
+/* #define HAL_DCMI_MODULE_ENABLED */
+/* #define HAL_DMA2D_MODULE_ENABLED */
+/* #define HAL_ETH_MODULE_ENABLED */
+/* #define HAL_ETH_LEGACY_MODULE_ENABLED */
+/* #define HAL_NAND_MODULE_ENABLED */
+/* #define HAL_NOR_MODULE_ENABLED */
+/* #define HAL_PCCARD_MODULE_ENABLED */
+/* #define HAL_SRAM_MODULE_ENABLED */
+/* #define HAL_SDRAM_MODULE_ENABLED */
+/* #define HAL_HASH_MODULE_ENABLED */
+/* #define HAL_I2C_MODULE_ENABLED */
+/* #define HAL_I2S_MODULE_ENABLED */
+/* #define HAL_IWDG_MODULE_ENABLED */
+/* #define HAL_LTDC_MODULE_ENABLED */
+/* #define HAL_RNG_MODULE_ENABLED */
+/* #define HAL_RTC_MODULE_ENABLED */
+/* #define HAL_SAI_MODULE_ENABLED */
+/* #define HAL_SD_MODULE_ENABLED */
+/* #define HAL_MMC_MODULE_ENABLED */
+/* #define HAL_SPI_MODULE_ENABLED */
+#define HAL_TIM_MODULE_ENABLED
+/* #define HAL_UART_MODULE_ENABLED */
+/* #define HAL_USART_MODULE_ENABLED */
+/* #define HAL_IRDA_MODULE_ENABLED */
+/* #define HAL_SMARTCARD_MODULE_ENABLED */
+/* #define HAL_SMBUS_MODULE_ENABLED */
+/* #define HAL_WWDG_MODULE_ENABLED */
+/* #define HAL_PCD_MODULE_ENABLED */
+/* #define HAL_HCD_MODULE_ENABLED */
+/* #define HAL_DSI_MODULE_ENABLED */
+/* #define HAL_QSPI_MODULE_ENABLED */
+/* #define HAL_QSPI_MODULE_ENABLED */
+/* #define HAL_CEC_MODULE_ENABLED */
+/* #define HAL_FMPI2C_MODULE_ENABLED */
+/* #define HAL_FMPSMBUS_MODULE_ENABLED */
+/* #define HAL_SPDIFRX_MODULE_ENABLED */
+/* #define HAL_DFSDM_MODULE_ENABLED */
+/* #define HAL_LPTIM_MODULE_ENABLED */
+#define HAL_GPIO_MODULE_ENABLED
+#define HAL_EXTI_MODULE_ENABLED
+#define HAL_DMA_MODULE_ENABLED
+#define HAL_RCC_MODULE_ENABLED
+#define HAL_FLASH_MODULE_ENABLED
+#define HAL_PWR_MODULE_ENABLED
+#define HAL_CORTEX_MODULE_ENABLED
+
+/* ########################## HSE/HSI Values adaptation ##################### */
+/**
+  * @brief Adjust the value of External High Speed oscillator (HSE) used in your application.
+  *        This value is used by the RCC HAL module to compute the system frequency
+  *        (when HSE is used as system clock source, directly or through the PLL).
+  */
+#if !defined  (HSE_VALUE)
+  #define HSE_VALUE    8000000U /*!< Value of the External oscillator in Hz */
+#endif /* HSE_VALUE */
+
+#if !defined  (HSE_STARTUP_TIMEOUT)
+  #define HSE_STARTUP_TIMEOUT    100U   /*!< Time out for HSE start up, in ms */
+#endif /* HSE_STARTUP_TIMEOUT */
+
+/**
+  * @brief Internal High Speed oscillator (HSI) value.
+  *        This value is used by the RCC HAL module to compute the system frequency
+  *        (when HSI is used as system clock source, directly or through the PLL).
+  */
+#if !defined  (HSI_VALUE)
+  #define HSI_VALUE    ((uint32_t)16000000U) /*!< Value of the Internal oscillator in Hz*/
+#endif /* HSI_VALUE */
+
+/**
+  * @brief Internal Low Speed oscillator (LSI) value.
+  */
+#if !defined  (LSI_VALUE)
+ #define LSI_VALUE  32000U       /*!< LSI Typical Value in Hz*/
+#endif /* LSI_VALUE */                      /*!< Value of the Internal Low Speed oscillator in Hz
+                                             The real value may vary depending on the variations
+                                             in voltage and temperature.*/
+/**
+  * @brief External Low Speed oscillator (LSE) value.
+  */
+#if !defined  (LSE_VALUE)
+ #define LSE_VALUE  32768U    /*!< Value of the External Low Speed oscillator in Hz */
+#endif /* LSE_VALUE */
+
+#if !defined  (LSE_STARTUP_TIMEOUT)
+  #define LSE_STARTUP_TIMEOUT    5000U   /*!< Time out for LSE start up, in ms */
+#endif /* LSE_STARTUP_TIMEOUT */
+
+/**
+  * @brief External clock source for I2S peripheral
+  *        This value is used by the I2S HAL module to compute the I2S clock source
+  *        frequency, this source is inserted directly through I2S_CKIN pad.
+  */
+#if !defined  (EXTERNAL_CLOCK_VALUE)
+  #define EXTERNAL_CLOCK_VALUE    12288000U /*!< Value of the External audio frequency in Hz*/
+#endif /* EXTERNAL_CLOCK_VALUE */
+
+/* Tip: To avoid modifying this file each time you need to use different HSE,
+   ===  you can define the HSE value in your toolchain compiler preprocessor. */
+
+/* ########################### System Configuration ######################### */
+/**
+  * @brief This is the HAL system configuration section
+  */
+#define  VDD_VALUE		      3300U /*!< Value of VDD in mv */
+#define  TICK_INT_PRIORITY            15U   /*!< tick interrupt priority */
+#define  USE_RTOS                     0U
+#define  PREFETCH_ENABLE              1U
+#define  INSTRUCTION_CACHE_ENABLE     1U
+#define  DATA_CACHE_ENABLE            1U
+
+#define  USE_HAL_ADC_REGISTER_CALLBACKS         0U /* ADC register callback disabled       */
+#define  USE_HAL_CAN_REGISTER_CALLBACKS         0U /* CAN register callback disabled       */
+#define  USE_HAL_CEC_REGISTER_CALLBACKS         0U /* CEC register callback disabled       */
+#define  USE_HAL_CRYP_REGISTER_CALLBACKS        0U /* CRYP register callback disabled      */
+#define  USE_HAL_DAC_REGISTER_CALLBACKS         0U /* DAC register callback disabled       */
+#define  USE_HAL_DCMI_REGISTER_CALLBACKS        0U /* DCMI register callback disabled      */
+#define  USE_HAL_DFSDM_REGISTER_CALLBACKS       0U /* DFSDM register callback disabled     */
+#define  USE_HAL_DMA2D_REGISTER_CALLBACKS       0U /* DMA2D register callback disabled     */
+#define  USE_HAL_DSI_REGISTER_CALLBACKS         0U /* DSI register callback disabled       */
+#define  USE_HAL_ETH_REGISTER_CALLBACKS         0U /* ETH register callback disabled       */
+#define  USE_HAL_HASH_REGISTER_CALLBACKS        0U /* HASH register callback disabled      */
+#define  USE_HAL_HCD_REGISTER_CALLBACKS         0U /* HCD register callback disabled       */
+#define  USE_HAL_I2C_REGISTER_CALLBACKS         0U /* I2C register callback disabled       */
+#define  USE_HAL_FMPI2C_REGISTER_CALLBACKS      0U /* FMPI2C register callback disabled    */
+#define  USE_HAL_FMPSMBUS_REGISTER_CALLBACKS    0U /* FMPSMBUS register callback disabled  */
+#define  USE_HAL_I2S_REGISTER_CALLBACKS         0U /* I2S register callback disabled       */
+#define  USE_HAL_IRDA_REGISTER_CALLBACKS        0U /* IRDA register callback disabled      */
+#define  USE_HAL_LPTIM_REGISTER_CALLBACKS       0U /* LPTIM register callback disabled     */
+#define  USE_HAL_LTDC_REGISTER_CALLBACKS        0U /* LTDC register callback disabled      */
+#define  USE_HAL_MMC_REGISTER_CALLBACKS         0U /* MMC register callback disabled       */
+#define  USE_HAL_NAND_REGISTER_CALLBACKS        0U /* NAND register callback disabled      */
+#define  USE_HAL_NOR_REGISTER_CALLBACKS         0U /* NOR register callback disabled       */
+#define  USE_HAL_PCCARD_REGISTER_CALLBACKS      0U /* PCCARD register callback disabled    */
+#define  USE_HAL_PCD_REGISTER_CALLBACKS         0U /* PCD register callback disabled       */
+#define  USE_HAL_QSPI_REGISTER_CALLBACKS        0U /* QSPI register callback disabled      */
+#define  USE_HAL_RNG_REGISTER_CALLBACKS         0U /* RNG register callback disabled       */
+#define  USE_HAL_RTC_REGISTER_CALLBACKS         0U /* RTC register callback disabled       */
+#define  USE_HAL_SAI_REGISTER_CALLBACKS         0U /* SAI register callback disabled       */
+#define  USE_HAL_SD_REGISTER_CALLBACKS          0U /* SD register callback disabled        */
+#define  USE_HAL_SMARTCARD_REGISTER_CALLBACKS   0U /* SMARTCARD register callback disabled */
+#define  USE_HAL_SDRAM_REGISTER_CALLBACKS       0U /* SDRAM register callback disabled     */
+#define  USE_HAL_SRAM_REGISTER_CALLBACKS        0U /* SRAM register callback disabled      */
+#define  USE_HAL_SPDIFRX_REGISTER_CALLBACKS     0U /* SPDIFRX register callback disabled   */
+#define  USE_HAL_SMBUS_REGISTER_CALLBACKS       0U /* SMBUS register callback disabled     */
+#define  USE_HAL_SPI_REGISTER_CALLBACKS         0U /* SPI register callback disabled       */
+#define  USE_HAL_TIM_REGISTER_CALLBACKS         0U /* TIM register callback disabled       */
+#define  USE_HAL_UART_REGISTER_CALLBACKS        0U /* UART register callback disabled      */
+#define  USE_HAL_USART_REGISTER_CALLBACKS       0U /* USART register callback disabled     */
+#define  USE_HAL_WWDG_REGISTER_CALLBACKS        0U /* WWDG register callback disabled      */
+
+/* ########################## Assert Selection ############################## */
+/**
+  * @brief Uncomment the line below to expanse the "assert_param" macro in the
+  *        HAL drivers code
+  */
+/* #define USE_FULL_ASSERT    1U */
+
+/* ################## Ethernet peripheral configuration ##################### */
+
+/* Section 1 : Ethernet peripheral configuration */
+
+/* MAC ADDRESS: MAC_ADDR0:MAC_ADDR1:MAC_ADDR2:MAC_ADDR3:MAC_ADDR4:MAC_ADDR5 */
+#define MAC_ADDR0   2U
+#define MAC_ADDR1   0U
+#define MAC_ADDR2   0U
+#define MAC_ADDR3   0U
+#define MAC_ADDR4   0U
+#define MAC_ADDR5   0U
+
+/* Definition of the Ethernet driver buffers size and count */
+#define ETH_RX_BUF_SIZE                ETH_MAX_PACKET_SIZE /* buffer size for receive               */
+#define ETH_TX_BUF_SIZE                ETH_MAX_PACKET_SIZE /* buffer size for transmit              */
+#define ETH_RXBUFNB                    4U       /* 4 Rx buffers of size ETH_RX_BUF_SIZE  */
+#define ETH_TXBUFNB                    4U       /* 4 Tx buffers of size ETH_TX_BUF_SIZE  */
+
+/* Section 2: PHY configuration section */
+
+/* DP83848_PHY_ADDRESS Address*/
+#define DP83848_PHY_ADDRESS
+/* PHY Reset delay these values are based on a 1 ms Systick interrupt*/
+#define PHY_RESET_DELAY                 0x000000FFU
+/* PHY Configuration delay */
+#define PHY_CONFIG_DELAY                0x00000FFFU
+
+#define PHY_READ_TO                     0x0000FFFFU
+#define PHY_WRITE_TO                    0x0000FFFFU
+
+/* Section 3: Common PHY Registers */
+
+#define PHY_BCR                         ((uint16_t)0x0000U)    /*!< Transceiver Basic Control Register   */
+#define PHY_BSR                         ((uint16_t)0x0001U)    /*!< Transceiver Basic Status Register    */
+
+#define PHY_RESET                       ((uint16_t)0x8000U)  /*!< PHY Reset */
+#define PHY_LOOPBACK                    ((uint16_t)0x4000U)  /*!< Select loop-back mode */
+#define PHY_FULLDUPLEX_100M             ((uint16_t)0x2100U)  /*!< Set the full-duplex mode at 100 Mb/s */
+#define PHY_HALFDUPLEX_100M             ((uint16_t)0x2000U)  /*!< Set the half-duplex mode at 100 Mb/s */
+#define PHY_FULLDUPLEX_10M              ((uint16_t)0x0100U)  /*!< Set the full-duplex mode at 10 Mb/s  */
+#define PHY_HALFDUPLEX_10M              ((uint16_t)0x0000U)  /*!< Set the half-duplex mode at 10 Mb/s  */
+#define PHY_AUTONEGOTIATION             ((uint16_t)0x1000U)  /*!< Enable auto-negotiation function     */
+#define PHY_RESTART_AUTONEGOTIATION     ((uint16_t)0x0200U)  /*!< Restart auto-negotiation function    */
+#define PHY_POWERDOWN                   ((uint16_t)0x0800U)  /*!< Select the power down mode           */
+#define PHY_ISOLATE                     ((uint16_t)0x0400U)  /*!< Isolate PHY from MII                 */
+
+#define PHY_AUTONEGO_COMPLETE           ((uint16_t)0x0020U)  /*!< Auto-Negotiation process completed   */
+#define PHY_LINKED_STATUS               ((uint16_t)0x0004U)  /*!< Valid link established               */
+#define PHY_JABBER_DETECTION            ((uint16_t)0x0002U)  /*!< Jabber condition detected            */
+
+/* Section 4: Extended PHY Registers */
+#define PHY_SR                          ((uint16_t))    /*!< PHY status register Offset                      */
+
+#define PHY_SPEED_STATUS                ((uint16_t))  /*!< PHY Speed mask                                  */
+#define PHY_DUPLEX_STATUS               ((uint16_t))  /*!< PHY Duplex mask                                 */
+
+/* ################## SPI peripheral configuration ########################## */
+
+/* CRC FEATURE: Use to activate CRC feature inside HAL SPI Driver
+* Activated: CRC code is present inside driver
+* Deactivated: CRC code cleaned from driver
+*/
+
+#define USE_SPI_CRC                     0U
+
+/* Includes ------------------------------------------------------------------*/
+/**
+  * @brief Include module's header file
+  */
+
+#ifdef HAL_RCC_MODULE_ENABLED
+  #include "stm32f4xx_hal_rcc.h"
+#endif /* HAL_RCC_MODULE_ENABLED */
+
+#ifdef HAL_GPIO_MODULE_ENABLED
+  #include "stm32f4xx_hal_gpio.h"
+#endif /* HAL_GPIO_MODULE_ENABLED */
+
+#ifdef HAL_EXTI_MODULE_ENABLED
+  #include "stm32f4xx_hal_exti.h"
+#endif /* HAL_EXTI_MODULE_ENABLED */
+
+#ifdef HAL_DMA_MODULE_ENABLED
+  #include "stm32f4xx_hal_dma.h"
+#endif /* HAL_DMA_MODULE_ENABLED */
+
+#ifdef HAL_CORTEX_MODULE_ENABLED
+  #include "stm32f4xx_hal_cortex.h"
+#endif /* HAL_CORTEX_MODULE_ENABLED */
+
+#ifdef HAL_ADC_MODULE_ENABLED
+  #include "stm32f4xx_hal_adc.h"
+#endif /* HAL_ADC_MODULE_ENABLED */
+
+#ifdef HAL_CAN_MODULE_ENABLED
+  #include "stm32f4xx_hal_can.h"
+#endif /* HAL_CAN_MODULE_ENABLED */
+
+#ifdef HAL_CAN_LEGACY_MODULE_ENABLED
+  #include "stm32f4xx_hal_can_legacy.h"
+#endif /* HAL_CAN_LEGACY_MODULE_ENABLED */
+
+#ifdef HAL_CRC_MODULE_ENABLED
+  #include "stm32f4xx_hal_crc.h"
+#endif /* HAL_CRC_MODULE_ENABLED */
+
+#ifdef HAL_CRYP_MODULE_ENABLED
+  #include "stm32f4xx_hal_cryp.h"
+#endif /* HAL_CRYP_MODULE_ENABLED */
+
+#ifdef HAL_DMA2D_MODULE_ENABLED
+  #include "stm32f4xx_hal_dma2d.h"
+#endif /* HAL_DMA2D_MODULE_ENABLED */
+
+#ifdef HAL_DAC_MODULE_ENABLED
+  #include "stm32f4xx_hal_dac.h"
+#endif /* HAL_DAC_MODULE_ENABLED */
+
+#ifdef HAL_DCMI_MODULE_ENABLED
+  #include "stm32f4xx_hal_dcmi.h"
+#endif /* HAL_DCMI_MODULE_ENABLED */
+
+#ifdef HAL_ETH_MODULE_ENABLED
+  #include "stm32f4xx_hal_eth.h"
+#endif /* HAL_ETH_MODULE_ENABLED */
+
+#ifdef HAL_ETH_LEGACY_MODULE_ENABLED
+  #include "stm32f4xx_hal_eth_legacy.h"
+#endif /* HAL_ETH_LEGACY_MODULE_ENABLED */
+
+#ifdef HAL_FLASH_MODULE_ENABLED
+  #include "stm32f4xx_hal_flash.h"
+#endif /* HAL_FLASH_MODULE_ENABLED */
+
+#ifdef HAL_SRAM_MODULE_ENABLED
+  #include "stm32f4xx_hal_sram.h"
+#endif /* HAL_SRAM_MODULE_ENABLED */
+
+#ifdef HAL_NOR_MODULE_ENABLED
+  #include "stm32f4xx_hal_nor.h"
+#endif /* HAL_NOR_MODULE_ENABLED */
+
+#ifdef HAL_NAND_MODULE_ENABLED
+  #include "stm32f4xx_hal_nand.h"
+#endif /* HAL_NAND_MODULE_ENABLED */
+
+#ifdef HAL_PCCARD_MODULE_ENABLED
+  #include "stm32f4xx_hal_pccard.h"
+#endif /* HAL_PCCARD_MODULE_ENABLED */
+
+#ifdef HAL_SDRAM_MODULE_ENABLED
+  #include "stm32f4xx_hal_sdram.h"
+#endif /* HAL_SDRAM_MODULE_ENABLED */
+
+#ifdef HAL_HASH_MODULE_ENABLED
+ #include "stm32f4xx_hal_hash.h"
+#endif /* HAL_HASH_MODULE_ENABLED */
+
+#ifdef HAL_I2C_MODULE_ENABLED
+ #include "stm32f4xx_hal_i2c.h"
+#endif /* HAL_I2C_MODULE_ENABLED */
+
+#ifdef HAL_SMBUS_MODULE_ENABLED
+ #include "stm32f4xx_hal_smbus.h"
+#endif /* HAL_SMBUS_MODULE_ENABLED */
+
+#ifdef HAL_I2S_MODULE_ENABLED
+ #include "stm32f4xx_hal_i2s.h"
+#endif /* HAL_I2S_MODULE_ENABLED */
+
+#ifdef HAL_IWDG_MODULE_ENABLED
+ #include "stm32f4xx_hal_iwdg.h"
+#endif /* HAL_IWDG_MODULE_ENABLED */
+
+#ifdef HAL_LTDC_MODULE_ENABLED
+ #include "stm32f4xx_hal_ltdc.h"
+#endif /* HAL_LTDC_MODULE_ENABLED */
+
+#ifdef HAL_PWR_MODULE_ENABLED
+ #include "stm32f4xx_hal_pwr.h"
+#endif /* HAL_PWR_MODULE_ENABLED */
+
+#ifdef HAL_RNG_MODULE_ENABLED
+ #include "stm32f4xx_hal_rng.h"
+#endif /* HAL_RNG_MODULE_ENABLED */
+
+#ifdef HAL_RTC_MODULE_ENABLED
+ #include "stm32f4xx_hal_rtc.h"
+#endif /* HAL_RTC_MODULE_ENABLED */
+
+#ifdef HAL_SAI_MODULE_ENABLED
+ #include "stm32f4xx_hal_sai.h"
+#endif /* HAL_SAI_MODULE_ENABLED */
+
+#ifdef HAL_SD_MODULE_ENABLED
+ #include "stm32f4xx_hal_sd.h"
+#endif /* HAL_SD_MODULE_ENABLED */
+
+#ifdef HAL_SPI_MODULE_ENABLED
+ #include "stm32f4xx_hal_spi.h"
+#endif /* HAL_SPI_MODULE_ENABLED */
+
+#ifdef HAL_TIM_MODULE_ENABLED
+ #include "stm32f4xx_hal_tim.h"
+#endif /* HAL_TIM_MODULE_ENABLED */
+
+#ifdef HAL_UART_MODULE_ENABLED
+ #include "stm32f4xx_hal_uart.h"
+#endif /* HAL_UART_MODULE_ENABLED */
+
+#ifdef HAL_USART_MODULE_ENABLED
+ #include "stm32f4xx_hal_usart.h"
+#endif /* HAL_USART_MODULE_ENABLED */
+
+#ifdef HAL_IRDA_MODULE_ENABLED
+ #include "stm32f4xx_hal_irda.h"
+#endif /* HAL_IRDA_MODULE_ENABLED */
+
+#ifdef HAL_SMARTCARD_MODULE_ENABLED
+ #include "stm32f4xx_hal_smartcard.h"
+#endif /* HAL_SMARTCARD_MODULE_ENABLED */
+
+#ifdef HAL_WWDG_MODULE_ENABLED
+ #include "stm32f4xx_hal_wwdg.h"
+#endif /* HAL_WWDG_MODULE_ENABLED */
+
+#ifdef HAL_PCD_MODULE_ENABLED
+ #include "stm32f4xx_hal_pcd.h"
+#endif /* HAL_PCD_MODULE_ENABLED */
+
+#ifdef HAL_HCD_MODULE_ENABLED
+ #include "stm32f4xx_hal_hcd.h"
+#endif /* HAL_HCD_MODULE_ENABLED */
+
+#ifdef HAL_DSI_MODULE_ENABLED
+ #include "stm32f4xx_hal_dsi.h"
+#endif /* HAL_DSI_MODULE_ENABLED */
+
+#ifdef HAL_QSPI_MODULE_ENABLED
+ #include "stm32f4xx_hal_qspi.h"
+#endif /* HAL_QSPI_MODULE_ENABLED */
+
+#ifdef HAL_CEC_MODULE_ENABLED
+ #include "stm32f4xx_hal_cec.h"
+#endif /* HAL_CEC_MODULE_ENABLED */
+
+#ifdef HAL_FMPI2C_MODULE_ENABLED
+ #include "stm32f4xx_hal_fmpi2c.h"
+#endif /* HAL_FMPI2C_MODULE_ENABLED */
+
+#ifdef HAL_FMPSMBUS_MODULE_ENABLED
+ #include "stm32f4xx_hal_fmpsmbus.h"
+#endif /* HAL_FMPSMBUS_MODULE_ENABLED */
+
+#ifdef HAL_SPDIFRX_MODULE_ENABLED
+ #include "stm32f4xx_hal_spdifrx.h"
+#endif /* HAL_SPDIFRX_MODULE_ENABLED */
+
+#ifdef HAL_DFSDM_MODULE_ENABLED
+ #include "stm32f4xx_hal_dfsdm.h"
+#endif /* HAL_DFSDM_MODULE_ENABLED */
+
+#ifdef HAL_LPTIM_MODULE_ENABLED
+ #include "stm32f4xx_hal_lptim.h"
+#endif /* HAL_LPTIM_MODULE_ENABLED */
+
+#ifdef HAL_MMC_MODULE_ENABLED
+ #include "stm32f4xx_hal_mmc.h"
+#endif /* HAL_MMC_MODULE_ENABLED */
+
+/* Exported macro ------------------------------------------------------------*/
+#ifdef  USE_FULL_ASSERT
+/**
+  * @brief  The assert_param macro is used for function's parameters check.
+  * @param  expr If expr is false, it calls assert_failed function
+  *         which reports the name of the source file and the source
+  *         line number of the call that failed.
+  *         If expr is true, it returns no value.
+  * @retval None
+  */
+  #define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__))
+/* Exported functions ------------------------------------------------------- */
+  void assert_failed(uint8_t* file, uint32_t line);
+#else
+  #define assert_param(expr) ((void)0U)
+#endif /* USE_FULL_ASSERT */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F4xx_HAL_CONF_H */

Core/Inc/stm32f4xx_it.h

@@ -0,0 +1,68 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    stm32f4xx_it.h
+  * @brief   This file contains the headers of the interrupt handlers.
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2025 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F4xx_IT_H
+#define __STM32F4xx_IT_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+/* Exported types ------------------------------------------------------------*/
+/* USER CODE BEGIN ET */
+
+/* USER CODE END ET */
+
+/* Exported constants --------------------------------------------------------*/
+/* USER CODE BEGIN EC */
+
+/* USER CODE END EC */
+
+/* Exported macro ------------------------------------------------------------*/
+/* USER CODE BEGIN EM */
+
+/* USER CODE END EM */
+
+/* Exported functions prototypes ---------------------------------------------*/
+void NMI_Handler(void);
+void HardFault_Handler(void);
+void MemManage_Handler(void);
+void BusFault_Handler(void);
+void UsageFault_Handler(void);
+void SVC_Handler(void);
+void DebugMon_Handler(void);
+void PendSV_Handler(void);
+void SysTick_Handler(void);
+void CAN1_RX0_IRQHandler(void);
+void TIM2_IRQHandler(void);
+/* USER CODE BEGIN EFP */
+
+/* USER CODE END EFP */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F4xx_IT_H */

Core/Inc/tim.h

@@ -0,0 +1,52 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    tim.h
+  * @brief   This file contains all the function prototypes for
+  *          the tim.c file
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2025 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __TIM_H__
+#define __TIM_H__
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "main.h"
+
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+extern TIM_HandleTypeDef htim2;
+
+/* USER CODE BEGIN Private defines */
+
+/* USER CODE END Private defines */
+
+void MX_TIM2_Init(void);
+
+/* USER CODE BEGIN Prototypes */
+
+/* USER CODE END Prototypes */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __TIM_H__ */
+

Core/Src/can.c

@@ -0,0 +1,254 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    can.c
+  * @brief   This file provides code for the configuration
+  *          of the CAN instances.
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2025 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+/* Includes ------------------------------------------------------------------*/
+#include "can.h"
+
+/* USER CODE BEGIN 0 */
+#include "UDS.h"
+
+CAN_TxHeaderTypeDef	TxHeader;      //发送
+CAN_RxHeaderTypeDef	RxHeader;      //接收
+
+/* USER CODE END 0 */
+
+CAN_HandleTypeDef hcan1;
+
+/* CAN1 init function */
+void MX_CAN1_Init(void)
+{
+
+  /* USER CODE BEGIN CAN1_Init 0 */
+
+  /* USER CODE END CAN1_Init 0 */
+
+  /* USER CODE BEGIN CAN1_Init 1 */
+
+  /* USER CODE END CAN1_Init 1 */
+  hcan1.Instance = CAN1;
+//  hcan1.Init.Prescaler = 12;//250k
+  hcan1.Init.Prescaler = 6;//500k
+//  hcan1.Init.Prescaler = 3;//1000k
+  hcan1.Init.Mode = CAN_MODE_NORMAL;
+  hcan1.Init.SyncJumpWidth = CAN_SJW_1TQ;
+  hcan1.Init.TimeSeg1 = CAN_BS1_11TQ;
+  hcan1.Init.TimeSeg2 = CAN_BS2_2TQ;
+  hcan1.Init.TimeTriggeredMode = DISABLE;
+  hcan1.Init.AutoBusOff = ENABLE;
+  hcan1.Init.AutoWakeUp = ENABLE;
+  hcan1.Init.AutoRetransmission = ENABLE;
+  hcan1.Init.ReceiveFifoLocked = DISABLE;
+  hcan1.Init.TransmitFifoPriority = DISABLE;
+  if (HAL_CAN_Init(&hcan1) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  /* USER CODE BEGIN CAN1_Init 2 */
+
+  /* USER CODE END CAN1_Init 2 */
+
+}
+
+void HAL_CAN_MspInit(CAN_HandleTypeDef* canHandle)
+{
+
+  GPIO_InitTypeDef GPIO_InitStruct = {0};
+  if(canHandle->Instance==CAN1)
+  {
+  /* USER CODE BEGIN CAN1_MspInit 0 */
+
+  /* USER CODE END CAN1_MspInit 0 */
+    /* CAN1 clock enable */
+    __HAL_RCC_CAN1_CLK_ENABLE();
+
+    __HAL_RCC_GPIOB_CLK_ENABLE();
+    /**CAN1 GPIO Configuration
+    PB8     ------> CAN1_RX
+    PB9     ------> CAN1_TX
+    */
+    GPIO_InitStruct.Pin = GPIO_PIN_8|GPIO_PIN_9;
+    GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
+    GPIO_InitStruct.Pull = GPIO_NOPULL;
+    GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
+    GPIO_InitStruct.Alternate = GPIO_AF9_CAN1;
+    HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
+
+    /* CAN1 interrupt Init */
+    HAL_NVIC_SetPriority(CAN1_RX0_IRQn, 0, 0);
+    HAL_NVIC_EnableIRQ(CAN1_RX0_IRQn);
+  /* USER CODE BEGIN CAN1_MspInit 1 */
+
+  /* USER CODE END CAN1_MspInit 1 */
+  }
+}
+
+void HAL_CAN_MspDeInit(CAN_HandleTypeDef* canHandle)
+{
+
+  if(canHandle->Instance==CAN1)
+  {
+  /* USER CODE BEGIN CAN1_MspDeInit 0 */
+
+  /* USER CODE END CAN1_MspDeInit 0 */
+    /* Peripheral clock disable */
+    __HAL_RCC_CAN1_CLK_DISABLE();
+
+    /**CAN1 GPIO Configuration
+    PB8     ------> CAN1_RX
+    PB9     ------> CAN1_TX
+    */
+    HAL_GPIO_DeInit(GPIOB, GPIO_PIN_8|GPIO_PIN_9);
+
+    /* CAN1 interrupt Deinit */
+    HAL_NVIC_DisableIRQ(CAN1_RX0_IRQn);
+  /* USER CODE BEGIN CAN1_MspDeInit 1 */
+
+  /* USER CODE END CAN1_MspDeInit 1 */
+  }
+}
+
+/* USER CODE BEGIN 1 */
+
+extern uint8_t app2_crc_flag;//crc校验成功标志位，成功后应答版本号位新的。
+
+uint16_t get_hardware_version(void) {
+    return *(volatile uint16_t*)(0x08000188);
+}
+
+// 获取版本信息的函数
+uint32_t get_software_version(void) {
+
+    if(*(volatile uint32_t*)0x0800C188 == 0xFFFFFFFF)
+    {
+        return *(volatile uint32_t*)0x08060188;
+    }
+    else
+    {
+        return *(volatile uint32_t*)0x0800C188;
+    }
+}
+
+uint32_t get_publish_data(void) {
+    if(*(volatile uint32_t*)(0x0800C188+4) == 0xFFFFFFFF)
+    {
+        return *(volatile uint32_t*)(0x08060188+4);
+    }
+    else
+    {
+        return *(volatile uint32_t*)(0x0800C188+4);
+    }
+}
+
+void CAN_Filter_config(void)
+{
+    CAN_FilterTypeDef sFilterConfig;
+
+    /* 配置CAN过滤器 */
+    sFilterConfig.FilterBank = 0;                             /* 过滤器0 */
+    sFilterConfig.FilterMode = CAN_FILTERMODE_IDMASK;
+    sFilterConfig.FilterScale = CAN_FILTERSCALE_32BIT;
+    sFilterConfig.FilterIdHigh = 0x0000;                      /* 32位ID */
+    sFilterConfig.FilterIdLow = 0x0000;
+    sFilterConfig.FilterMaskIdHigh = 0x0000;                  /* 32位MASK */
+    sFilterConfig.FilterMaskIdLow = 0x0000;
+    sFilterConfig.FilterFIFOAssignment = CAN_FILTER_FIFO0;    /* 过滤器0关联到FIFO0 */
+    sFilterConfig.FilterActivation = CAN_FILTER_ENABLE;       /* 激活滤波器0 */
+    sFilterConfig.SlaveStartFilterBank = 14;
+
+    /* 过滤器配置 */
+    if (HAL_CAN_ConfigFilter(&hcan1, &sFilterConfig) != HAL_OK)
+    {
+        Error_Handler();
+    }
+	HAL_CAN_Start(&hcan1);//开启CAN
+	HAL_CAN_ActivateNotification(&hcan1 ,CAN_IT_RX_FIFO0_MSG_PENDING);//开启CAN的中断
+}
+
+void CAN_SendData(uint8_t canCom, uint32_t mailbox, uint32_t messageId, uint8_t * data, uint32_t len)
+{
+	uint32_t start_time = HAL_GetTick();  // 使用系统时间戳，更精确
+	uint32_t TxMailbox = CAN_TX_MAILBOX0;
+
+    TxHeader.StdId = messageId;         /* 标准标识符 */
+    TxHeader.ExtId = messageId;         /* 扩展标识符(29位) */
+    TxHeader.IDE = CAN_ID_EXT;   /* 使用标准帧 or 扩展帧 */
+    TxHeader.RTR = CAN_RTR_DATA; /* 数据帧 */
+    if(len > 8)
+    {
+    	len=8;
+    }
+    TxHeader.DLC = len;
+
+    if (HAL_CAN_AddTxMessage(&hcan1 , &TxHeader, data, &TxMailbox) != HAL_OK) /* 发送消息 */
+    {
+        //return 1;
+    }
+
+    // 超时时间：100ms
+	while (HAL_CAN_IsTxMessagePending(&hcan1, TxMailbox))
+    {
+		if (HAL_GetTick() - start_time > 100)  // 100ms超时
+        {
+            HAL_CAN_AbortTxRequest(&hcan1, TxMailbox);     /* 超时，直接中止邮箱的发送请求 */
+            //return 1;
+        }
+    }
+
+    //return 0;
+
+}
+/*CAN接收中断函数*/
+void HAL_CAN_RxFifo0MsgPendingCallback(CAN_HandleTypeDef *hcan){
+	uint8_t RxData[8];
+	if(hcan->Instance == CAN1){
+		HAL_CAN_GetRxMessage(&hcan1, CAN_RX_FIFO0, &RxHeader, RxData);
+		if (RxHeader.ExtId == 0x701 && RxHeader.IDE == CAN_ID_EXT) {
+			can_rx_isr_i(0,RxHeader.ExtId,RxData, RxHeader.DLC);
+			//can_rx_isr_i(0,,id,data,len);
+		}
+		//读取版本号
+		if (RxHeader.ExtId == 0x21D && RxHeader.IDE == CAN_ID_EXT) {
+		    uint16_t hardware_version = get_hardware_version();
+		    uint16_t software_version;
+			if(app2_crc_flag == 1)//crc校验成功标志位，成功后应答版本号位新的。
+			{
+				software_version = *(volatile uint32_t*)0x08060188;
+			}
+			else
+			{
+				software_version = *(volatile uint32_t*)0x0800C188;
+			}
+
+		    uint32_t publish_data = get_publish_data();
+
+		    uint8_t version[8];
+		    version[0] = hardware_version >> 8;
+		    version[1] = hardware_version & 0xFF;
+		    version[2] = software_version >> 8;
+		    version[3] = software_version & 0xFF;
+		    version[4] = publish_data >> 24;
+		    version[5] = publish_data >> 16;
+		    version[6] = publish_data >> 8;
+		    version[7] = publish_data & 0xFF;
+		    CAN_SendData(1, 2, 0x21D, version,8);
+		}
+	}
+}
+
+/* USER CODE END 1 */

Core/Src/flash.c

@@ -0,0 +1,443 @@
+/*
+* Flash-based Non-Volatile Memory (NVM)
+*
+* This file supports storing and loading persistent configuration based on
+* the STM32 builtin flash memory.
+*
+* The STM32F405xx has 12 flash sectors of heterogeneous size. We use the last
+* two sectors for configuration data. These pages have a size of 128kB each.
+* Setting any bit in these sectors to 0 is always possible, but setting them
+* to 1 requires erasing the whole sector.
+*
+* We consider each sector as an array of 64-bit fields except the first N bytes, which we
+* instead use as an allocation block. The allocation block is a compact bit-field (2 bit per entry)
+* that keeps track of the state of each field (erased, invalid, valid).
+*
+* One sector is always considered the valid (read) sector and the other one is the
+* target for the next write access: they can be considered to be ping-pong or double buffred.
+*
+* When writing a block of data, instead of always erasing the whole writable sector the
+* new data is appended in the erased area. This presumably increases flash life span.
+* The writable sector is only erased if there is not enough space for the new data.
+*
+* On startup, if there is exactly one sector
+* whose last non-erased value has the state "valid" that sector is considered
+* the valid sector. In any other case the selection is undefined.
+*
+*
+* To write a new block of data atomically we first mark all associated fields
+* as "invalid" (in the allocation table) then write the data and then mark the
+* fields as "valid" (in the direction of increasing address).
+*/
+#include <string.h>
+#include <stdbool.h>
+//#include <types.h>
+#include "flash.h"
+#include "stm32f405xx.h"
+#include "stm32f4xx_board.h"
+
+#include "can.h"
+
+//#include "main.h"
+//#include "tim.h"
+//#include "gpio.h"
+
+
+
+#define K(v) (v<<10)
+
+static uint32_t sectors_size[12] = {K(16), K(16), K(16), K(16), K(64), K(128), K(128), K(128), K(128), K(128), K(128), K(128)};
+
+static const uint32_t FLASH_ERR_FLAGS =
+#if defined(FLASH_FLAG_EOP)
+        FLASH_FLAG_EOP |
+#endif
+#if defined(FLASH_FLAG_OPERR)
+        FLASH_FLAG_OPERR |
+#endif
+#if defined(FLASH_FLAG_WRPERR)
+        FLASH_FLAG_WRPERR |
+#endif
+#if defined(FLASH_FLAG_PGAERR)
+        FLASH_FLAG_PGAERR |
+#endif
+#if defined(FLASH_FLAG_PGSERR)
+        FLASH_FLAG_PGSERR |
+#endif
+#if defined(FLASH_FLAG_PGPERR)
+        FLASH_FLAG_PGPERR |
+#endif
+        0;
+
+void HAL_FLASH_ClearError() {
+    __HAL_FLASH_CLEAR_FLAG(FLASH_ERR_FLAGS);
+}
+
+static uint32_t _sector_frame_address(uint32_t Address)
+{
+  uint32_t sector = 0;
+
+  if((Address < ADDR_FLASH_SECTOR_1) && (Address >= ADDR_FLASH_SECTOR_0))
+  {
+    sector = FLASH_SECTOR_0;
+  }
+  else if((Address < ADDR_FLASH_SECTOR_2) && (Address >= ADDR_FLASH_SECTOR_1))
+  {
+    sector = FLASH_SECTOR_1;
+  }
+  else if((Address < ADDR_FLASH_SECTOR_3) && (Address >= ADDR_FLASH_SECTOR_2))
+  {
+    sector = FLASH_SECTOR_2;
+  }
+  else if((Address < ADDR_FLASH_SECTOR_4) && (Address >= ADDR_FLASH_SECTOR_3))
+  {
+    sector = FLASH_SECTOR_3;
+  }
+  else if((Address < ADDR_FLASH_SECTOR_5) && (Address >= ADDR_FLASH_SECTOR_4))
+  {
+    sector = FLASH_SECTOR_4;
+  }
+  else if((Address < ADDR_FLASH_SECTOR_6) && (Address >= ADDR_FLASH_SECTOR_5))
+  {
+    sector = FLASH_SECTOR_5;
+  }
+  else if((Address < ADDR_FLASH_SECTOR_7) && (Address >= ADDR_FLASH_SECTOR_6))
+  {
+    sector = FLASH_SECTOR_6;
+  }
+  else if((Address < ADDR_FLASH_SECTOR_8) && (Address >= ADDR_FLASH_SECTOR_7))
+  {
+    sector = FLASH_SECTOR_7;
+  }
+  else if((Address < ADDR_FLASH_SECTOR_9) && (Address >= ADDR_FLASH_SECTOR_8))
+  {
+    sector = FLASH_SECTOR_8;
+  }
+  else if((Address < ADDR_FLASH_SECTOR_10) && (Address >= ADDR_FLASH_SECTOR_9))
+  {
+    sector = FLASH_SECTOR_9;
+  }
+  else if((Address < ADDR_FLASH_SECTOR_11) && (Address >= ADDR_FLASH_SECTOR_10))
+  {
+    sector = FLASH_SECTOR_10;
+  }else {
+    sector = FLASH_SECTOR_11;
+  }
+  return sector;
+}
+
+void flash_unlock(void)
+{
+    /* Authorize the FLASH Registers access */
+    WRITE_REG(FLASH->KEYR, FLASH_KEY1);
+    WRITE_REG(FLASH->KEYR, FLASH_KEY2);
+}
+
+/**
+  * @brief  Locks the FLASH control register access
+  * @retval HAL Status
+  */
+void flash_lock(void)
+{
+  /* Set the LOCK Bit to lock the FLASH Registers access */
+  FLASH->CR |= FLASH_CR_LOCK;
+}
+
+void flash_wait_ready(uint32_t Timeout)
+{
+  uint32_t tickstart = 0U;
+
+  tickstart = HAL_GetTick();
+
+  while(__HAL_FLASH_GET_FLAG(FLASH_FLAG_BSY) != RESET)
+  {
+//  	wdog_reload();
+    if(Timeout != HAL_MAX_DELAY)
+    {
+      if((Timeout == 0U)||((HAL_GetTick() - tickstart ) > Timeout))
+      {
+        return;
+      }
+    }
+  }
+  /* Check FLASH End of Operation flag  */
+  if (__HAL_FLASH_GET_FLAG(FLASH_FLAG_EOP) != RESET)
+  {
+    /* Clear FLASH End of Operation pending bit */
+    __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP);
+  }
+}
+
+void flash_erase_sector(uint32_t Sector)
+{
+  uint32_t tmp_psize = 0U;
+
+  uint8_t VoltageRange = FLASH_VOLTAGE_RANGE_3;
+
+  if (VoltageRange == FLASH_VOLTAGE_RANGE_1)
+  {
+    tmp_psize = FLASH_PSIZE_BYTE;
+  }
+  else if (VoltageRange == FLASH_VOLTAGE_RANGE_2)
+  {
+    tmp_psize = FLASH_PSIZE_HALF_WORD;
+  }
+  else if (VoltageRange == FLASH_VOLTAGE_RANGE_3)
+  {
+    tmp_psize = FLASH_PSIZE_WORD;
+  }
+  else
+  {
+    tmp_psize = FLASH_PSIZE_DOUBLE_WORD;
+  }
+
+  /* Need to add offset of 4 when sector higher than FLASH_SECTOR_11 */
+  if (Sector > FLASH_SECTOR_11)
+  {
+    Sector += 4U;
+  }
+  /* If the previous operation is completed, proceed to erase the sector */
+  CLEAR_BIT(FLASH->CR, FLASH_CR_PSIZE);
+  FLASH->CR |= tmp_psize;
+  CLEAR_BIT(FLASH->CR, FLASH_CR_SNB);
+  FLASH->CR |= FLASH_CR_SER | (Sector << FLASH_CR_SNB_Pos);
+  FLASH->CR |= FLASH_CR_STRT;
+
+  flash_wait_ready(2000);
+
+  CLEAR_BIT(FLASH->CR, (FLASH_CR_SER | FLASH_CR_SNB));
+}
+
+static void flash_write_word(uint32_t Address, uint32_t Data)
+{
+  /* If the previous operation is completed, proceed to program the new data */
+  CLEAR_BIT(FLASH->CR, FLASH_CR_PSIZE);
+  FLASH->CR |= FLASH_PSIZE_WORD;
+  FLASH->CR |= FLASH_CR_PG;
+
+  *(__IO uint32_t*)Address = Data;
+
+  flash_wait_ready(10);
+
+  FLASH->CR &= (~FLASH_CR_PG);
+}
+//不能用
+static void flash_write_byte(uint32_t Address, uint8_t Data)
+{
+  /* If the previous operation is completed, proceed to program the new data */
+  CLEAR_BIT(FLASH->CR, FLASH_CR_PSIZE);
+  FLASH->CR |= FLASH_PSIZE_BYTE;
+  FLASH->CR |= FLASH_CR_PG;
+
+  *(__IO uint8_t*)Address = Data;
+
+  flash_wait_ready(10);
+
+  FLASH->CR &= (~FLASH_CR_PG);
+}
+
+// @brief Erases a flash sector. This sets all bits in the sector to 1.
+// The sector's current index is reset to the minimum value (n_reserved).
+// @returns 0 on success or a non-zero error code otherwise
+int flash_erase_page(uint32_t address) {
+//	wdog_reload();
+    flash_unlock();
+    HAL_FLASH_ClearError();
+    flash_erase_sector(_sector_frame_address(address));
+    flash_lock();
+//	wdog_reload();
+    return 0;
+}
+
+int flash_erase_pages(uint32_t address, uint32_t size) {
+	for (; size > 0; ) {
+		flash_erase_page(address);
+		uint8_t sector = _sector_frame_address(address);
+		address += sectors_size[sector];
+		size -= sectors_size[sector];;
+	}
+	return 0;
+}
+
+int flash_erase_app(uint8_t app_num) {
+	if(app_num == 1) {
+		app_status_set(1,false);
+
+		//total = 16+64+128+128=336k
+		flash_erase_page(ADDR_FLASH_SECTOR_3);//16k
+		flash_erase_page(ADDR_FLASH_SECTOR_4);//64k
+		flash_erase_page(ADDR_FLASH_SECTOR_5);//128k
+		flash_erase_page(ADDR_FLASH_SECTOR_6);//128k
+	}
+	else if(app_num == 2) {
+		app_status_set(2,false);
+
+		//total = 128+128+128=384k
+		flash_erase_page(ADDR_FLASH_SECTOR_7);//128k
+		flash_erase_page(ADDR_FLASH_SECTOR_8);//128k
+		flash_erase_page(ADDR_FLASH_SECTOR_9);//128k
+	}
+	return 0;
+}
+
+void app_status_set(uint8_t app_num,bool status) {
+  uint8_t app_ok_flag[2];
+  if(app_num == 1) {
+    app_ok_flag[0] = status;
+    app_ok_flag[1] = *(volatile uint8_t*)(CONFIG_IAP_INFO_ADDR+1);
+    flash_erase_page(CONFIG_IAP_INFO_ADDR);
+    flash_write_page(CONFIG_IAP_INFO_ADDR, app_ok_flag, 2, false);
+  }
+  else if(app_num == 2) {
+    app_ok_flag[0] = *(volatile uint8_t*)(CONFIG_IAP_INFO_ADDR);
+    app_ok_flag[1] = status;
+    flash_erase_page(CONFIG_IAP_INFO_ADDR);
+    flash_write_page(CONFIG_IAP_INFO_ADDR, app_ok_flag, 2, false);
+  }
+}
+
+int flash_write_page(uint32_t target_addr, uint8_t *data, uint32_t length, bool erase) {
+	uint32_t offset = target_addr & 0x3;
+    target_addr -= offset;
+    if (erase && flash_erase_page(target_addr) != 0) {
+        return -1;
+    }
+//	wdog_reload();
+    flash_unlock();
+    HAL_FLASH_ClearError();
+    // handle unaligned start
+    for (; (offset & 0x3) && length; ++data, ++offset, --length) {
+        flash_write_byte(target_addr + offset, *data);
+    }
+    // write 32-bit values (64-bit doesn't work)
+    for (; length >= 4; data += 4, offset += 4, length -=4) {
+        flash_write_word(target_addr + offset, *(uint32_t *)data);
+    }
+
+    // handle unaligned end
+    for (; length; ++data, ++offset, --length) {
+        flash_write_byte(target_addr + offset, *data);
+    }
+
+    flash_lock();
+    return 0;
+}
+
+int flash_test(void) {
+	int reg = 0;
+	uint8_t buffer[1024];
+
+	reg = flash_erase_pages(ADDR_FLASH_SECTOR_2, ADDR_FLASH_SECTOR_10-ADDR_FLASH_SECTOR_2);
+
+	memset(buffer, 0x55, sizeof(buffer));
+	reg = flash_erase_page(ADDR_FLASH_SECTOR_10);
+	reg = flash_write_page(ADDR_FLASH_SECTOR_10, buffer, sizeof(buffer), false);
+	memset(buffer, 0xAA, sizeof(buffer));
+	reg = flash_write_page(ADDR_FLASH_SECTOR_10, buffer, sizeof(buffer), true);
+
+	memset(buffer, 0x55, sizeof(buffer));
+	reg = flash_erase_page(ADDR_FLASH_SECTOR_11);
+	reg = flash_write_page(ADDR_FLASH_SECTOR_11, buffer, sizeof(buffer), false);
+	memset(buffer, 0xAA, sizeof(buffer));
+	reg = flash_write_page(ADDR_FLASH_SECTOR_11, buffer, sizeof(buffer), true);
+
+	return reg;
+}
+#if 1
+//APP1_ADRESS 内容复制到 APP2_ADRESS
+void app1_copy_to_app2(void) {
+  uint8_t data[1];
+  //1、擦除APP2的flash和完整性标志位
+  flash_erase_app(2);
+  //2、从APP1_ADDRESS读出APP2_ADDRESS - APP1_ADDRESS个数据，复制写入到APP2_ADDRESS
+  for (uint32_t i = 0; i < APP2_ADDRESS - APP1_ADDRESS; i++) {
+    data[0] = *(volatile uint8_t*)(APP1_ADDRESS + i);
+    flash_write_page(APP2_ADDRESS + i, data, 1, false);
+  }
+}
+void app2_copy_to_app1(void) {
+  uint8_t data[1];
+  //1、擦除APP1的flash和完整性标志位
+  flash_erase_app(1);
+  //2、从APP2_ADDRESS读出APP2_ADDRESS - APP1_ADDRESS个数据，复制写入到APP1_ADDRESS
+  for (uint32_t i = 0; i < APP2_ADDRESS - APP1_ADDRESS; i++) {
+    data[0] = *(volatile uint8_t*)(APP2_ADDRESS + i);
+    flash_write_page(APP1_ADDRESS + i, data, 1, false);
+  }
+}
+
+#else
+//使用字(32位)为单位批量复制，提效不大
+void app1_copy_to_app2(void) {
+    uint32_t app_size = APP2_ADDRESS - APP1_ADDRESS;
+
+    // 1. 擦除APP2区域
+    flash_erase_app(2);
+
+    // 2. 一次性读取较多数据，批量写入
+    uint32_t buffer[256];  // 1KB缓冲区
+    uint32_t offset = 0;
+
+    while (offset < app_size) {
+        // 计算本次复制的数据量（不超过缓冲区大小）
+        uint32_t copy_size = app_size - offset;
+        if (copy_size > sizeof(buffer)) {
+            copy_size = sizeof(buffer);
+        }
+
+        // 按字(32位)读取
+        uint32_t word_count = (copy_size + 3) / 4;  // 向上取整到4字节
+
+        for (uint32_t i = 0; i < word_count; i++) {
+            buffer[i] = *(volatile uint32_t*)(APP1_ADDRESS + offset + i * 4);
+        }
+
+        // 批量写入
+        flash_write_page(APP2_ADDRESS + offset, (uint8_t*)buffer, copy_size, false);
+
+        offset += copy_size;
+    }
+}
+#endif
+
+void jump_to_app(uint32_t app_addr)
+{
+	__disable_irq();
+    // 3. 清除所有中断挂起位（非常重要！）
+    for (int i = 0; i < 8; i++) {
+        NVIC->ICPR[i] = 0xFFFFFFFF;  // 清除挂起
+        NVIC->ICER[i] = 0xFFFFFFFF;  // 禁用中断
+    }
+
+	SysTick->CTRL = 0;
+
+	HAL_CAN_DeInit(&hcan1);
+	HAL_DeInit();
+
+	__set_MSP(REG32(app_addr));
+//	SCB->VTOR = app_addr;
+
+	((void (*)(void))(REG32(app_addr + 4)))();
+}
+
+#if 0
+void flash_write_magic(uint32_t magic) {
+	uint32_t buffer[16];
+	if (magic == REG32(CONFIG_IAP_INFO_ADDR + 8)) {
+		return;
+	}
+	memcpy(buffer, (void *)CONFIG_IAP_INFO_ADDR, sizeof(buffer));
+
+	buffer[2] = magic;
+
+	flash_write_page(CONFIG_IAP_INFO_ADDR, (u8 *)buffer, sizeof(buffer), true);
+}
+
+uint32_t flash_read_magic(void) {
+	return REG32(CONFIG_IAP_INFO_ADDR + 8);
+}
+#endif
+
+
+
+

Core/Src/gpio.c

@@ -0,0 +1,86 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    gpio.c
+  * @brief   This file provides code for the configuration
+  *          of all used GPIO pins.
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2025 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Includes ------------------------------------------------------------------*/
+#include "gpio.h"
+
+/* USER CODE BEGIN 0 */
+
+/* USER CODE END 0 */
+
+/*----------------------------------------------------------------------------*/
+/* Configure GPIO                                                             */
+/*----------------------------------------------------------------------------*/
+/* USER CODE BEGIN 1 */
+
+/* USER CODE END 1 */
+
+/** Configure pins as
+        * Analog
+        * Input
+        * Output
+        * EVENT_OUT
+        * EXTI
+*/
+void MX_GPIO_Init(void)
+{
+
+  GPIO_InitTypeDef GPIO_InitStruct = {0};
+
+  /* GPIO Ports Clock Enable */
+  __HAL_RCC_GPIOH_CLK_ENABLE();
+  __HAL_RCC_GPIOA_CLK_ENABLE();
+  __HAL_RCC_GPIOB_CLK_ENABLE();
+  __HAL_RCC_GPIOC_CLK_ENABLE();
+
+  /*Configure GPIO pin Output Level */
+
+  /*Configure GPIO pin : PC4  抱闸输出 */
+  GPIO_InitStruct.Pin = GPIO_PIN_4;
+  GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
+  GPIO_InitStruct.Pull = GPIO_NOPULL;
+  GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
+  HAL_GPIO_Init(GPIOC, &GPIO_InitStruct);
+
+  /*Configure GPIO pin : PB3  抱闸输出*/
+  GPIO_InitStruct.Pin = GPIO_PIN_3;
+  GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
+  GPIO_InitStruct.Pull = GPIO_NOPULL;
+  GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
+  HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
+
+  /*Configure GPIO pin : PA2  抱闸状态读取 */
+  GPIO_InitStruct.Pin = GPIO_PIN_2;
+  GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
+  GPIO_InitStruct.Pull = GPIO_NOPULL;
+  GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
+  HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
+
+  /*Configure GPIO pin : PA3  抱闸状态读取*/
+  GPIO_InitStruct.Pin = GPIO_PIN_3;
+  GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
+  GPIO_InitStruct.Pull = GPIO_NOPULL;
+  GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
+  HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
+}
+
+/* USER CODE BEGIN 2 */
+
+/* USER CODE END 2 */

Core/Src/main.c

@@ -0,0 +1,313 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file           : main.c
+  * @brief          : Main program body
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2025 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+/* Includes ------------------------------------------------------------------*/
+#include "main.h"
+#include "can.h"
+#include "tim.h"
+#include "gpio.h"
+
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+#include "flash.h"
+#include "UDS.h"
+
+/* USER CODE END Includes */
+
+/* Private typedef -----------------------------------------------------------*/
+/* USER CODE BEGIN PTD */
+
+/* USER CODE END PTD */
+
+/* Private define ------------------------------------------------------------*/
+/* USER CODE BEGIN PD */
+
+/* USER CODE END PD */
+
+/* Private macro -------------------------------------------------------------*/
+/* USER CODE BEGIN PM */
+
+/* USER CODE END PM */
+
+/* Private variables ---------------------------------------------------------*/
+
+/* USER CODE BEGIN PV */
+extern uint8_t TxBuf[8];
+extern uint8_t ota_start_flag;
+extern uint32_t system_time_ms;           // 系统运行时间，用于判断上电等待接收升级指令
+extern uint8_t app_error_flag;
+/* USER CODE END PV */
+
+/* Private function prototypes -----------------------------------------------*/
+void SystemClock_Config(void);
+/* USER CODE BEGIN PFP */
+
+/* USER CODE END PFP */
+
+/* Private user code ---------------------------------------------------------*/
+/* USER CODE BEGIN 0 */
+
+// 定义版本信息并强制放在指定的Flash地址
+// 使用section属性将变量放入特定段
+typedef struct {
+    uint16_t hardware_version;  // 硬件版本
+    uint16_t software_version;  // boot软件版本
+} VersionInfo;
+__attribute__((section(".version_info"), used))
+const VersionInfo version_info = {
+    .hardware_version = 0x0100,  // 示例：V1.0
+    .software_version = 0x0100,  // 示例：V1.01
+};
+
+// 获取版本信息的函数
+uint32_t get_app_version(uint8_t soft)
+{
+	uint32_t app1_version = *(volatile uint32_t*)0x0800C188;
+	uint32_t app2_version = *(volatile uint32_t*)0x08060188;
+
+	if(app1_version == 0xFFFFFFFF)
+	{
+		app1_version = 0;
+	}
+	if(app2_version == 0xFFFFFFFF)
+	{
+		app2_version = 0;
+	}
+
+	if(soft == 1)//app1
+	{
+        return app1_version;
+	}
+	else if(soft == 2)//app2
+	{
+        return app2_version;
+	}
+	else
+	{
+		return 0;
+	}
+}
+
+/* USER CODE END 0 */
+
+/**
+  * @brief  The application entry point.
+  * @retval int
+  */
+int main(void)
+{
+
+  /* USER CODE BEGIN 1 */
+
+  /* USER CODE END 1 */
+
+  /* MCU Configuration--------------------------------------------------------*/
+
+  /* Reset of all peripherals, Initializes the Flash interface and the Systick. */
+  HAL_Init();
+
+  /* USER CODE BEGIN Init */
+
+  /* USER CODE END Init */
+
+  /* Configure the system clock */
+  SystemClock_Config();
+
+  /* USER CODE BEGIN SysInit */
+
+  /* USER CODE END SysInit */
+
+  /* Initialize all configured peripherals */
+  MX_GPIO_Init();
+  MX_CAN1_Init();
+  MX_TIM2_Init();
+  /* USER CODE BEGIN 2 */
+  HAL_TIM_Base_Start_IT(&htim2); // 启动定时器中断
+  CAN_Filter_config();
+  i15765_init();
+  i15765app_init();
+
+#if  0	//测试抱闸功能
+  uint8_t brake_r_state = 0;
+  uint8_t brake_l_state = 0;
+
+  brake_r_state = BRAKE_R;
+  brake_l_state = BRAKE_L;
+
+  BRAKE_R_SET_0;
+  BRAKE_L_SET_0;
+  brake_r_state = BRAKE_R;
+  brake_l_state = BRAKE_L;
+
+  BRAKE_R_SET_1;
+  BRAKE_L_SET_1;
+  brake_r_state = BRAKE_R;
+  brake_l_state = BRAKE_L;
+
+#endif
+//  TxBuf[0] = 0x1;
+//  TxBuf[1] = 0x22;
+//  TxBuf[2] = 0x33;
+//  TxBuf[3] = 0x44;
+//  TxBuf[4] = 0x55;
+//  TxBuf[5] = 0x66;
+//  TxBuf[6] = 0x77;
+//  TxBuf[7] = 0x88;
+//  CAN_SendData(1, 2, 0x709, TxBuf,8);
+#if 0
+  //只第一次刷程序时执行1次，再屏蔽掉刷一次
+  if(1 != *(volatile uint8_t*)(CONFIG_IAP_INFO_ADDR))
+  {
+	  app_status_set(1,true);
+  }
+//  if(1 != *(volatile uint8_t*)(CONFIG_IAP_INFO_ADDR+1))//app2无固件
+//  {
+//	  app1_copy_to_app2();
+//	  app_status_set(2,true);
+//  }
+#endif
+
+  uint32_t app1_version = get_app_version(1);
+  uint32_t app2_version = get_app_version(2);
+
+  if(1 == *(volatile uint8_t*)(CONFIG_IAP_INFO_ADDR+1))//APP_B is ok
+  {
+	  if(app1_version < app2_version)
+	  {
+		app2_copy_to_app1();
+		//flash_erase_app(1);
+		app_status_set(1,true);
+	  }
+  }
+//  app1_copy_to_app2();
+//  app_status_set(1,true);
+//  app_status_set(2,true);
+
+  //VECT_TAB_OFFSET
+  /* USER CODE END 2 */
+
+  /* Infinite loop */
+  /* USER CODE BEGIN WHILE */
+  while (1)
+  {
+    /* USER CODE END WHILE */
+
+    /* USER CODE BEGIN 3 */
+	  check_SID_run();
+
+	  //if((system_time_ms == WAIT_OTA_TIME_MS)&&(1))//复位后判断是否从APP跳转过来，不是的话直接跳到APP
+	  if(system_time_ms == WAIT_OTA_TIME_MS)
+	  {
+		  //APP_A is ok
+		  if(1 == *(volatile uint8_t*)CONFIG_IAP_INFO_ADDR)
+		  //if(0)
+		  {
+			  system_time_ms = WAIT_OTA_TIME_MS;
+			  jump_to_app(APP1_ADDRESS);
+		  }
+		  else
+		  {
+			  app_error_flag = 1;
+		  }
+	  }
+	  //CAN_SendData(1, 2, 0x709, TxBuf,8);
+	  //HAL_Delay(1000);
+  }
+
+  /* USER CODE END 3 */
+}
+
+/**
+  * @brief System Clock Configuration
+  * @retval None
+  */
+void SystemClock_Config(void)
+{
+  RCC_OscInitTypeDef RCC_OscInitStruct = {0};
+  RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
+
+  /** Configure the main internal regulator output voltage
+  */
+  __HAL_RCC_PWR_CLK_ENABLE();
+  __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
+
+  /** Initializes the RCC Oscillators according to the specified parameters
+  * in the RCC_OscInitTypeDef structure.
+  */
+  RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
+  RCC_OscInitStruct.HSEState = RCC_HSE_ON;
+  RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
+  RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
+  RCC_OscInitStruct.PLL.PLLM = 4;
+  RCC_OscInitStruct.PLL.PLLN = 168;
+  RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2;
+  RCC_OscInitStruct.PLL.PLLQ = 4;
+  if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
+  {
+    Error_Handler();
+  }
+
+  /** Initializes the CPU, AHB and APB buses clocks
+  */
+  RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
+                              |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2;
+  RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
+  RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
+  RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV4;
+  RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV2;
+
+  if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_5) != HAL_OK)
+  {
+    Error_Handler();
+  }
+}
+
+/* USER CODE BEGIN 4 */
+
+/* USER CODE END 4 */
+
+/**
+  * @brief  This function is executed in case of error occurrence.
+  * @retval None
+  */
+void Error_Handler(void)
+{
+  /* USER CODE BEGIN Error_Handler_Debug */
+  /* User can add his own implementation to report the HAL error return state */
+  __disable_irq();
+  while (1)
+  {
+  }
+  /* USER CODE END Error_Handler_Debug */
+}
+#ifdef USE_FULL_ASSERT
+/**
+  * @brief  Reports the name of the source file and the source line number
+  *         where the assert_param error has occurred.
+  * @param  file: pointer to the source file name
+  * @param  line: assert_param error line source number
+  * @retval None
+  */
+void assert_failed(uint8_t *file, uint32_t line)
+{
+  /* USER CODE BEGIN 6 */
+  /* User can add his own implementation to report the file name and line number,
+     ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */
+  /* USER CODE END 6 */
+}
+#endif /* USE_FULL_ASSERT */

Core/Src/stm32f4xx_hal_msp.c

@@ -0,0 +1,82 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file         stm32f4xx_hal_msp.c
+  * @brief        This file provides code for the MSP Initialization
+  *               and de-Initialization codes.
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2025 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Includes ------------------------------------------------------------------*/
+#include "main.h"
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+/* Private typedef -----------------------------------------------------------*/
+/* USER CODE BEGIN TD */
+
+/* USER CODE END TD */
+
+/* Private define ------------------------------------------------------------*/
+/* USER CODE BEGIN Define */
+
+/* USER CODE END Define */
+
+/* Private macro -------------------------------------------------------------*/
+/* USER CODE BEGIN Macro */
+
+/* USER CODE END Macro */
+
+/* Private variables ---------------------------------------------------------*/
+/* USER CODE BEGIN PV */
+
+/* USER CODE END PV */
+
+/* Private function prototypes -----------------------------------------------*/
+/* USER CODE BEGIN PFP */
+
+/* USER CODE END PFP */
+
+/* External functions --------------------------------------------------------*/
+/* USER CODE BEGIN ExternalFunctions */
+
+/* USER CODE END ExternalFunctions */
+
+/* USER CODE BEGIN 0 */
+
+/* USER CODE END 0 */
+/**
+  * Initializes the Global MSP.
+  */
+void HAL_MspInit(void)
+{
+
+  /* USER CODE BEGIN MspInit 0 */
+
+  /* USER CODE END MspInit 0 */
+
+  __HAL_RCC_SYSCFG_CLK_ENABLE();
+  __HAL_RCC_PWR_CLK_ENABLE();
+
+  /* System interrupt init*/
+
+  /* USER CODE BEGIN MspInit 1 */
+
+  /* USER CODE END MspInit 1 */
+}
+
+/* USER CODE BEGIN 1 */
+
+/* USER CODE END 1 */

Core/Src/stm32f4xx_it.c

@@ -0,0 +1,232 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    stm32f4xx_it.c
+  * @brief   Interrupt Service Routines.
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2025 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Includes ------------------------------------------------------------------*/
+#include "main.h"
+#include "stm32f4xx_it.h"
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+/* USER CODE END Includes */
+
+/* Private typedef -----------------------------------------------------------*/
+/* USER CODE BEGIN TD */
+
+/* USER CODE END TD */
+
+/* Private define ------------------------------------------------------------*/
+/* USER CODE BEGIN PD */
+
+/* USER CODE END PD */
+
+/* Private macro -------------------------------------------------------------*/
+/* USER CODE BEGIN PM */
+
+/* USER CODE END PM */
+
+/* Private variables ---------------------------------------------------------*/
+/* USER CODE BEGIN PV */
+
+/* USER CODE END PV */
+
+/* Private function prototypes -----------------------------------------------*/
+/* USER CODE BEGIN PFP */
+
+/* USER CODE END PFP */
+
+/* Private user code ---------------------------------------------------------*/
+/* USER CODE BEGIN 0 */
+
+/* USER CODE END 0 */
+
+/* External variables --------------------------------------------------------*/
+extern CAN_HandleTypeDef hcan1;
+extern TIM_HandleTypeDef htim2;
+/* USER CODE BEGIN EV */
+
+/* USER CODE END EV */
+
+/******************************************************************************/
+/*           Cortex-M4 Processor Interruption and Exception Handlers          */
+/******************************************************************************/
+/**
+  * @brief This function handles Non maskable interrupt.
+  */
+void NMI_Handler(void)
+{
+  /* USER CODE BEGIN NonMaskableInt_IRQn 0 */
+
+  /* USER CODE END NonMaskableInt_IRQn 0 */
+  /* USER CODE BEGIN NonMaskableInt_IRQn 1 */
+   while (1)
+  {
+  }
+  /* USER CODE END NonMaskableInt_IRQn 1 */
+}
+
+/**
+  * @brief This function handles Hard fault interrupt.
+  */
+void HardFault_Handler(void)
+{
+  /* USER CODE BEGIN HardFault_IRQn 0 */
+
+  /* USER CODE END HardFault_IRQn 0 */
+  while (1)
+  {
+    /* USER CODE BEGIN W1_HardFault_IRQn 0 */
+    /* USER CODE END W1_HardFault_IRQn 0 */
+  }
+}
+
+/**
+  * @brief This function handles Memory management fault.
+  */
+void MemManage_Handler(void)
+{
+  /* USER CODE BEGIN MemoryManagement_IRQn 0 */
+
+  /* USER CODE END MemoryManagement_IRQn 0 */
+  while (1)
+  {
+    /* USER CODE BEGIN W1_MemoryManagement_IRQn 0 */
+    /* USER CODE END W1_MemoryManagement_IRQn 0 */
+  }
+}
+
+/**
+  * @brief This function handles Pre-fetch fault, memory access fault.
+  */
+void BusFault_Handler(void)
+{
+  /* USER CODE BEGIN BusFault_IRQn 0 */
+
+  /* USER CODE END BusFault_IRQn 0 */
+  while (1)
+  {
+    /* USER CODE BEGIN W1_BusFault_IRQn 0 */
+    /* USER CODE END W1_BusFault_IRQn 0 */
+  }
+}
+
+/**
+  * @brief This function handles Undefined instruction or illegal state.
+  */
+void UsageFault_Handler(void)
+{
+  /* USER CODE BEGIN UsageFault_IRQn 0 */
+
+  /* USER CODE END UsageFault_IRQn 0 */
+  while (1)
+  {
+    /* USER CODE BEGIN W1_UsageFault_IRQn 0 */
+    /* USER CODE END W1_UsageFault_IRQn 0 */
+  }
+}
+
+/**
+  * @brief This function handles System service call via SWI instruction.
+  */
+void SVC_Handler(void)
+{
+  /* USER CODE BEGIN SVCall_IRQn 0 */
+
+  /* USER CODE END SVCall_IRQn 0 */
+  /* USER CODE BEGIN SVCall_IRQn 1 */
+
+  /* USER CODE END SVCall_IRQn 1 */
+}
+
+/**
+  * @brief This function handles Debug monitor.
+  */
+void DebugMon_Handler(void)
+{
+  /* USER CODE BEGIN DebugMonitor_IRQn 0 */
+
+  /* USER CODE END DebugMonitor_IRQn 0 */
+  /* USER CODE BEGIN DebugMonitor_IRQn 1 */
+
+  /* USER CODE END DebugMonitor_IRQn 1 */
+}
+
+/**
+  * @brief This function handles Pendable request for system service.
+  */
+void PendSV_Handler(void)
+{
+  /* USER CODE BEGIN PendSV_IRQn 0 */
+
+  /* USER CODE END PendSV_IRQn 0 */
+  /* USER CODE BEGIN PendSV_IRQn 1 */
+
+  /* USER CODE END PendSV_IRQn 1 */
+}
+
+/**
+  * @brief This function handles System tick timer.
+  */
+void SysTick_Handler(void)
+{
+  /* USER CODE BEGIN SysTick_IRQn 0 */
+
+  /* USER CODE END SysTick_IRQn 0 */
+  HAL_IncTick();
+  /* USER CODE BEGIN SysTick_IRQn 1 */
+
+  /* USER CODE END SysTick_IRQn 1 */
+}
+
+/******************************************************************************/
+/* STM32F4xx Peripheral Interrupt Handlers                                    */
+/* Add here the Interrupt Handlers for the used peripherals.                  */
+/* For the available peripheral interrupt handler names,                      */
+/* please refer to the startup file (startup_stm32f4xx.s).                    */
+/******************************************************************************/
+
+/**
+  * @brief This function handles CAN1 RX0 interrupts.
+  */
+void CAN1_RX0_IRQHandler(void)
+{
+  /* USER CODE BEGIN CAN1_RX0_IRQn 0 */
+
+  /* USER CODE END CAN1_RX0_IRQn 0 */
+  HAL_CAN_IRQHandler(&hcan1);
+  /* USER CODE BEGIN CAN1_RX0_IRQn 1 */
+
+  /* USER CODE END CAN1_RX0_IRQn 1 */
+}
+
+/**
+  * @brief This function handles TIM2 global interrupt.
+  */
+void TIM2_IRQHandler(void)
+{
+  /* USER CODE BEGIN TIM2_IRQn 0 */
+
+  /* USER CODE END TIM2_IRQn 0 */
+  HAL_TIM_IRQHandler(&htim2);
+  /* USER CODE BEGIN TIM2_IRQn 1 */
+
+  /* USER CODE END TIM2_IRQn 1 */
+}
+
+/* USER CODE BEGIN 1 */
+
+/* USER CODE END 1 */

Core/Src/syscalls.c

@@ -0,0 +1,176 @@
+/**
+ ******************************************************************************
+ * @file      syscalls.c
+ * @author    Auto-generated by STM32CubeIDE
+ * @brief     STM32CubeIDE Minimal System calls file
+ *
+ *            For more information about which c-functions
+ *            need which of these lowlevel functions
+ *            please consult the Newlib libc-manual
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2020-2025 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ */
+
+/* Includes */
+#include <sys/stat.h>
+#include <stdlib.h>
+#include <errno.h>
+#include <stdio.h>
+#include <signal.h>
+#include <time.h>
+#include <sys/time.h>
+#include <sys/times.h>
+
+
+/* Variables */
+extern int __io_putchar(int ch) __attribute__((weak));
+extern int __io_getchar(void) __attribute__((weak));
+
+
+char *__env[1] = { 0 };
+char **environ = __env;
+
+
+/* Functions */
+void initialise_monitor_handles()
+{
+}
+
+int _getpid(void)
+{
+  return 1;
+}
+
+int _kill(int pid, int sig)
+{
+  (void)pid;
+  (void)sig;
+  errno = EINVAL;
+  return -1;
+}
+
+void _exit (int status)
+{
+  _kill(status, -1);
+  while (1) {}    /* Make sure we hang here */
+}
+
+__attribute__((weak)) int _read(int file, char *ptr, int len)
+{
+  (void)file;
+  int DataIdx;
+
+  for (DataIdx = 0; DataIdx < len; DataIdx++)
+  {
+    *ptr++ = __io_getchar();
+  }
+
+  return len;
+}
+
+__attribute__((weak)) int _write(int file, char *ptr, int len)
+{
+  (void)file;
+  int DataIdx;
+
+  for (DataIdx = 0; DataIdx < len; DataIdx++)
+  {
+    __io_putchar(*ptr++);
+  }
+  return len;
+}
+
+int _close(int file)
+{
+  (void)file;
+  return -1;
+}
+
+
+int _fstat(int file, struct stat *st)
+{
+  (void)file;
+  st->st_mode = S_IFCHR;
+  return 0;
+}
+
+int _isatty(int file)
+{
+  (void)file;
+  return 1;
+}
+
+int _lseek(int file, int ptr, int dir)
+{
+  (void)file;
+  (void)ptr;
+  (void)dir;
+  return 0;
+}
+
+int _open(char *path, int flags, ...)
+{
+  (void)path;
+  (void)flags;
+  /* Pretend like we always fail */
+  return -1;
+}
+
+int _wait(int *status)
+{
+  (void)status;
+  errno = ECHILD;
+  return -1;
+}
+
+int _unlink(char *name)
+{
+  (void)name;
+  errno = ENOENT;
+  return -1;
+}
+
+int _times(struct tms *buf)
+{
+  (void)buf;
+  return -1;
+}
+
+int _stat(char *file, struct stat *st)
+{
+  (void)file;
+  st->st_mode = S_IFCHR;
+  return 0;
+}
+
+int _link(char *old, char *new)
+{
+  (void)old;
+  (void)new;
+  errno = EMLINK;
+  return -1;
+}
+
+int _fork(void)
+{
+  errno = EAGAIN;
+  return -1;
+}
+
+int _execve(char *name, char **argv, char **env)
+{
+  (void)name;
+  (void)argv;
+  (void)env;
+  errno = ENOMEM;
+  return -1;
+}

Core/Src/sysmem.c

@@ -0,0 +1,79 @@
+/**
+ ******************************************************************************
+ * @file      sysmem.c
+ * @author    Generated by STM32CubeIDE
+ * @brief     STM32CubeIDE System Memory calls file
+ *
+ *            For more information about which C functions
+ *            need which of these lowlevel functions
+ *            please consult the newlib libc manual
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2025 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ */
+
+/* Includes */
+#include <errno.h>
+#include <stdint.h>
+
+/**
+ * Pointer to the current high watermark of the heap usage
+ */
+static uint8_t *__sbrk_heap_end = NULL;
+
+/**
+ * @brief _sbrk() allocates memory to the newlib heap and is used by malloc
+ *        and others from the C library
+ *
+ * @verbatim
+ * ############################################################################
+ * #  .data  #  .bss  #       newlib heap       #          MSP stack          #
+ * #         #        #                         # Reserved by _Min_Stack_Size #
+ * ############################################################################
+ * ^-- RAM start      ^-- _end                             _estack, RAM end --^
+ * @endverbatim
+ *
+ * This implementation starts allocating at the '_end' linker symbol
+ * The '_Min_Stack_Size' linker symbol reserves a memory for the MSP stack
+ * The implementation considers '_estack' linker symbol to be RAM end
+ * NOTE: If the MSP stack, at any point during execution, grows larger than the
+ * reserved size, please increase the '_Min_Stack_Size'.
+ *
+ * @param incr Memory size
+ * @return Pointer to allocated memory
+ */
+void *_sbrk(ptrdiff_t incr)
+{
+  extern uint8_t _end; /* Symbol defined in the linker script */
+  extern uint8_t _estack; /* Symbol defined in the linker script */
+  extern uint32_t _Min_Stack_Size; /* Symbol defined in the linker script */
+  const uint32_t stack_limit = (uint32_t)&_estack - (uint32_t)&_Min_Stack_Size;
+  const uint8_t *max_heap = (uint8_t *)stack_limit;
+  uint8_t *prev_heap_end;
+
+  /* Initialize heap end at first call */
+  if (NULL == __sbrk_heap_end)
+  {
+    __sbrk_heap_end = &_end;
+  }
+
+  /* Protect heap from growing into the reserved MSP stack */
+  if (__sbrk_heap_end + incr > max_heap)
+  {
+    errno = ENOMEM;
+    return (void *)-1;
+  }
+
+  prev_heap_end = __sbrk_heap_end;
+  __sbrk_heap_end += incr;
+
+  return (void *)prev_heap_end;
+}

Core/Src/system_stm32f4xx.c

@@ -0,0 +1,747 @@
+/**
+  ******************************************************************************
+  * @file    system_stm32f4xx.c
+  * @author  MCD Application Team
+  * @brief   CMSIS Cortex-M4 Device Peripheral Access Layer System Source File.
+  *
+  *   This file provides two functions and one global variable to be called from 
+  *   user application:
+  *      - SystemInit(): This function is called at startup just after reset and 
+  *                      before branch to main program. This call is made inside
+  *                      the "startup_stm32f4xx.s" file.
+  *
+  *      - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
+  *                                  by the user application to setup the SysTick 
+  *                                  timer or configure other parameters.
+  *                                     
+  *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
+  *                                 be called whenever the core clock is changed
+  *                                 during program execution.
+  *
+  *
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+
+/** @addtogroup CMSIS
+  * @{
+  */
+
+/** @addtogroup stm32f4xx_system
+  * @{
+  */  
+  
+/** @addtogroup STM32F4xx_System_Private_Includes
+  * @{
+  */
+
+
+#include "stm32f4xx.h"
+
+#if !defined  (HSE_VALUE) 
+  #define HSE_VALUE    ((uint32_t)25000000) /*!< Default value of the External oscillator in Hz */
+#endif /* HSE_VALUE */
+
+#if !defined  (HSI_VALUE)
+  #define HSI_VALUE    ((uint32_t)16000000) /*!< Value of the Internal oscillator in Hz*/
+#endif /* HSI_VALUE */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32F4xx_System_Private_TypesDefinitions
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32F4xx_System_Private_Defines
+  * @{
+  */
+
+/************************* Miscellaneous Configuration ************************/
+/*!< Uncomment the following line if you need to use external SRAM or SDRAM as data memory  */
+#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx)\
+ || defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)\
+ || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx)
+/* #define DATA_IN_ExtSRAM */
+#endif /* STM32F40xxx || STM32F41xxx || STM32F42xxx || STM32F43xxx || STM32F469xx || STM32F479xx ||\
+          STM32F412Zx || STM32F412Vx */
+ 
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)\
+ || defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx)
+/* #define DATA_IN_ExtSDRAM */
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx ||\
+          STM32F479xx */
+
+/* Note: Following vector table addresses must be defined in line with linker
+         configuration. */
+/*!< Uncomment the following line if you need to relocate the vector table
+     anywhere in Flash or Sram, else the vector table is kept at the automatic
+     remap of boot address selected */
+//#define USER_VECT_TAB_ADDRESS
+
+#if defined(USER_VECT_TAB_ADDRESS)
+/*!< Uncomment the following line if you need to relocate your vector Table
+     in Sram else user remap will be done in Flash. */
+/* #define VECT_TAB_SRAM */
+#if defined(VECT_TAB_SRAM)
+#define VECT_TAB_BASE_ADDRESS   SRAM_BASE       /*!< Vector Table base address field.
+                                                     This value must be a multiple of 0x200. */
+#else
+#define VECT_TAB_BASE_ADDRESS   0x08008000UL/*FLASH_BASE*/      /*!< Vector Table base address field.
+                                                     This value must be a multiple of 0x200. */
+#endif /* VECT_TAB_SRAM */
+#if !defined(VECT_TAB_OFFSET)
+#define VECT_TAB_OFFSET         0x00000000U//0x00008000U     /*!< Vector Table offset field.This value must be a multiple of 0x200. */
+
+#endif /* VECT_TAB_OFFSET */
+#endif /* USER_VECT_TAB_ADDRESS */
+/******************************************************************************/
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32F4xx_System_Private_Macros
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32F4xx_System_Private_Variables
+  * @{
+  */
+  /* This variable is updated in three ways:
+      1) by calling CMSIS function SystemCoreClockUpdate()
+      2) by calling HAL API function HAL_RCC_GetHCLKFreq()
+      3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency 
+         Note: If you use this function to configure the system clock; then there
+               is no need to call the 2 first functions listed above, since SystemCoreClock
+               variable is updated automatically.
+  */
+uint32_t SystemCoreClock = 16000000;
+const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
+const uint8_t APBPrescTable[8]  = {0, 0, 0, 0, 1, 2, 3, 4};
+/**
+  * @}
+  */
+
+/** @addtogroup STM32F4xx_System_Private_FunctionPrototypes
+  * @{
+  */
+
+#if defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM)
+  static void SystemInit_ExtMemCtl(void); 
+#endif /* DATA_IN_ExtSRAM || DATA_IN_ExtSDRAM */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32F4xx_System_Private_Functions
+  * @{
+  */
+
+/**
+  * @brief  Setup the microcontroller system
+  *         Initialize the FPU setting, vector table location and External memory 
+  *         configuration.
+  * @param  None
+  * @retval None
+  */
+void SystemInit(void)
+{
+  /* FPU settings ------------------------------------------------------------*/
+  #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+    SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2));  /* set CP10 and CP11 Full Access */
+  #endif
+
+#if defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM)
+  SystemInit_ExtMemCtl(); 
+#endif /* DATA_IN_ExtSRAM || DATA_IN_ExtSDRAM */
+
+  /* Configure the Vector Table location -------------------------------------*/
+#if defined(USER_VECT_TAB_ADDRESS)
+  SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
+#endif /* USER_VECT_TAB_ADDRESS */
+}
+
+/**
+   * @brief  Update SystemCoreClock variable according to Clock Register Values.
+  *         The SystemCoreClock variable contains the core clock (HCLK), it can
+  *         be used by the user application to setup the SysTick timer or configure
+  *         other parameters.
+  *           
+  * @note   Each time the core clock (HCLK) changes, this function must be called
+  *         to update SystemCoreClock variable value. Otherwise, any configuration
+  *         based on this variable will be incorrect.         
+  *     
+  * @note   - The system frequency computed by this function is not the real 
+  *           frequency in the chip. It is calculated based on the predefined 
+  *           constant and the selected clock source:
+  *             
+  *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
+  *                                              
+  *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
+  *                          
+  *           - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) 
+  *             or HSI_VALUE(*) multiplied/divided by the PLL factors.
+  *         
+  *         (*) HSI_VALUE is a constant defined in stm32f4xx_hal_conf.h file (default value
+  *             16 MHz) but the real value may vary depending on the variations
+  *             in voltage and temperature.   
+  *    
+  *         (**) HSE_VALUE is a constant defined in stm32f4xx_hal_conf.h file (its value
+  *              depends on the application requirements), user has to ensure that HSE_VALUE
+  *              is same as the real frequency of the crystal used. Otherwise, this function
+  *              may have wrong result.
+  *                
+  *         - The result of this function could be not correct when using fractional
+  *           value for HSE crystal.
+  *     
+  * @param  None
+  * @retval None
+  */
+void SystemCoreClockUpdate(void)
+{
+  uint32_t tmp, pllvco, pllp, pllsource, pllm;
+  
+  /* Get SYSCLK source -------------------------------------------------------*/
+  tmp = RCC->CFGR & RCC_CFGR_SWS;
+
+  switch (tmp)
+  {
+    case 0x00:  /* HSI used as system clock source */
+      SystemCoreClock = HSI_VALUE;
+      break;
+    case 0x04:  /* HSE used as system clock source */
+      SystemCoreClock = HSE_VALUE;
+      break;
+    case 0x08:  /* PLL used as system clock source */
+
+      /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N
+         SYSCLK = PLL_VCO / PLL_P
+         */    
+      pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) >> 22;
+      pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM;
+      
+      if (pllsource != 0)
+      {
+        /* HSE used as PLL clock source */
+        pllvco = (HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6);
+      }
+      else
+      {
+        /* HSI used as PLL clock source */
+        pllvco = (HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6);
+      }
+
+      pllp = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >>16) + 1 ) *2;
+      SystemCoreClock = pllvco/pllp;
+      break;
+    default:
+      SystemCoreClock = HSI_VALUE;
+      break;
+  }
+  /* Compute HCLK frequency --------------------------------------------------*/
+  /* Get HCLK prescaler */
+  tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
+  /* HCLK frequency */
+  SystemCoreClock >>= tmp;
+}
+
+#if defined (DATA_IN_ExtSRAM) && defined (DATA_IN_ExtSDRAM)
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)\
+ || defined(STM32F469xx) || defined(STM32F479xx)
+/**
+  * @brief  Setup the external memory controller.
+  *         Called in startup_stm32f4xx.s before jump to main.
+  *         This function configures the external memories (SRAM/SDRAM)
+  *         This SRAM/SDRAM will be used as program data memory (including heap and stack).
+  * @param  None
+  * @retval None
+  */
+void SystemInit_ExtMemCtl(void)
+{
+  __IO uint32_t tmp = 0x00;
+
+  register uint32_t tmpreg = 0, timeout = 0xFFFF;
+  register __IO uint32_t index;
+
+  /* Enable GPIOC, GPIOD, GPIOE, GPIOF, GPIOG, GPIOH and GPIOI interface clock */
+  RCC->AHB1ENR |= 0x000001F8;
+
+  /* Delay after an RCC peripheral clock enabling */
+  tmp = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOCEN);
+  
+  /* Connect PDx pins to FMC Alternate function */
+  GPIOD->AFR[0]  = 0x00CCC0CC;
+  GPIOD->AFR[1]  = 0xCCCCCCCC;
+  /* Configure PDx pins in Alternate function mode */  
+  GPIOD->MODER   = 0xAAAA0A8A;
+  /* Configure PDx pins speed to 100 MHz */  
+  GPIOD->OSPEEDR = 0xFFFF0FCF;
+  /* Configure PDx pins Output type to push-pull */  
+  GPIOD->OTYPER  = 0x00000000;
+  /* No pull-up, pull-down for PDx pins */ 
+  GPIOD->PUPDR   = 0x00000000;
+
+  /* Connect PEx pins to FMC Alternate function */
+  GPIOE->AFR[0]  = 0xC00CC0CC;
+  GPIOE->AFR[1]  = 0xCCCCCCCC;
+  /* Configure PEx pins in Alternate function mode */ 
+  GPIOE->MODER   = 0xAAAA828A;
+  /* Configure PEx pins speed to 100 MHz */ 
+  GPIOE->OSPEEDR = 0xFFFFC3CF;
+  /* Configure PEx pins Output type to push-pull */  
+  GPIOE->OTYPER  = 0x00000000;
+  /* No pull-up, pull-down for PEx pins */ 
+  GPIOE->PUPDR   = 0x00000000;
+  
+  /* Connect PFx pins to FMC Alternate function */
+  GPIOF->AFR[0]  = 0xCCCCCCCC;
+  GPIOF->AFR[1]  = 0xCCCCCCCC;
+  /* Configure PFx pins in Alternate function mode */   
+  GPIOF->MODER   = 0xAA800AAA;
+  /* Configure PFx pins speed to 50 MHz */ 
+  GPIOF->OSPEEDR = 0xAA800AAA;
+  /* Configure PFx pins Output type to push-pull */  
+  GPIOF->OTYPER  = 0x00000000;
+  /* No pull-up, pull-down for PFx pins */ 
+  GPIOF->PUPDR   = 0x00000000;
+
+  /* Connect PGx pins to FMC Alternate function */
+  GPIOG->AFR[0]  = 0xCCCCCCCC;
+  GPIOG->AFR[1]  = 0xCCCCCCCC;
+  /* Configure PGx pins in Alternate function mode */ 
+  GPIOG->MODER   = 0xAAAAAAAA;
+  /* Configure PGx pins speed to 50 MHz */ 
+  GPIOG->OSPEEDR = 0xAAAAAAAA;
+  /* Configure PGx pins Output type to push-pull */  
+  GPIOG->OTYPER  = 0x00000000;
+  /* No pull-up, pull-down for PGx pins */ 
+  GPIOG->PUPDR   = 0x00000000;
+  
+  /* Connect PHx pins to FMC Alternate function */
+  GPIOH->AFR[0]  = 0x00C0CC00;
+  GPIOH->AFR[1]  = 0xCCCCCCCC;
+  /* Configure PHx pins in Alternate function mode */ 
+  GPIOH->MODER   = 0xAAAA08A0;
+  /* Configure PHx pins speed to 50 MHz */ 
+  GPIOH->OSPEEDR = 0xAAAA08A0;
+  /* Configure PHx pins Output type to push-pull */  
+  GPIOH->OTYPER  = 0x00000000;
+  /* No pull-up, pull-down for PHx pins */ 
+  GPIOH->PUPDR   = 0x00000000;
+  
+  /* Connect PIx pins to FMC Alternate function */
+  GPIOI->AFR[0]  = 0xCCCCCCCC;
+  GPIOI->AFR[1]  = 0x00000CC0;
+  /* Configure PIx pins in Alternate function mode */ 
+  GPIOI->MODER   = 0x0028AAAA;
+  /* Configure PIx pins speed to 50 MHz */ 
+  GPIOI->OSPEEDR = 0x0028AAAA;
+  /* Configure PIx pins Output type to push-pull */  
+  GPIOI->OTYPER  = 0x00000000;
+  /* No pull-up, pull-down for PIx pins */ 
+  GPIOI->PUPDR   = 0x00000000;
+  
+/*-- FMC Configuration -------------------------------------------------------*/
+  /* Enable the FMC interface clock */
+  RCC->AHB3ENR |= 0x00000001;
+  /* Delay after an RCC peripheral clock enabling */
+  tmp = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN);
+
+  FMC_Bank5_6->SDCR[0] = 0x000019E4;
+  FMC_Bank5_6->SDTR[0] = 0x01115351;      
+  
+  /* SDRAM initialization sequence */
+  /* Clock enable command */
+  FMC_Bank5_6->SDCMR = 0x00000011; 
+  tmpreg = FMC_Bank5_6->SDSR & 0x00000020; 
+  while((tmpreg != 0) && (timeout-- > 0))
+  {
+    tmpreg = FMC_Bank5_6->SDSR & 0x00000020; 
+  }
+
+  /* Delay */
+  for (index = 0; index<1000; index++);
+  
+  /* PALL command */
+  FMC_Bank5_6->SDCMR = 0x00000012;           
+  tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
+  timeout = 0xFFFF;
+  while((tmpreg != 0) && (timeout-- > 0))
+  {
+    tmpreg = FMC_Bank5_6->SDSR & 0x00000020; 
+  }
+  
+  /* Auto refresh command */
+  FMC_Bank5_6->SDCMR = 0x00000073;
+  tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
+  timeout = 0xFFFF;
+  while((tmpreg != 0) && (timeout-- > 0))
+  {
+    tmpreg = FMC_Bank5_6->SDSR & 0x00000020; 
+  }
+ 
+  /* MRD register program */
+  FMC_Bank5_6->SDCMR = 0x00046014;
+  tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
+  timeout = 0xFFFF;
+  while((tmpreg != 0) && (timeout-- > 0))
+  {
+    tmpreg = FMC_Bank5_6->SDSR & 0x00000020; 
+  } 
+  
+  /* Set refresh count */
+  tmpreg = FMC_Bank5_6->SDRTR;
+  FMC_Bank5_6->SDRTR = (tmpreg | (0x0000027C<<1));
+  
+  /* Disable write protection */
+  tmpreg = FMC_Bank5_6->SDCR[0]; 
+  FMC_Bank5_6->SDCR[0] = (tmpreg & 0xFFFFFDFF);
+
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
+  /* Configure and enable Bank1_SRAM2 */
+  FMC_Bank1->BTCR[2]  = 0x00001011;
+  FMC_Bank1->BTCR[3]  = 0x00000201;
+  FMC_Bank1E->BWTR[2] = 0x0fffffff;
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */ 
+#if defined(STM32F469xx) || defined(STM32F479xx)
+  /* Configure and enable Bank1_SRAM2 */
+  FMC_Bank1->BTCR[2]  = 0x00001091;
+  FMC_Bank1->BTCR[3]  = 0x00110212;
+  FMC_Bank1E->BWTR[2] = 0x0fffffff;
+#endif /* STM32F469xx || STM32F479xx */
+
+  (void)(tmp); 
+}
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */
+#elif defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM)
+/**
+  * @brief  Setup the external memory controller.
+  *         Called in startup_stm32f4xx.s before jump to main.
+  *         This function configures the external memories (SRAM/SDRAM)
+  *         This SRAM/SDRAM will be used as program data memory (including heap and stack).
+  * @param  None
+  * @retval None
+  */
+void SystemInit_ExtMemCtl(void)
+{
+  __IO uint32_t tmp = 0x00;
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)\
+ || defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx)
+#if defined (DATA_IN_ExtSDRAM)
+  register uint32_t tmpreg = 0, timeout = 0xFFFF;
+  register __IO uint32_t index;
+
+#if defined(STM32F446xx)
+  /* Enable GPIOA, GPIOC, GPIOD, GPIOE, GPIOF, GPIOG interface
+      clock */
+  RCC->AHB1ENR |= 0x0000007D;
+#else
+  /* Enable GPIOC, GPIOD, GPIOE, GPIOF, GPIOG, GPIOH and GPIOI interface 
+      clock */
+  RCC->AHB1ENR |= 0x000001F8;
+#endif /* STM32F446xx */  
+  /* Delay after an RCC peripheral clock enabling */
+  tmp = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOCEN);
+  
+#if defined(STM32F446xx)
+  /* Connect PAx pins to FMC Alternate function */
+  GPIOA->AFR[0]  |= 0xC0000000;
+  GPIOA->AFR[1]  |= 0x00000000;
+  /* Configure PDx pins in Alternate function mode */
+  GPIOA->MODER   |= 0x00008000;
+  /* Configure PDx pins speed to 50 MHz */
+  GPIOA->OSPEEDR |= 0x00008000;
+  /* Configure PDx pins Output type to push-pull */
+  GPIOA->OTYPER  |= 0x00000000;
+  /* No pull-up, pull-down for PDx pins */
+  GPIOA->PUPDR   |= 0x00000000;
+
+  /* Connect PCx pins to FMC Alternate function */
+  GPIOC->AFR[0]  |= 0x00CC0000;
+  GPIOC->AFR[1]  |= 0x00000000;
+  /* Configure PDx pins in Alternate function mode */
+  GPIOC->MODER   |= 0x00000A00;
+  /* Configure PDx pins speed to 50 MHz */
+  GPIOC->OSPEEDR |= 0x00000A00;
+  /* Configure PDx pins Output type to push-pull */
+  GPIOC->OTYPER  |= 0x00000000;
+  /* No pull-up, pull-down for PDx pins */
+  GPIOC->PUPDR   |= 0x00000000;
+#endif /* STM32F446xx */
+
+  /* Connect PDx pins to FMC Alternate function */
+  GPIOD->AFR[0]  = 0x000000CC;
+  GPIOD->AFR[1]  = 0xCC000CCC;
+  /* Configure PDx pins in Alternate function mode */  
+  GPIOD->MODER   = 0xA02A000A;
+  /* Configure PDx pins speed to 50 MHz */  
+  GPIOD->OSPEEDR = 0xA02A000A;
+  /* Configure PDx pins Output type to push-pull */  
+  GPIOD->OTYPER  = 0x00000000;
+  /* No pull-up, pull-down for PDx pins */ 
+  GPIOD->PUPDR   = 0x00000000;
+
+  /* Connect PEx pins to FMC Alternate function */
+  GPIOE->AFR[0]  = 0xC00000CC;
+  GPIOE->AFR[1]  = 0xCCCCCCCC;
+  /* Configure PEx pins in Alternate function mode */ 
+  GPIOE->MODER   = 0xAAAA800A;
+  /* Configure PEx pins speed to 50 MHz */ 
+  GPIOE->OSPEEDR = 0xAAAA800A;
+  /* Configure PEx pins Output type to push-pull */  
+  GPIOE->OTYPER  = 0x00000000;
+  /* No pull-up, pull-down for PEx pins */ 
+  GPIOE->PUPDR   = 0x00000000;
+
+  /* Connect PFx pins to FMC Alternate function */
+  GPIOF->AFR[0]  = 0xCCCCCCCC;
+  GPIOF->AFR[1]  = 0xCCCCCCCC;
+  /* Configure PFx pins in Alternate function mode */   
+  GPIOF->MODER   = 0xAA800AAA;
+  /* Configure PFx pins speed to 50 MHz */ 
+  GPIOF->OSPEEDR = 0xAA800AAA;
+  /* Configure PFx pins Output type to push-pull */  
+  GPIOF->OTYPER  = 0x00000000;
+  /* No pull-up, pull-down for PFx pins */ 
+  GPIOF->PUPDR   = 0x00000000;
+
+  /* Connect PGx pins to FMC Alternate function */
+  GPIOG->AFR[0]  = 0xCCCCCCCC;
+  GPIOG->AFR[1]  = 0xCCCCCCCC;
+  /* Configure PGx pins in Alternate function mode */ 
+  GPIOG->MODER   = 0xAAAAAAAA;
+  /* Configure PGx pins speed to 50 MHz */ 
+  GPIOG->OSPEEDR = 0xAAAAAAAA;
+  /* Configure PGx pins Output type to push-pull */  
+  GPIOG->OTYPER  = 0x00000000;
+  /* No pull-up, pull-down for PGx pins */ 
+  GPIOG->PUPDR   = 0x00000000;
+
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)\
+ || defined(STM32F469xx) || defined(STM32F479xx)  
+  /* Connect PHx pins to FMC Alternate function */
+  GPIOH->AFR[0]  = 0x00C0CC00;
+  GPIOH->AFR[1]  = 0xCCCCCCCC;
+  /* Configure PHx pins in Alternate function mode */ 
+  GPIOH->MODER   = 0xAAAA08A0;
+  /* Configure PHx pins speed to 50 MHz */ 
+  GPIOH->OSPEEDR = 0xAAAA08A0;
+  /* Configure PHx pins Output type to push-pull */  
+  GPIOH->OTYPER  = 0x00000000;
+  /* No pull-up, pull-down for PHx pins */ 
+  GPIOH->PUPDR   = 0x00000000;
+  
+  /* Connect PIx pins to FMC Alternate function */
+  GPIOI->AFR[0]  = 0xCCCCCCCC;
+  GPIOI->AFR[1]  = 0x00000CC0;
+  /* Configure PIx pins in Alternate function mode */ 
+  GPIOI->MODER   = 0x0028AAAA;
+  /* Configure PIx pins speed to 50 MHz */ 
+  GPIOI->OSPEEDR = 0x0028AAAA;
+  /* Configure PIx pins Output type to push-pull */  
+  GPIOI->OTYPER  = 0x00000000;
+  /* No pull-up, pull-down for PIx pins */ 
+  GPIOI->PUPDR   = 0x00000000;
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */
+  
+/*-- FMC Configuration -------------------------------------------------------*/
+  /* Enable the FMC interface clock */
+  RCC->AHB3ENR |= 0x00000001;
+  /* Delay after an RCC peripheral clock enabling */
+  tmp = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN);
+
+  /* Configure and enable SDRAM bank1 */
+#if defined(STM32F446xx)
+  FMC_Bank5_6->SDCR[0] = 0x00001954;
+#else  
+  FMC_Bank5_6->SDCR[0] = 0x000019E4;
+#endif /* STM32F446xx */
+  FMC_Bank5_6->SDTR[0] = 0x01115351;      
+  
+  /* SDRAM initialization sequence */
+  /* Clock enable command */
+  FMC_Bank5_6->SDCMR = 0x00000011; 
+  tmpreg = FMC_Bank5_6->SDSR & 0x00000020; 
+  while((tmpreg != 0) && (timeout-- > 0))
+  {
+    tmpreg = FMC_Bank5_6->SDSR & 0x00000020; 
+  }
+
+  /* Delay */
+  for (index = 0; index<1000; index++);
+  
+  /* PALL command */
+  FMC_Bank5_6->SDCMR = 0x00000012;           
+  tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
+  timeout = 0xFFFF;
+  while((tmpreg != 0) && (timeout-- > 0))
+  {
+    tmpreg = FMC_Bank5_6->SDSR & 0x00000020; 
+  }
+  
+  /* Auto refresh command */
+#if defined(STM32F446xx)
+  FMC_Bank5_6->SDCMR = 0x000000F3;
+#else  
+  FMC_Bank5_6->SDCMR = 0x00000073;
+#endif /* STM32F446xx */
+  tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
+  timeout = 0xFFFF;
+  while((tmpreg != 0) && (timeout-- > 0))
+  {
+    tmpreg = FMC_Bank5_6->SDSR & 0x00000020; 
+  }
+ 
+  /* MRD register program */
+#if defined(STM32F446xx)
+  FMC_Bank5_6->SDCMR = 0x00044014;
+#else  
+  FMC_Bank5_6->SDCMR = 0x00046014;
+#endif /* STM32F446xx */
+  tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
+  timeout = 0xFFFF;
+  while((tmpreg != 0) && (timeout-- > 0))
+  {
+    tmpreg = FMC_Bank5_6->SDSR & 0x00000020; 
+  } 
+  
+  /* Set refresh count */
+  tmpreg = FMC_Bank5_6->SDRTR;
+#if defined(STM32F446xx)
+  FMC_Bank5_6->SDRTR = (tmpreg | (0x0000050C<<1));
+#else    
+  FMC_Bank5_6->SDRTR = (tmpreg | (0x0000027C<<1));
+#endif /* STM32F446xx */
+  
+  /* Disable write protection */
+  tmpreg = FMC_Bank5_6->SDCR[0]; 
+  FMC_Bank5_6->SDCR[0] = (tmpreg & 0xFFFFFDFF);
+#endif /* DATA_IN_ExtSDRAM */
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx */
+
+#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx)\
+ || defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)\
+ || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx)
+
+#if defined(DATA_IN_ExtSRAM)
+/*-- GPIOs Configuration -----------------------------------------------------*/
+   /* Enable GPIOD, GPIOE, GPIOF and GPIOG interface clock */
+  RCC->AHB1ENR   |= 0x00000078;
+  /* Delay after an RCC peripheral clock enabling */
+  tmp = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);
+  
+  /* Connect PDx pins to FMC Alternate function */
+  GPIOD->AFR[0]  = 0x00CCC0CC;
+  GPIOD->AFR[1]  = 0xCCCCCCCC;
+  /* Configure PDx pins in Alternate function mode */  
+  GPIOD->MODER   = 0xAAAA0A8A;
+  /* Configure PDx pins speed to 100 MHz */  
+  GPIOD->OSPEEDR = 0xFFFF0FCF;
+  /* Configure PDx pins Output type to push-pull */  
+  GPIOD->OTYPER  = 0x00000000;
+  /* No pull-up, pull-down for PDx pins */ 
+  GPIOD->PUPDR   = 0x00000000;
+
+  /* Connect PEx pins to FMC Alternate function */
+  GPIOE->AFR[0]  = 0xC00CC0CC;
+  GPIOE->AFR[1]  = 0xCCCCCCCC;
+  /* Configure PEx pins in Alternate function mode */ 
+  GPIOE->MODER   = 0xAAAA828A;
+  /* Configure PEx pins speed to 100 MHz */ 
+  GPIOE->OSPEEDR = 0xFFFFC3CF;
+  /* Configure PEx pins Output type to push-pull */  
+  GPIOE->OTYPER  = 0x00000000;
+  /* No pull-up, pull-down for PEx pins */ 
+  GPIOE->PUPDR   = 0x00000000;
+
+  /* Connect PFx pins to FMC Alternate function */
+  GPIOF->AFR[0]  = 0x00CCCCCC;
+  GPIOF->AFR[1]  = 0xCCCC0000;
+  /* Configure PFx pins in Alternate function mode */   
+  GPIOF->MODER   = 0xAA000AAA;
+  /* Configure PFx pins speed to 100 MHz */ 
+  GPIOF->OSPEEDR = 0xFF000FFF;
+  /* Configure PFx pins Output type to push-pull */  
+  GPIOF->OTYPER  = 0x00000000;
+  /* No pull-up, pull-down for PFx pins */ 
+  GPIOF->PUPDR   = 0x00000000;
+
+  /* Connect PGx pins to FMC Alternate function */
+  GPIOG->AFR[0]  = 0x00CCCCCC;
+  GPIOG->AFR[1]  = 0x000000C0;
+  /* Configure PGx pins in Alternate function mode */ 
+  GPIOG->MODER   = 0x00085AAA;
+  /* Configure PGx pins speed to 100 MHz */ 
+  GPIOG->OSPEEDR = 0x000CAFFF;
+  /* Configure PGx pins Output type to push-pull */  
+  GPIOG->OTYPER  = 0x00000000;
+  /* No pull-up, pull-down for PGx pins */ 
+  GPIOG->PUPDR   = 0x00000000;
+  
+/*-- FMC/FSMC Configuration --------------------------------------------------*/
+  /* Enable the FMC/FSMC interface clock */
+  RCC->AHB3ENR         |= 0x00000001;
+
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
+  /* Delay after an RCC peripheral clock enabling */
+  tmp = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN);
+  /* Configure and enable Bank1_SRAM2 */
+  FMC_Bank1->BTCR[2]  = 0x00001011;
+  FMC_Bank1->BTCR[3]  = 0x00000201;
+  FMC_Bank1E->BWTR[2] = 0x0fffffff;
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */ 
+#if defined(STM32F469xx) || defined(STM32F479xx)
+  /* Delay after an RCC peripheral clock enabling */
+  tmp = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN);
+  /* Configure and enable Bank1_SRAM2 */
+  FMC_Bank1->BTCR[2]  = 0x00001091;
+  FMC_Bank1->BTCR[3]  = 0x00110212;
+  FMC_Bank1E->BWTR[2] = 0x0fffffff;
+#endif /* STM32F469xx || STM32F479xx */
+#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx)|| defined(STM32F417xx)\
+   || defined(STM32F412Zx) || defined(STM32F412Vx)
+  /* Delay after an RCC peripheral clock enabling */
+  tmp = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FSMCEN);
+  /* Configure and enable Bank1_SRAM2 */
+  FSMC_Bank1->BTCR[2]  = 0x00001011;
+  FSMC_Bank1->BTCR[3]  = 0x00000201;
+  FSMC_Bank1E->BWTR[2] = 0x0FFFFFFF;
+#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F412Zx || STM32F412Vx */
+
+#endif /* DATA_IN_ExtSRAM */
+#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx ||\
+          STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx || STM32F412Zx || STM32F412Vx  */ 
+  (void)(tmp); 
+}
+#endif /* DATA_IN_ExtSRAM && DATA_IN_ExtSDRAM */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */

Core/Src/tim.c

@@ -0,0 +1,156 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    tim.c
+  * @brief   This file provides code for the configuration
+  *          of the TIM instances.
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2025 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+/* Includes ------------------------------------------------------------------*/
+#include "tim.h"
+
+/* USER CODE BEGIN 0 */
+#include "can.h"
+#include "UDS.h"
+
+/* USER CODE END 0 */
+
+TIM_HandleTypeDef htim2;
+
+/* TIM2 init function */
+void MX_TIM2_Init(void)
+{
+
+  /* USER CODE BEGIN TIM2_Init 0 */
+
+  /* USER CODE END TIM2_Init 0 */
+
+  TIM_ClockConfigTypeDef sClockSourceConfig = {0};
+  TIM_MasterConfigTypeDef sMasterConfig = {0};
+
+  /* USER CODE BEGIN TIM2_Init 1 */
+
+  /* USER CODE END TIM2_Init 1 */
+  htim2.Instance = TIM2;
+  htim2.Init.Prescaler = 84-1;
+  htim2.Init.CounterMode = TIM_COUNTERMODE_UP;
+  htim2.Init.Period = 1000;
+  htim2.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1;
+  htim2.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE;
+  if (HAL_TIM_Base_Init(&htim2) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  sClockSourceConfig.ClockSource = TIM_CLOCKSOURCE_INTERNAL;
+  if (HAL_TIM_ConfigClockSource(&htim2, &sClockSourceConfig) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET;
+  sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE;
+  if (HAL_TIMEx_MasterConfigSynchronization(&htim2, &sMasterConfig) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  /* USER CODE BEGIN TIM2_Init 2 */
+
+  /* USER CODE END TIM2_Init 2 */
+
+}
+
+void HAL_TIM_Base_MspInit(TIM_HandleTypeDef* tim_baseHandle)
+{
+
+  if(tim_baseHandle->Instance==TIM2)
+  {
+  /* USER CODE BEGIN TIM2_MspInit 0 */
+
+  /* USER CODE END TIM2_MspInit 0 */
+    /* TIM2 clock enable */
+    __HAL_RCC_TIM2_CLK_ENABLE();
+
+    /* TIM2 interrupt Init */
+    HAL_NVIC_SetPriority(TIM2_IRQn, 0, 0);
+    HAL_NVIC_EnableIRQ(TIM2_IRQn);
+  /* USER CODE BEGIN TIM2_MspInit 1 */
+
+  /* USER CODE END TIM2_MspInit 1 */
+  }
+}
+
+void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef* tim_baseHandle)
+{
+
+  if(tim_baseHandle->Instance==TIM2)
+  {
+  /* USER CODE BEGIN TIM2_MspDeInit 0 */
+
+  /* USER CODE END TIM2_MspDeInit 0 */
+    /* Peripheral clock disable */
+    __HAL_RCC_TIM2_CLK_DISABLE();
+
+    /* TIM2 interrupt Deinit */
+    HAL_NVIC_DisableIRQ(TIM2_IRQn);
+  /* USER CODE BEGIN TIM2_MspDeInit 1 */
+
+  /* USER CODE END TIM2_MspDeInit 1 */
+  }
+}
+
+/* USER CODE BEGIN 1 */
+uint8_t TxBuf[8];
+uint8_t ota_start_flag = 0;
+uint32_t system_time_ms = 0;           // 系统运行时间，用于判断上电等待接收升级指令
+uint8_t app_error_flag = 0;
+uint32_t app_error_counter = 0;
+void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim)
+{
+	if (htim->Instance == TIM2)
+	{
+		i15765_update();
+
+		if(ota_start_flag == 0)
+		{
+			system_time_ms++;       // 系统时间加1ms
+			if(system_time_ms >= WAIT_OTA_TIME_MS)
+			{
+				system_time_ms = WAIT_OTA_TIME_MS;
+			}
+		}
+		else
+		{
+			system_time_ms = 0;
+		}
+
+		if(app_error_flag == 1)
+		{
+			app_error_counter++;
+			if(app_error_counter >= 1000)
+			{
+				app_error_counter = 0;
+				uint16_t hardware_version = *(volatile uint32_t*)0x08000188;
+				TxBuf[0] = 0x04;
+				TxBuf[1] = 0x50;
+				TxBuf[2] = 0x02;
+				TxBuf[3] = hardware_version >> 8;
+				TxBuf[4] = hardware_version & 0xFF;;
+				TxBuf[5] = 0x55;
+				TxBuf[6] = 0x55;
+				TxBuf[7] = 0x55;
+				CAN_SendData(1, 2, 0x709, TxBuf,8);
+			}
+		}
+	}
+}
+/* USER CODE END 1 */

Core/Startup/startup_stm32f405rgtx.s

@@ -0,0 +1,501 @@
+/**
+  ******************************************************************************
+  * @file      startup_stm32f405xx.s
+  * @author    MCD Application Team
+  * @brief     STM32F405xx Devices vector table for GCC based toolchains. 
+  *            This module performs:
+  *                - Set the initial SP
+  *                - Set the initial PC == Reset_Handler,
+  *                - Set the vector table entries with the exceptions ISR address
+  *                - Branches to main in the C library (which eventually
+  *                  calls main()).
+  *            After Reset the Cortex-M4 processor is in Thread mode,
+  *            priority is Privileged, and the Stack is set to Main.
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+    
+  .syntax unified
+  .cpu cortex-m4
+  .fpu softvfp
+  .thumb
+
+.global  g_pfnVectors
+.global  Default_Handler
+
+/* start address for the initialization values of the .data section. 
+defined in linker script */
+.word  _sidata
+/* start address for the .data section. defined in linker script */  
+.word  _sdata
+/* end address for the .data section. defined in linker script */
+.word  _edata
+/* start address for the .bss section. defined in linker script */
+.word  _sbss
+/* end address for the .bss section. defined in linker script */
+.word  _ebss
+/* stack used for SystemInit_ExtMemCtl; always internal RAM used */
+
+/**
+ * @brief  This is the code that gets called when the processor first
+ *          starts execution following a reset event. Only the absolutely
+ *          necessary set is performed, after which the application
+ *          supplied main() routine is called. 
+ * @param  None
+ * @retval : None
+*/
+
+    .section  .text.Reset_Handler
+  .weak  Reset_Handler
+  .type  Reset_Handler, %function
+Reset_Handler:  
+  ldr   sp, =_estack     /* set stack pointer */
+  
+/* Call the clock system initialization function.*/
+  bl  SystemInit  
+
+/* Copy the data segment initializers from flash to SRAM */  
+  ldr r0, =_sdata
+  ldr r1, =_edata
+  ldr r2, =_sidata
+  movs r3, #0
+  b LoopCopyDataInit
+
+CopyDataInit:
+  ldr r4, [r2, r3]
+  str r4, [r0, r3]
+  adds r3, r3, #4
+
+LoopCopyDataInit:
+  adds r4, r0, r3
+  cmp r4, r1
+  bcc CopyDataInit
+  
+/* Zero fill the bss segment. */
+  ldr r2, =_sbss
+  ldr r4, =_ebss
+  movs r3, #0
+  b LoopFillZerobss
+
+FillZerobss:
+  str  r3, [r2]
+  adds r2, r2, #4
+
+LoopFillZerobss:
+  cmp r2, r4
+  bcc FillZerobss
+ 
+/* Call static constructors */
+    bl __libc_init_array
+/* Call the application's entry point.*/
+  bl  main
+  bx  lr    
+.size  Reset_Handler, .-Reset_Handler
+
+/**
+ * @brief  This is the code that gets called when the processor receives an 
+ *         unexpected interrupt.  This simply enters an infinite loop, preserving
+ *         the system state for examination by a debugger.
+ * @param  None     
+ * @retval None       
+*/
+    .section  .text.Default_Handler,"ax",%progbits
+Default_Handler:
+Infinite_Loop:
+  b  Infinite_Loop
+  .size  Default_Handler, .-Default_Handler
+/******************************************************************************
+*
+* The minimal vector table for a Cortex M3. Note that the proper constructs
+* must be placed on this to ensure that it ends up at physical address
+* 0x0000.0000.
+* 
+*******************************************************************************/
+   .section  .isr_vector,"a",%progbits
+  .type  g_pfnVectors, %object
+    
+
+	
+g_pfnVectors:
+  .word  _estack
+  .word  Reset_Handler
+
+  .word  NMI_Handler
+  .word  HardFault_Handler
+  .word  MemManage_Handler
+  .word  BusFault_Handler
+  .word  UsageFault_Handler
+  .word  0
+  .word  0
+  .word  0
+  .word  0
+  .word  SVC_Handler
+  .word  DebugMon_Handler
+  .word  0
+  .word  PendSV_Handler
+  .word  SysTick_Handler
+  
+  /* External Interrupts */
+  .word     WWDG_IRQHandler                   /* Window WatchDog              */                                        
+  .word     PVD_IRQHandler                    /* PVD through EXTI Line detection */                        
+  .word     TAMP_STAMP_IRQHandler             /* Tamper and TimeStamps through the EXTI line */            
+  .word     RTC_WKUP_IRQHandler               /* RTC Wakeup through the EXTI line */                      
+  .word     FLASH_IRQHandler                  /* FLASH                        */                                          
+  .word     RCC_IRQHandler                    /* RCC                          */                                            
+  .word     EXTI0_IRQHandler                  /* EXTI Line0                   */                        
+  .word     EXTI1_IRQHandler                  /* EXTI Line1                   */                          
+  .word     EXTI2_IRQHandler                  /* EXTI Line2                   */                          
+  .word     EXTI3_IRQHandler                  /* EXTI Line3                   */                          
+  .word     EXTI4_IRQHandler                  /* EXTI Line4                   */                          
+  .word     DMA1_Stream0_IRQHandler           /* DMA1 Stream 0                */                  
+  .word     DMA1_Stream1_IRQHandler           /* DMA1 Stream 1                */                   
+  .word     DMA1_Stream2_IRQHandler           /* DMA1 Stream 2                */                   
+  .word     DMA1_Stream3_IRQHandler           /* DMA1 Stream 3                */                   
+  .word     DMA1_Stream4_IRQHandler           /* DMA1 Stream 4                */                   
+  .word     DMA1_Stream5_IRQHandler           /* DMA1 Stream 5                */                   
+  .word     DMA1_Stream6_IRQHandler           /* DMA1 Stream 6                */                   
+  .word     ADC_IRQHandler                    /* ADC1, ADC2 and ADC3s         */                   
+  .word     CAN1_TX_IRQHandler                /* CAN1 TX                      */                         
+  .word     CAN1_RX0_IRQHandler               /* CAN1 RX0                     */                          
+  .word     CAN1_RX1_IRQHandler               /* CAN1 RX1                     */                          
+  .word     CAN1_SCE_IRQHandler               /* CAN1 SCE                     */                          
+  .word     EXTI9_5_IRQHandler                /* External Line[9:5]s          */                          
+  .word     TIM1_BRK_TIM9_IRQHandler          /* TIM1 Break and TIM9          */         
+  .word     TIM1_UP_TIM10_IRQHandler          /* TIM1 Update and TIM10        */         
+  .word     TIM1_TRG_COM_TIM11_IRQHandler     /* TIM1 Trigger and Commutation and TIM11 */
+  .word     TIM1_CC_IRQHandler                /* TIM1 Capture Compare         */                          
+  .word     TIM2_IRQHandler                   /* TIM2                         */                   
+  .word     TIM3_IRQHandler                   /* TIM3                         */                   
+  .word     TIM4_IRQHandler                   /* TIM4                         */                   
+  .word     I2C1_EV_IRQHandler                /* I2C1 Event                   */                          
+  .word     I2C1_ER_IRQHandler                /* I2C1 Error                   */                          
+  .word     I2C2_EV_IRQHandler                /* I2C2 Event                   */                          
+  .word     I2C2_ER_IRQHandler                /* I2C2 Error                   */                            
+  .word     SPI1_IRQHandler                   /* SPI1                         */                   
+  .word     SPI2_IRQHandler                   /* SPI2                         */                   
+  .word     USART1_IRQHandler                 /* USART1                       */                   
+  .word     USART2_IRQHandler                 /* USART2                       */                   
+  .word     USART3_IRQHandler                 /* USART3                       */                   
+  .word     EXTI15_10_IRQHandler              /* External Line[15:10]s        */                          
+  .word     RTC_Alarm_IRQHandler              /* RTC Alarm (A and B) through EXTI Line */                 
+  .word     OTG_FS_WKUP_IRQHandler            /* USB OTG FS Wakeup through EXTI line */                       
+  .word     TIM8_BRK_TIM12_IRQHandler         /* TIM8 Break and TIM12         */         
+  .word     TIM8_UP_TIM13_IRQHandler          /* TIM8 Update and TIM13        */         
+  .word     TIM8_TRG_COM_TIM14_IRQHandler     /* TIM8 Trigger and Commutation and TIM14 */
+  .word     TIM8_CC_IRQHandler                /* TIM8 Capture Compare         */                          
+  .word     DMA1_Stream7_IRQHandler           /* DMA1 Stream7                 */                          
+  .word     FSMC_IRQHandler                   /* FSMC                         */                   
+  .word     SDIO_IRQHandler                   /* SDIO                         */                   
+  .word     TIM5_IRQHandler                   /* TIM5                         */                   
+  .word     SPI3_IRQHandler                   /* SPI3                         */                   
+  .word     UART4_IRQHandler                  /* UART4                        */                   
+  .word     UART5_IRQHandler                  /* UART5                        */                   
+  .word     TIM6_DAC_IRQHandler               /* TIM6 and DAC1&2 underrun errors */                   
+  .word     TIM7_IRQHandler                   /* TIM7                         */
+  .word     DMA2_Stream0_IRQHandler           /* DMA2 Stream 0                */                   
+  .word     DMA2_Stream1_IRQHandler           /* DMA2 Stream 1                */                   
+  .word     DMA2_Stream2_IRQHandler           /* DMA2 Stream 2                */                   
+  .word     DMA2_Stream3_IRQHandler           /* DMA2 Stream 3                */                   
+  .word     DMA2_Stream4_IRQHandler           /* DMA2 Stream 4                */                   
+  .word     0                                 /* Reserved                     */                   
+  .word     0                                 /* Reserved                     */                     
+  .word     CAN2_TX_IRQHandler                /* CAN2 TX                      */                          
+  .word     CAN2_RX0_IRQHandler               /* CAN2 RX0                     */                          
+  .word     CAN2_RX1_IRQHandler               /* CAN2 RX1                     */                          
+  .word     CAN2_SCE_IRQHandler               /* CAN2 SCE                     */                          
+  .word     OTG_FS_IRQHandler                 /* USB OTG FS                   */                   
+  .word     DMA2_Stream5_IRQHandler           /* DMA2 Stream 5                */                   
+  .word     DMA2_Stream6_IRQHandler           /* DMA2 Stream 6                */                   
+  .word     DMA2_Stream7_IRQHandler           /* DMA2 Stream 7                */                   
+  .word     USART6_IRQHandler                 /* USART6                       */                    
+  .word     I2C3_EV_IRQHandler                /* I2C3 event                   */                          
+  .word     I2C3_ER_IRQHandler                /* I2C3 error                   */                          
+  .word     OTG_HS_EP1_OUT_IRQHandler         /* USB OTG HS End Point 1 Out   */                   
+  .word     OTG_HS_EP1_IN_IRQHandler          /* USB OTG HS End Point 1 In    */                   
+  .word     OTG_HS_WKUP_IRQHandler            /* USB OTG HS Wakeup through EXTI */                         
+  .word     OTG_HS_IRQHandler                 /* USB OTG HS                   */                   
+  .word     0                                 /* Reserved                         */                   
+  .word     0                                 /* Reserved                  */                   
+  .word     HASH_RNG_IRQHandler               /* Hash and Rng                 */
+  .word     FPU_IRQHandler                    /* FPU                          */
+
+                      
+
+  .size  g_pfnVectors, .-g_pfnVectors
+
+/*******************************************************************************
+*
+* Provide weak aliases for each Exception handler to the Default_Handler. 
+* As they are weak aliases, any function with the same name will override 
+* this definition.
+* 
+*******************************************************************************/
+   .weak      NMI_Handler
+   .thumb_set NMI_Handler,Default_Handler
+  
+   .weak      HardFault_Handler
+   .thumb_set HardFault_Handler,Default_Handler
+  
+   .weak      MemManage_Handler
+   .thumb_set MemManage_Handler,Default_Handler
+  
+   .weak      BusFault_Handler
+   .thumb_set BusFault_Handler,Default_Handler
+
+   .weak      UsageFault_Handler
+   .thumb_set UsageFault_Handler,Default_Handler
+
+   .weak      SVC_Handler
+   .thumb_set SVC_Handler,Default_Handler
+
+   .weak      DebugMon_Handler
+   .thumb_set DebugMon_Handler,Default_Handler
+
+   .weak      PendSV_Handler
+   .thumb_set PendSV_Handler,Default_Handler
+
+   .weak      SysTick_Handler
+   .thumb_set SysTick_Handler,Default_Handler              
+  
+   .weak      WWDG_IRQHandler                   
+   .thumb_set WWDG_IRQHandler,Default_Handler      
+                  
+   .weak      PVD_IRQHandler      
+   .thumb_set PVD_IRQHandler,Default_Handler
+               
+   .weak      TAMP_STAMP_IRQHandler            
+   .thumb_set TAMP_STAMP_IRQHandler,Default_Handler
+            
+   .weak      RTC_WKUP_IRQHandler                  
+   .thumb_set RTC_WKUP_IRQHandler,Default_Handler
+            
+   .weak      FLASH_IRQHandler         
+   .thumb_set FLASH_IRQHandler,Default_Handler
+                  
+   .weak      RCC_IRQHandler      
+   .thumb_set RCC_IRQHandler,Default_Handler
+                  
+   .weak      EXTI0_IRQHandler         
+   .thumb_set EXTI0_IRQHandler,Default_Handler
+                  
+   .weak      EXTI1_IRQHandler         
+   .thumb_set EXTI1_IRQHandler,Default_Handler
+                     
+   .weak      EXTI2_IRQHandler         
+   .thumb_set EXTI2_IRQHandler,Default_Handler 
+                 
+   .weak      EXTI3_IRQHandler         
+   .thumb_set EXTI3_IRQHandler,Default_Handler
+                        
+   .weak      EXTI4_IRQHandler         
+   .thumb_set EXTI4_IRQHandler,Default_Handler
+                  
+   .weak      DMA1_Stream0_IRQHandler               
+   .thumb_set DMA1_Stream0_IRQHandler,Default_Handler
+         
+   .weak      DMA1_Stream1_IRQHandler               
+   .thumb_set DMA1_Stream1_IRQHandler,Default_Handler
+                  
+   .weak      DMA1_Stream2_IRQHandler               
+   .thumb_set DMA1_Stream2_IRQHandler,Default_Handler
+                  
+   .weak      DMA1_Stream3_IRQHandler               
+   .thumb_set DMA1_Stream3_IRQHandler,Default_Handler 
+                 
+   .weak      DMA1_Stream4_IRQHandler              
+   .thumb_set DMA1_Stream4_IRQHandler,Default_Handler
+                  
+   .weak      DMA1_Stream5_IRQHandler               
+   .thumb_set DMA1_Stream5_IRQHandler,Default_Handler
+                  
+   .weak      DMA1_Stream6_IRQHandler               
+   .thumb_set DMA1_Stream6_IRQHandler,Default_Handler
+                  
+   .weak      ADC_IRQHandler      
+   .thumb_set ADC_IRQHandler,Default_Handler
+               
+   .weak      CAN1_TX_IRQHandler   
+   .thumb_set CAN1_TX_IRQHandler,Default_Handler
+            
+   .weak      CAN1_RX0_IRQHandler                  
+   .thumb_set CAN1_RX0_IRQHandler,Default_Handler
+                           
+   .weak      CAN1_RX1_IRQHandler                  
+   .thumb_set CAN1_RX1_IRQHandler,Default_Handler
+            
+   .weak      CAN1_SCE_IRQHandler                  
+   .thumb_set CAN1_SCE_IRQHandler,Default_Handler
+            
+   .weak      EXTI9_5_IRQHandler   
+   .thumb_set EXTI9_5_IRQHandler,Default_Handler
+            
+   .weak      TIM1_BRK_TIM9_IRQHandler            
+   .thumb_set TIM1_BRK_TIM9_IRQHandler,Default_Handler
+            
+   .weak      TIM1_UP_TIM10_IRQHandler            
+   .thumb_set TIM1_UP_TIM10_IRQHandler,Default_Handler
+      
+   .weak      TIM1_TRG_COM_TIM11_IRQHandler      
+   .thumb_set TIM1_TRG_COM_TIM11_IRQHandler,Default_Handler
+      
+   .weak      TIM1_CC_IRQHandler   
+   .thumb_set TIM1_CC_IRQHandler,Default_Handler
+                  
+   .weak      TIM2_IRQHandler            
+   .thumb_set TIM2_IRQHandler,Default_Handler
+                  
+   .weak      TIM3_IRQHandler            
+   .thumb_set TIM3_IRQHandler,Default_Handler
+                  
+   .weak      TIM4_IRQHandler            
+   .thumb_set TIM4_IRQHandler,Default_Handler
+                  
+   .weak      I2C1_EV_IRQHandler   
+   .thumb_set I2C1_EV_IRQHandler,Default_Handler
+                     
+   .weak      I2C1_ER_IRQHandler   
+   .thumb_set I2C1_ER_IRQHandler,Default_Handler
+                     
+   .weak      I2C2_EV_IRQHandler   
+   .thumb_set I2C2_EV_IRQHandler,Default_Handler
+                  
+   .weak      I2C2_ER_IRQHandler   
+   .thumb_set I2C2_ER_IRQHandler,Default_Handler
+                           
+   .weak      SPI1_IRQHandler            
+   .thumb_set SPI1_IRQHandler,Default_Handler
+                        
+   .weak      SPI2_IRQHandler            
+   .thumb_set SPI2_IRQHandler,Default_Handler
+                  
+   .weak      USART1_IRQHandler      
+   .thumb_set USART1_IRQHandler,Default_Handler
+                     
+   .weak      USART2_IRQHandler      
+   .thumb_set USART2_IRQHandler,Default_Handler
+                     
+   .weak      USART3_IRQHandler      
+   .thumb_set USART3_IRQHandler,Default_Handler
+                  
+   .weak      EXTI15_10_IRQHandler               
+   .thumb_set EXTI15_10_IRQHandler,Default_Handler
+               
+   .weak      RTC_Alarm_IRQHandler               
+   .thumb_set RTC_Alarm_IRQHandler,Default_Handler
+            
+   .weak      OTG_FS_WKUP_IRQHandler         
+   .thumb_set OTG_FS_WKUP_IRQHandler,Default_Handler
+            
+   .weak      TIM8_BRK_TIM12_IRQHandler         
+   .thumb_set TIM8_BRK_TIM12_IRQHandler,Default_Handler
+         
+   .weak      TIM8_UP_TIM13_IRQHandler            
+   .thumb_set TIM8_UP_TIM13_IRQHandler,Default_Handler
+         
+   .weak      TIM8_TRG_COM_TIM14_IRQHandler      
+   .thumb_set TIM8_TRG_COM_TIM14_IRQHandler,Default_Handler
+      
+   .weak      TIM8_CC_IRQHandler   
+   .thumb_set TIM8_CC_IRQHandler,Default_Handler
+                  
+   .weak      DMA1_Stream7_IRQHandler               
+   .thumb_set DMA1_Stream7_IRQHandler,Default_Handler
+                     
+   .weak      FSMC_IRQHandler            
+   .thumb_set FSMC_IRQHandler,Default_Handler
+                     
+   .weak      SDIO_IRQHandler            
+   .thumb_set SDIO_IRQHandler,Default_Handler
+                     
+   .weak      TIM5_IRQHandler            
+   .thumb_set TIM5_IRQHandler,Default_Handler
+                     
+   .weak      SPI3_IRQHandler            
+   .thumb_set SPI3_IRQHandler,Default_Handler
+                     
+   .weak      UART4_IRQHandler         
+   .thumb_set UART4_IRQHandler,Default_Handler
+                  
+   .weak      UART5_IRQHandler         
+   .thumb_set UART5_IRQHandler,Default_Handler
+                  
+   .weak      TIM6_DAC_IRQHandler                  
+   .thumb_set TIM6_DAC_IRQHandler,Default_Handler
+               
+   .weak      TIM7_IRQHandler            
+   .thumb_set TIM7_IRQHandler,Default_Handler
+         
+   .weak      DMA2_Stream0_IRQHandler               
+   .thumb_set DMA2_Stream0_IRQHandler,Default_Handler
+               
+   .weak      DMA2_Stream1_IRQHandler               
+   .thumb_set DMA2_Stream1_IRQHandler,Default_Handler
+                  
+   .weak      DMA2_Stream2_IRQHandler               
+   .thumb_set DMA2_Stream2_IRQHandler,Default_Handler
+            
+   .weak      DMA2_Stream3_IRQHandler               
+   .thumb_set DMA2_Stream3_IRQHandler,Default_Handler
+            
+   .weak      DMA2_Stream4_IRQHandler               
+   .thumb_set DMA2_Stream4_IRQHandler,Default_Handler
+            
+   .weak      CAN2_TX_IRQHandler   
+   .thumb_set CAN2_TX_IRQHandler,Default_Handler
+                           
+   .weak      CAN2_RX0_IRQHandler                  
+   .thumb_set CAN2_RX0_IRQHandler,Default_Handler
+                           
+   .weak      CAN2_RX1_IRQHandler                  
+   .thumb_set CAN2_RX1_IRQHandler,Default_Handler
+                           
+   .weak      CAN2_SCE_IRQHandler                  
+   .thumb_set CAN2_SCE_IRQHandler,Default_Handler
+                           
+   .weak      OTG_FS_IRQHandler      
+   .thumb_set OTG_FS_IRQHandler,Default_Handler
+                     
+   .weak      DMA2_Stream5_IRQHandler               
+   .thumb_set DMA2_Stream5_IRQHandler,Default_Handler
+                  
+   .weak      DMA2_Stream6_IRQHandler               
+   .thumb_set DMA2_Stream6_IRQHandler,Default_Handler
+                  
+   .weak      DMA2_Stream7_IRQHandler               
+   .thumb_set DMA2_Stream7_IRQHandler,Default_Handler
+                  
+   .weak      USART6_IRQHandler      
+   .thumb_set USART6_IRQHandler,Default_Handler
+                        
+   .weak      I2C3_EV_IRQHandler   
+   .thumb_set I2C3_EV_IRQHandler,Default_Handler
+                        
+   .weak      I2C3_ER_IRQHandler   
+   .thumb_set I2C3_ER_IRQHandler,Default_Handler
+                        
+   .weak      OTG_HS_EP1_OUT_IRQHandler         
+   .thumb_set OTG_HS_EP1_OUT_IRQHandler,Default_Handler
+               
+   .weak      OTG_HS_EP1_IN_IRQHandler            
+   .thumb_set OTG_HS_EP1_IN_IRQHandler,Default_Handler
+               
+   .weak      OTG_HS_WKUP_IRQHandler         
+   .thumb_set OTG_HS_WKUP_IRQHandler,Default_Handler
+            
+   .weak      OTG_HS_IRQHandler      
+   .thumb_set OTG_HS_IRQHandler,Default_Handler
+                                                     
+   .weak      HASH_RNG_IRQHandler                  
+   .thumb_set HASH_RNG_IRQHandler,Default_Handler   
+
+   .weak      FPU_IRQHandler                  
+   .thumb_set FPU_IRQHandler,Default_Handler  

Core/can_tp/CRC32.c

@@ -0,0 +1,57 @@
+#include "CRC32.h"
+
+unsigned int crc32val = 0xFFFFFFFF;
+
+//G(x) =x32 + x26 + x23 + x22 + x16 + x12 + x11 + x10 + x8 + x7 + x5 + x4 + x2 + x + 1
+static const unsigned  int crc32_tab[256] = {
+   0x00000000,0x77073096,0xEE0E612C,0x990951BA,0x076DC419,0x706AF48F,0xE963A535,
+   0x9E6495A3,0x0EDB8832,0x79DCB8A4,0xE0D5E91E,0x97D2D988,0x09B64C2B,0x7EB17CBD,
+   0xE7B82D07,0x90BF1D91,0x1DB71064,0x6AB020F2,0xF3B97148,0x84BE41DE,0x1ADAD47D,
+   0x6DDDE4EB,0xF4D4B551,0x83D385C7,0x136C9856,0x646BA8C0,0xFD62F97A,0x8A65C9EC,
+   0x14015C4F,0x63066CD9,0xFA0F3D63,0x8D080DF5,0x3B6E20C8,0x4C69105E,0xD56041E4,
+   0xA2677172,0x3C03E4D1,0x4B04D447,0xD20D85FD,0xA50AB56B,0x35B5A8FA,0x42B2986C,
+   0xDBBBC9D6,0xACBCF940,0x32D86CE3,0x45DF5C75,0xDCD60DCF,0xABD13D59,0x26D930AC,
+   0x51DE003A,0xC8D75180,0xBFD06116,0x21B4F4B5,0x56B3C423,0xCFBA9599,0xB8BDA50F,
+   0x2802B89E,0x5F058808,0xC60CD9B2,0xB10BE924,0x2F6F7C87,0x58684C11,0xC1611DAB,
+   0xB6662D3D,0x76DC4190,0x01DB7106,0x98D220BC,0xEFD5102A,0x71B18589,0x06B6B51F,
+   0x9FBFE4A5,0xE8B8D433,0x7807C9A2,0x0F00F934,0x9609A88E,0xE10E9818,0x7F6A0DBB,
+   0x086D3D2D,0x91646C97,0xE6635C01,0x6B6B51F4,0x1C6C6162,0x856530D8,0xF262004E,
+   0x6C0695ED,0x1B01A57B,0x8208F4C1,0xF50FC457,0x65B0D9C6,0x12B7E950,0x8BBEB8EA,
+   0xFCB9887C,0x62DD1DDF,0x15DA2D49,0x8CD37CF3,0xFBD44C65,0x4DB26158,0x3AB551CE,
+   0xA3BC0074,0xD4BB30E2,0x4ADFA541,0x3DD895D7,0xA4D1C46D,0xD3D6F4FB,0x4369E96A,
+   0x346ED9FC,0xAD678846,0xDA60B8D0,0x44042D73,0x33031DE5,0xAA0A4C5F,0xDD0D7CC9,
+   0x5005713C,0x270241AA,0xBE0B1010,0xC90C2086,0x5768B525,0x206F85B3,0xB966D409,
+   0xCE61E49F,0x5EDEF90E,0x29D9C998,0xB0D09822,0xC7D7A8B4,0x59B33D17,0x2EB40D81,
+   0xB7BD5C3B,0xC0BA6CAD,0xEDB88320,0x9ABFB3B6,0x03B6E20C,0x74B1D29A,0xEAD54739,
+   0x9DD277AF,0x04DB2615,0x73DC1683,0xE3630B12,0x94643B84,0x0D6D6A3E,0x7A6A5AA8,
+   0xE40ECF0B,0x9309FF9D,0x0A00AE27,0x7D079EB1,0xF00F9344,0x8708A3D2,0x1E01F268,
+   0x6906C2FE,0xF762575D,0x806567CB,0x196C3671,0x6E6B06E7,0xFED41B76,0x89D32BE0,
+   0x10DA7A5A,0x67DD4ACC,0xF9B9DF6F,0x8EBEEFF9,0x17B7BE43,0x60B08ED5,0xD6D6A3E8,
+   0xA1D1937E,0x38D8C2C4,0x4FDFF252,0xD1BB67F1,0xA6BC5767,0x3FB506DD,0x48B2364B,
+   0xD80D2BDA,0xAF0A1B4C,0x36034AF6,0x41047A60,0xDF60EFC3,0xA867DF55,0x316E8EEF,
+   0x4669BE79,0xCB61B38C,0xBC66831A,0x256FD2A0,0x5268E236,0xCC0C7795,0xBB0B4703,
+   0x220216B9,0x5505262F,0xC5BA3BBE,0xB2BD0B28,0x2BB45A92,0x5CB36A04,0xC2D7FFA7,
+   0xB5D0CF31,0x2CD99E8B,0x5BDEAE1D,0x9B64C2B0,0xEC63F226,0x756AA39C,0x026D930A,
+   0x9C0906A9,0xEB0E363F,0x72076785,0x05005713,0x95BF4A82,0xE2B87A14,0x7BB12BAE,
+   0x0CB61B38,0x92D28E9B,0xE5D5BE0D,0x7CDCEFB7,0x0BDBDF21,0x86D3D2D4,0xF1D4E242,
+   0x68DDB3F8,0x1FDA836E,0x81BE16CD,0xF6B9265B,0x6FB077E1,0x18B74777,0x88085AE6,
+   0xFF0F6A70,0x66063BCA,0x11010B5C,0x8F659EFF,0xF862AE69,0x616BFFD3,0x166CCF45,
+   0xA00AE278,0xD70DD2EE,0x4E048354,0x3903B3C2,0xA7672661,0xD06016F7,0x4969474D,
+   0x3E6E77DB,0xAED16A4A,0xD9D65ADC,0x40DF0B66,0x37D83BF0,0xA9BCAE53,0xDEBB9EC5,
+   0x47B2CF7F,0x30B5FFE9,0xBDBDF21C,0xCABAC28A,0x53B39330,0x24B4A3A6,0xBAD03605,
+   0xCDD70693,0x54DE5729,0x23D967BF,0xB3667A2E,0xC4614AB8,0x5D681B02,0x2A6F2B94,
+   0xB40BBE37,0xC30C8EA1,0x5A05DF1B,0x2D02EF8D
+  };
+
+unsigned int crc32(unsigned int crc32val, unsigned char *s, unsigned int len)
+{
+	unsigned i;
+
+    for (i = 0; i < len; i++)
+    {
+        crc32val = crc32_tab[(crc32val ^ s[i]) & 0xff] ^ (crc32val >> 8);
+    }
+
+    return crc32val;
+}
+

Core/can_tp/CRC32.h

@@ -0,0 +1,7 @@
+#ifndef CRC32_H_
+#define CRC32_H_
+
+extern unsigned int crc32val;
+unsigned int crc32(unsigned int crc32val, unsigned char *s,unsigned int len);
+
+#endif /* CRC32_H_ */

Core/can_tp/MCU_CAN.c

@@ -0,0 +1,145 @@
+#include "MCU_CAN.h"
+#include "i15765.h"
+
+/* receive and transmit buffer sizes */
+#define CAN_BUF_RX_SIZE       10
+#define CAN_BUF_TX_SIZE        8
+
+/* total number of channels */
+#define CAN_PORTS              2
+
+/* used for FIFO buffers */
+can_t can_buf_rx[ CAN_PORTS ][ CAN_BUF_RX_SIZE ];
+can_t can_buf_tx[ CAN_PORTS ][ CAN_BUF_TX_SIZE ];
+
+uint8_t volatile can_buf_rx_head[ CAN_PORTS ];
+uint8_t volatile can_buf_rx_cnt[ CAN_PORTS ];
+uint8_t volatile can_buf_tx_tail[ CAN_PORTS ];
+uint8_t volatile can_buf_tx_cnt[ CAN_PORTS ];
+
+uint8_t can_buf_rx_tail[ CAN_PORTS ];
+uint8_t can_buf_tx_head[ CAN_PORTS ];
+uint8_t can_tx_is_active[ CAN_PORTS ];
+
+/*
+** Called by application layer to receive a CAN message.
+** RETURN 0: for success
+**        1: for failure
+*/
+uint8_t can_rx(uint8_t p, can_t *frame)
+{
+	uint8_t ret = 1;
+
+	/* since the below global memory is shared with the rx isr, disable isrs */
+//	CAN_LOCK();
+
+	/* if there is something in the buffer, return it */
+	if(can_buf_rx_cnt[p])
+	{
+
+		/* update buffer size */
+		can_buf_rx_cnt[p]--;
+
+		/* copy over the new can frame from current buffer location */
+		*frame = can_buf_rx[p][can_buf_rx_tail[p]];
+
+		/* move on to next index in buffer */
+		if(++can_buf_rx_tail[p] >= CAN_BUF_RX_SIZE)
+			can_buf_rx_tail[p] = 0;
+
+		ret = 0;
+	}
+
+//	CAN_UNLOCK();
+
+	return ret;
+}
+
+/*
+** Internal transmit interrupt.
+*/
+void can_tx_isr_i(uint8_t p)
+{
+
+	/* if there is nothing to transmit, then exit */
+	if(can_buf_tx_cnt[p])
+	{
+
+		/* we will have one less */
+		can_buf_tx_cnt[p]--;
+
+		/* load the mailbox */
+//		can_mbox_write(p, &can_buf_tx[p][can_buf_tx_tail[p]]);
+
+		/* move on to next index in buffer */
+		if(++can_buf_tx_tail[p] >= CAN_BUF_TX_SIZE)
+			can_buf_tx_tail[p] = 0;
+
+	}
+	else
+	{
+
+		/* the buffer is empty, so we're not transmission is no longer active */
+		can_tx_is_active[p] = 0;
+	}
+}
+
+
+/*
+** Internal receive interrupt.
+*/
+
+void can_rx_isr_i(uint8_t p,uint32_t msgId,uint8_t * data, uint8_t len)
+{
+	can_t *frame;
+	can_t tmp_frame;
+
+	/* is there room in the buffer and is it extended? */
+	if(can_buf_rx_cnt[p] < CAN_BUF_RX_SIZE)
+	{
+
+		/* mark we have one more in the buffer */
+		can_buf_rx_cnt[p]++;
+
+		/* get pointer to the next open index */
+		frame = (can_t *)&can_buf_rx[p][ can_buf_rx_head[p] ];
+
+		/* move on to next index in buffer */
+		if(++can_buf_rx_head[p] >= CAN_BUF_RX_SIZE)
+			can_buf_rx_head[p] = 0;
+
+	}
+	else
+	{
+		/* point to empty location because our rx buffer is full (always do a read) */
+		frame = (can_t *)&tmp_frame;
+	}
+
+	//qiaoxu  Get ID �� data lenth  and  data
+	//ID
+	frame->id = msgId;
+
+	/* get dlc */
+	frame->buf_len = len;
+
+	/*
+		*   @return The function will return:
+		*           - 0: When RX message box hasn't received new data
+		*           - 1: When RX data are stored in the data buffer
+		*           - 3: When RX data are stored in the data buffer and a message was lost
+	*/
+	if(frame->buf_len > 0)
+	{
+		frame->buf[0] = data[0];
+		frame->buf[1] = data[1];
+		frame->buf[2] = data[2];
+		frame->buf[3] = data[3];
+
+		frame->buf[4] = data[4];
+		frame->buf[5] = data[5];
+		frame->buf[6] = data[6];
+		frame->buf[7] = data[7];
+	}
+
+}
+

Core/can_tp/MCU_CAN.h

@@ -0,0 +1,20 @@
+#ifndef MCU_CAN_H_
+#define MCU_CAN_H_
+
+#include <stdint.h>
+#include "stm32f4xx_board.h"
+
+#define APP_START_ADDRESS 	ADDR_FLASH_SECTOR_3
+#define APP_STOP_ADDRESS	ADDR_FLASH_SECTOR_7
+
+typedef struct
+{
+    uint32_t id;
+    uint8_t  buf[8];
+    uint8_t  buf_len;
+} can_t;
+
+extern  void    can_tx_isr_i(uint8_t p);
+extern  void    can_rx_isr_i(uint8_t p, uint32_t msgId, uint8_t * data, uint8_t len);
+
+#endif /* MCU_CAN_H_ */

Core/can_tp/UDS.h

@@ -0,0 +1,15 @@
+#ifndef INCLUDE_UDS_H_
+#define INCLUDE_UDS_H_
+
+#include "i15765.h"
+#include "i15765sid_function.h"
+#include "i15765app.h"
+#include "MCU_CAN.h"
+#include "bits.h"
+#include "CRC32.h"
+#include "flash.h"
+
+#define WAIT_OTA_TIME_MS  1500
+//#define WAIT_OTA_TIME_MS  10
+
+#endif

Core/can_tp/bits.h

@@ -0,0 +1,33 @@
+/* bit definitions */
+#define B0  (0x000000001)
+#define B1  (0x000000002)
+#define B2  (0x000000004)
+#define B3  (0x000000008)
+#define B4  (0x000000010)
+#define B5  (0x000000020)
+#define B6  (0x000000040)
+#define B7  (0x000000080)
+#define B8  (0x000000100)
+#define B9  (0x000000200)
+#define B10 (0x000000400)
+#define B11 (0x000000800)
+#define B12 (0x000001000)
+#define B13 (0x000002000)
+#define B14 (0x000004000)
+#define B15 (0x000008000)
+#define B16 (0x000010000)
+#define B17 (0x000020000)
+#define B18 (0x000040000)
+#define B19 (0x000080000)
+#define B20 (0x000100000)
+#define B21 (0x000200000)
+#define B22 (0x000400000)
+#define B23 (0x000800000)
+#define B24 (0x001000000)
+#define B25 (0x002000000)
+#define B26 (0x004000000)
+#define B27 (0x008000000)
+#define B28 (0x010000000)
+#define B29 (0x020000000)
+#define B30 (0x040000000)
+#define B31 (0x080000000)

Core/can_tp/hal_stdtypes.h

@@ -0,0 +1,152 @@
+#ifndef __HAL_STDTYPES_H__
+#define __HAL_STDTYPES_H__
+
+#include <stdint.h>
+#include <stdbool.h>
+
+/* USER CODE BEGIN (0) */
+/* USER CODE END */
+/************************************************************/
+/* Type Definitions                                         */
+/************************************************************/
+#ifndef _UINT64_DECLARED
+typedef uint64_t uint64;
+#define _UINT64_DECLARED
+#endif
+
+#ifndef _UINT32_DECLARED
+typedef uint32_t uint32;
+#define _UINT32_DECLARED
+#endif
+
+#ifndef _UINT16_DECLARED
+typedef uint16_t uint16;
+#define _UINT16_DECLARED
+#endif
+
+#ifndef _UINT8_DECLARED
+typedef uint8_t uint8;
+#define _UINT8_DECLARED
+#endif
+
+#ifndef _BOOLEAN_DECLARED
+#ifdef __cplusplus
+typedef bool boolean;
+#else
+typedef _Bool boolean;
+#endif
+#define _BOOLEAN_DECLARED
+#endif
+
+#ifndef _SINT64_DECLARED
+typedef int64_t sint64;
+#define _SINT64_DECLARED
+#endif
+
+#ifndef _SINT32_DECLARED
+typedef int32_t sint32;
+#define _SINT32_DECLARED
+#endif
+
+#ifndef _SINT16_DECLARED
+typedef int16_t sint16;
+#define _SINT16_DECLARED
+#endif
+
+#ifndef _SINT8_DECLARED
+typedef int8_t sint8;
+#define _SINT8_DECLARED
+#endif
+
+#ifndef _FLOAT32_DECLARED
+typedef float float32;
+#define _FLOAT32_DECLARED
+#endif
+
+#ifndef _FLOAT64_DECLARED
+typedef double float64;
+#define _FLOAT64_DECLARED
+#endif
+
+
+typedef uint8 Std_ReturnType;
+
+typedef struct
+{
+    uint16 vendorID;
+    uint16 moduleID;
+    uint8  instanceID;
+    uint8  sw_major_version;
+    uint8  sw_minor_version;
+    uint8  sw_patch_version;
+} Std_VersionInfoType;
+
+/*****************************************************************************/
+/* SYMBOL DEFINITIONS                                                        */
+/*****************************************************************************/
+#ifndef STATUSTYPEDEFINED
+#define STATUSTYPEDEFINED
+#define E_OK     0x00U
+
+typedef unsigned char StatusType;
+#endif
+
+#ifndef E_NOT_OK
+#define E_NOT_OK   0x01U
+#endif
+
+#ifndef STD_ON
+#define STD_ON     0x01U
+#endif
+
+#ifndef STD_OFF
+#define STD_OFF    0x00U
+#endif
+
+
+/************************************************************/
+/* Global Definitions                                       */
+/************************************************************/
+/** @def NULL
+*   @brief NULL definition
+*/
+
+//#ifndef NULL
+///*SAFETYMCUSW 218 S MR:20.2 <APPROVED> "Custom Type Definition." */
+//#define NULL ((void *) 0U)
+//#endif
+
+/*****************************************************************************/
+/* Define:       NULL_PTR                                                    */
+/* Description:  Void pointer to 0                                           */
+/*****************************************************************************/
+#ifndef NULL_PTR
+#define NULL_PTR ((void *)0x0)
+#endif
+
+/** @def TRUE
+*   @brief definition for TRUE
+*/
+#ifndef TRUE
+#define TRUE true
+#endif
+
+/** @def FALSE
+*   @brief BOOLEAN definition for FALSE
+*/
+#ifndef FALSE
+#define FALSE false
+#endif
+
+/*****************************************************************************/
+/* Define:       NULL_PTR                                                    */
+/* Description:  Void pointer to 0                                           */
+/*****************************************************************************/
+#ifndef NULL_PTR
+#define NULL_PTR ((void *)0x0U)
+#endif
+
+/* USER CODE BEGIN (1) */
+/* USER CODE END */
+
+#endif /* __HAL_STDTYPES_H__ */

Core/can_tp/i15765.c

@@ -0,0 +1,969 @@
+#include "MCU_CAN.h"
+#include "i15765.h"
+#include "bits.h"
+
+/* FC types */	//Flow Control
+#define I15765_FS_CTS    0
+#define I15765_FS_WT     1
+#define I15765_FS_OVFLW  2
+/* PDU types */
+#define I15765_PDU_SF    0		//Single Frame
+#define I15765_PDU_FF    1		//First Frame
+#define I15765_PDU_CF    2		//Consecutive Frame
+#define I15765_PDU_FC    3		//Flow Control  N_PCI
+
+/* source address */
+#define I15765CFG_SA                           0xf1
+
+/* multi-frame TX buffer size */
+#define I15765CFG_MF_TX_BUF_NUM                  1
+#define I15765CFG_MF_TX_BUF_SIZE               1024
+
+/* multi-frame RX buffer size */
+#define I15765CFG_MF_RX_BUF_NUM                  1
+#define I15765CFG_MF_RX_BUF_SIZE               2048
+
+extern uint8_t can_rx(uint8_t p, can_t *frame);
+
+extern void CAN_SendData(uint8_t canCom, uint32_t mailbox, uint32_t messageId, uint8_t * data, uint32_t len);
+
+extern void i15765app_process(i15765_t *msg);
+
+/* misc */
+#define MIN(X, Y)       ((X) < (Y) ? (X) : (Y))
+#define ADDR_FUNC(tat)  (tat == I15765_TAT_NF11 || tat == I15765_TAT_NF29)
+
+
+enum
+{
+    STATE_IDLE = 0,
+    STATE_TX_FF,
+    STATE_TX_FC,
+    STATE_TX_CF,
+    STATE_WT_FC,
+    STATE_WT_CF,
+    STATE_TX_CTS,
+    STATE_TX_OVFLW
+};
+
+
+/* multiframe rx type */
+typedef struct
+{
+	uint8_t sn;		//Sequence Number
+	i15765_t msg;
+	uint8_t state;
+	uint16_t timeout;
+	uint8_t buf[I15765CFG_MF_RX_BUF_SIZE];
+
+} i15765_mfr_t;
+
+
+/* multiframe tx type */
+typedef struct
+{
+	uint8_t bs;
+	uint8_t bs_cnt;
+	uint16_t st;
+	uint16_t st_cnt;
+	uint8_t sn;
+	uint8_t wt_cnt;
+	i15765_t msg;
+	uint8_t state;
+	uint8_t *status;
+	uint16_t timeout;
+	uint8_t buf[I15765CFG_MF_TX_BUF_SIZE];
+
+} i15765_mft_t;
+
+
+/* multiframe buffers */
+i15765_mfr_t i15765_mfrb[I15765CFG_MF_RX_BUF_NUM];
+i15765_mft_t i15765_mftb[I15765CFG_MF_TX_BUF_NUM];
+
+/* used instead of NULL pointers */
+uint8_t i15765_tmp;
+
+/* source address */
+uint8_t i15765_sa = I15765CFG_SA;
+
+
+
+
+/*
+** Compare address information of two messages.
+**
+** INPUT: msg1 - Pointer to first message
+**        msg2 - Pointer to second message
+**
+** RETURN: 1: if the ai's match
+**         0: otherwise
+*/
+uint8_t i15765_ai_cmp(i15765_t *msg1, i15765_t *msg2)
+{
+	if((msg1->sa != msg2->sa)
+	        || (msg1->ta != msg2->ta)
+	        || (msg1->tat != msg2->tat))
+		return 0;
+
+	return 1;
+}
+/*
+** Initialize the receive and transmit buffers.
+*/
+void i15765_init(void)
+{
+
+	uint8_t i;
+
+	/* clear the rx buffers */
+	for(i = 0; i < I15765CFG_MF_RX_BUF_NUM; i++)
+		i15765_mfrb[i].state = STATE_IDLE;
+
+	/* clear the tx buffers */
+	for(i = 0; i < I15765CFG_MF_TX_BUF_NUM; i++)
+	{
+
+		i15765_mftb[i].state = STATE_IDLE;
+		i15765_mftb[i].status = 0;//&i15765_tmp;
+	}
+
+//	i15765app_init();
+}
+
+
+
+/*
+** Sets the pointer to the first available index.
+**
+** INPUT: mfrb - pointer to available index
+**
+** RETURN: 0: success, index found
+**         1: failure, buf is full
+*/
+uint8_t i15765_mfrb_get(i15765_mfr_t **mfrb)
+{
+
+	uint8_t i;
+
+	/* find first available index */
+	for(i = 0; i < I15765CFG_MF_RX_BUF_NUM; i++)
+	{
+
+		if(i15765_mfrb[i].state == STATE_IDLE)
+		{
+
+			*mfrb = &i15765_mfrb[i];
+			return 0;
+		}
+	}
+
+	return 1;
+}
+
+/*
+** Sets the pointer to the first available index.
+**
+** INPUT: mftb - pointer to available index
+**
+** RETURN: 0: success, index found
+**         1: failure, buf is full
+*/
+uint8_t i15765_mftb_get(i15765_mft_t **mftb)
+{
+
+	uint8_t i;
+
+	/* find first available index */
+	for(i = 0; i < I15765CFG_MF_TX_BUF_NUM; i++)
+	{
+
+		if(i15765_mftb[i].state == STATE_IDLE)
+		{
+
+			*mftb = &i15765_mftb[i];
+			return 0;
+		}
+	}
+
+	return 1;
+}
+
+
+
+/*
+** Delete all receive mf buffers with matching AE info
+*/
+void i15765_mfrb_del(i15765_t *msg)
+{
+	uint8_t i;
+
+	for(i = 0; i < I15765CFG_MF_RX_BUF_NUM; i++)
+	{
+		if(i15765_ai_cmp(&i15765_mfrb[i].msg, msg))
+		{
+			i15765_mfrb[i].state = STATE_IDLE;
+		}
+	}
+	return;
+}
+
+
+
+/*
+** Delete all transmit mf buffers with matching AE info
+*/
+void i15765_mftb_del(i15765_t *msg)
+{
+
+	uint8_t i;
+
+	for(i = 0; i < I15765CFG_MF_TX_BUF_NUM; i++)
+	{
+
+		if(i15765_ai_cmp(&i15765_mftb[i].msg, msg)
+		        && (i15765_mftb[i].state != STATE_IDLE))
+		{
+
+			i15765_mftb[i].state = STATE_IDLE;
+			*i15765_mftb[i].status = I15765_FAILED;
+			i15765_mftb[i].status = &i15765_tmp;
+		}
+	}
+
+	return;
+}
+
+
+
+/*
+** Sets the ptr to point to the first index in buf whose
+** address information matches the current message.
+**
+** INPUT: msg - the address information to match
+**        ptr - double pointer to matching index
+**
+** RETURN: 0 - match found
+**         1 - no match
+*/
+uint8_t i15765_mftb_seek(i15765_t *msg, i15765_mft_t **ptr)
+{
+
+	uint8_t i;
+
+	for(i = 0; i < I15765CFG_MF_TX_BUF_NUM; i++)
+	{
+
+		if(i15765_mftb[i].state != STATE_IDLE)
+		{
+			*ptr = &i15765_mftb[i];
+			return 0;
+		}
+	}
+
+	return 1;
+}
+/*
+** Sets the ptr to point to the first index in buf whose
+** address information matches the current message.
+**
+** INPUT: msg - the address information to match
+**        ptr - double pointer to matching index
+**
+** RETURN: 0 - match found
+**         1 - no match
+*/
+uint8_t i15765_mfrb_seek(i15765_t *msg, i15765_mfr_t **ptr)
+{
+
+	uint8_t i;
+
+	for(i = 0; i < I15765CFG_MF_RX_BUF_NUM; i++)
+	{
+		if(i15765_mfrb[i].state != STATE_IDLE)
+		{
+			*ptr = &i15765_mfrb[i];
+			return 0;
+		}
+	}
+
+	return 1;
+}
+/*
+** Convert an i15765 message to a CAN frame and transmit it
+**
+** INPUT:  msg - the message to transmit
+**
+** RETURN: 0 - success
+**         1 - failure
+**
+*/
+uint8_t i15765_tx(i15765_t *msg)
+{
+
+	can_t can;
+	uint8_t i = 0;
+
+	// 11bit  ��׼֡  ֱ�Ӹ�ֵID��
+	/* physical response */
+	can.id = UDS_TX_ID;
+//	can.id = msg->ID;
+	/* pack the data, garbage will be packed when we overflow so it is the
+	   receiver's responsibility to only read as much as was valid */
+	for(i = 0; i < 8; i++)
+		can.buf[i] = (i < msg->buf_len) ? msg->buf[i] : BUFFER_DATA_LAST;
+
+	/* fix all packets to 8 bytes per 15765-4 */
+	can.buf_len = 8;
+
+	/* Send message */
+//	return can_tx(0, &can);
+
+	CAN_SendData(UDS_CAN_COM, UDS_TX_MAILBOX, can.id, can.buf, can.buf_len);
+
+	return 0;
+}
+
+/*
+** Initialize and attempt transmission of a single frame message.
+** INPUT:  frame - pointer to the i15765 frame to be transmitted
+** RETURN: 0 - success
+**         1 - failure
+*/
+uint8_t i15765_tx_sf(i15765_t *msg)
+{
+
+	uint8_t i;
+	uint8_t cnt;
+	i15765_t sf;
+	uint8_t buf[8];
+
+	/* copy over the old message */
+	sf = *msg;
+
+	/* start writing at the beginning */
+	i = 0;
+
+	/* construct SF N_PDU and pack it into a CAN frame */
+	buf[i++] = (I15765_PDU_SF << 4) | (uint8_t)msg->buf_len;
+
+	for(cnt = 0; cnt < msg->buf_len; cnt++)
+		buf[i++] = msg->buf[cnt];
+
+	sf.buf = buf;
+	sf.buf_len = i;
+
+	/* attempt to buffer the CAN frame */
+	return i15765_tx(&sf);
+}
+
+
+
+/*
+** Transmit a first frame.
+** INPUT: frame - pointer to the i15765 multiframe buffer
+*/
+void i15765_tx_ff(i15765_mft_t *mftb)
+{
+
+	uint8_t i = 0;
+	uint8_t *ptr;
+	uint8_t buf[8];
+	i15765_t frame;
+
+	/* copy over message */
+	frame = mftb->msg;
+	frame.buf = buf;
+	ptr = mftb->buf;
+
+	/* construct FF N_PDU and pack it into a CAN frame */
+	frame.buf[i++] = (I15765_PDU_FF << 4) | (mftb->msg.buf_len >> 8);
+	frame.buf[i++] = (uint8_t)mftb->msg.buf_len;
+
+	/* copy over the data */
+	while(i < 8)
+		frame.buf[i++] = *ptr++;
+
+	/* FF's are always 8 bytes long */
+	frame.buf_len = 8;
+
+	/* transmit the CAN frame, testing to see if it was sent correctly */
+	if(i15765_tx(&frame) == 0)
+	{
+
+		mftb->state = STATE_WT_FC;
+		mftb->timeout = TIMEOUT_FC_S;
+		mftb->msg.buf = ptr;
+	}
+
+	return;
+}
+
+
+
+/*
+** Transmit a consecutive frame.
+** INPUT: mftb - pointer to the i15765 multiframe buffer
+*/
+void i15765_tx_cf(i15765_mft_t *mftb)
+{
+
+	uint8_t min;
+	uint8_t i = 0;
+	uint8_t *ptr;
+	uint16_t rem;
+	uint8_t buf[8];
+	i15765_t frame;
+
+	/* copy over message */
+	frame = mftb->msg;
+	frame.buf = buf;
+	ptr = mftb->msg.buf;
+
+	/* update separation time */
+	if(mftb->st_cnt)
+	{
+
+		/* delay */
+		mftb->st_cnt--;
+		return;
+
+	}
+	else
+	{
+
+		/* transmit */
+		mftb->st_cnt = mftb->st;
+	}
+
+	/* load PDU type */
+	frame.buf[i++] = (I15765_PDU_CF << 4) | (mftb->sn++ & 0xf);
+
+	/* how much data can we (or need we) copy over? */
+	rem = mftb->msg.buf_len - (mftb->msg.buf - mftb->buf);
+	min = (uint8_t)MIN(rem, 8 - i);
+
+	/* add in the PDU field (and maybe AE) */
+	min += i;
+
+	/* copy  over the data */
+	while(i < min)
+		frame.buf[i++] = *ptr++;
+
+	/* FF's are always 8 bytes long */
+	frame.buf_len = min;
+
+	/* transmit the CAN frame, testing to see if it was sent correctly */
+	if(i15765_tx(&frame) == 0)
+	{
+
+		mftb->timeout = TIMEOUT_CF_S;
+		mftb->msg.buf = ptr;
+
+		/* if bs is zero, then transmit away, else check how many we have left */
+		mftb->bs_cnt--;
+		if(mftb->bs && (mftb->bs_cnt == 0))
+		{
+			//			mftb->state = STATE_WT_FC;//qiaoxu  Ϊ���ó����ķ��ʹ���8֡
+		}
+	}
+
+	rem = mftb->msg.buf_len - (mftb->msg.buf - mftb->buf);
+	if(rem == 0)
+	{
+
+		*mftb->status = I15765_SENT;
+		mftb->status = &i15765_tmp;
+		mftb->state = STATE_IDLE;
+	}
+
+	return;
+}
+
+
+
+/*
+** Initialize and attempt transmit a multi-frame message.
+** INPUT:  msg - pointer to the i15765 message to be transmitted
+**         status - pointer to user RAM location for status feedback
+**
+*/
+void i15765_tx_mf(i15765_t *msg, uint8_t *status)
+{
+
+	uint16_t i;
+	i15765_mft_t *mftb;
+
+	/* delete any mf buffers with matching address information */
+//	i15765_mftb_del(msg);
+
+	/* assume failure */
+	*status = I15765_FAILED;
+
+	/* find an available spot for this message */
+	if(i15765_mftb_get(&mftb))
+		return;
+
+	/* there was room, so update status */
+	*status = I15765_SENDING;
+
+	/* copy over the data */
+	for(i = 0; i < msg->buf_len; i++)
+		mftb->buf[i] = msg->buf[i];
+
+	/* copy over message */
+	mftb->msg = *msg;
+	mftb->msg.buf = mftb->buf;
+
+	/* set state to wait for a flow control PDU */
+	mftb->state = STATE_TX_FF;
+	mftb->sn = 1;
+
+	mftb->status = status;
+
+	/* transmit the CAN frame, testing to see if it was sent correctly */
+	mftb->timeout = TIMEOUT_TX_S;
+	i15765_tx_ff(mftb);
+}
+
+
+
+/*
+** Transmit a flow control frame and updates the status of mfrb. Reception
+** will be paused until the FC has been transmitted.
+** INPUT: mfrb - pointer multiframe receive buffer
+*/
+void i15765_tx_fc(i15765_mfr_t *mfrb)
+{
+
+	uint8_t fs;
+	i15765_t msg;
+	uint8_t buf[8];
+
+	/* get the FF_DL and check for potential buffer overflow */
+	if(mfrb->msg.buf_len > I15765CFG_MF_RX_BUF_SIZE)
+	{
+
+		fs = I15765_FS_OVFLW;
+		mfrb->state = STATE_TX_OVFLW;
+
+	}
+	else
+	{
+
+		fs = I15765_FS_CTS;		//
+//		fs = I15765_FS_WT;		//wait
+		mfrb->state = STATE_TX_CTS;
+	}
+
+	/* pack the pci */
+	msg.buf = buf;
+	msg.buf[0] = (I15765_PDU_FC << 4) | fs;
+	msg.buf[1] = BS;	//qiaoxu modify
+	msg.buf[2] = STmin; //qiaoxu modify
+	msg.buf_len = 3;
+
+	msg.sa = i15765_sa;
+	msg.ta = mfrb->msg.sa;
+	msg.tat = mfrb->msg.tat;
+
+	/* set pri same as received FF */
+	msg.pri = mfrb->msg.pri;
+
+	/* send the message */
+	if(i15765_tx(&msg) == 0)
+	{
+		/* transmission successful */
+		mfrb->timeout = TIMEOUT_CF_R;
+		mfrb->state = (mfrb->state == STATE_TX_CTS) ? STATE_WT_CF : STATE_IDLE;
+	}
+}
+
+/*
+** Handles a recieved single frame
+** INPUT: msg - pointer to the received message
+*/
+void i15765_rx_sf(i15765_t *msg)
+{
+
+	/* ignore message if errors are present */
+	if((msg->buf[0] == 0) || (msg->buf[0] > (msg->buf_len - 1)))
+	{
+		return;
+	}
+
+	/* message length */
+	msg->buf_len = msg->buf[0];
+
+	/* skip PCI field */
+	msg->buf++;
+
+	i15765app_process(msg);
+}
+
+/*
+** Handles a recieved first frame.
+** INPUT: msg - pointer to the received message segment
+*/
+void i15765_rx_ff(i15765_t *msg)
+{
+
+	uint8_t i;
+	uint16_t ff_dl;
+	i15765_mfr_t *mfrb;
+
+	//qiaoxu   ɾ��
+	/* delete any mf buffers with matching address information */
+	i15765_mfrb_del(msg);
+
+	/* find an available spot for this message */
+	if(i15765_mfrb_get(&mfrb))
+		return;
+
+	/* first frame data length */
+	ff_dl = ((msg->buf[0] & 0xf) << 8) | msg->buf[1];
+
+	/* if the total size could fit in an SF PDU, ignore */
+	if(ff_dl <= 7)
+		return;
+
+	/* skip PCI field */
+	msg->buf += 2;
+	msg->buf_len -= 2;
+
+	/* buffer the necessary info */
+	mfrb->sn = 0;
+	mfrb->msg = *msg;
+	mfrb->msg.buf_len = ff_dl;
+
+	/* reset buf pointer and store data that was recieved with the FF */
+	mfrb->msg.buf = mfrb->buf;
+	for(i = 0; i < msg->buf_len; i++)
+		*mfrb->msg.buf++ = msg->buf[i];
+
+	/* transmit a flow control frame (the status will be updated based on FS) */
+	mfrb->timeout = TIMEOUT_TX_R;
+	i15765_tx_fc(mfrb);
+}
+
+
+
+/*
+** Handles a recieved consecutive frame
+** INPUT: msg - pointer to the received message
+*/
+void i15765_rx_cf(i15765_t *msg)
+{
+	uint8_t i;
+	uint8_t min;
+	uint16_t rem;
+	i15765_mfr_t *mfrb;
+
+	/* find the matching index */	//qiaoxu
+	if(i15765_mfrb_seek(msg, &mfrb))
+		return;
+
+	/* if the CF frame is not expected, ignore it */
+	if(mfrb->state != STATE_WT_CF)
+		return;
+
+	/* increment the sequence number and compare */
+	if((++mfrb->sn & 0xf) == (msg->buf[0] & 0xf))
+	{
+		/* skip PCI field */
+		msg->buf++;
+		msg->buf_len--;
+
+		/* if we are at the end of the message, stop early */
+		rem = (mfrb->buf + mfrb->msg.buf_len) - mfrb->msg.buf;
+
+		min = (uint8_t) MIN(msg->buf_len, rem);
+
+		/* add the data to the buffer */
+		for(i = 0; i < min; i++)
+			*mfrb->msg.buf++ = msg->buf[i];
+
+		rem = (mfrb->buf + mfrb->msg.buf_len) - mfrb->msg.buf;
+
+		/* if we stopped early, the reception is complete */
+		if(rem == 0)
+		{
+
+			mfrb->msg.buf = mfrb->buf;
+			i15765app_process(&mfrb->msg);
+			mfrb->state = STATE_IDLE;
+
+		}
+		else
+		{
+			mfrb->timeout = TIMEOUT_CF_R;
+
+		}
+	}
+	else
+	{
+		/* abort the reception */
+		mfrb->state = STATE_IDLE;
+
+	}
+}
+
+
+/*
+** Handle a recieved flow control frame
+** INPUT: msg - pointer to the received message
+*/
+void i15765_rx_fc(i15765_t *msg)
+{
+
+	i15765_mft_t *mftb;
+
+	/* find matching multiframe transmit buffer */
+	if(i15765_mftb_seek(msg, &mftb))//qiaoxu
+		return;
+
+	/* if the FC frame is not expected, ignore it */
+	if(mftb->state != STATE_WT_FC)
+		return;
+
+	//qiaoxu add
+	if(msg->buf_len<3)
+	{
+		return;
+	}
+	//////////////////////////////////////////////////////////////
+
+	/* determine what type of FC this is and act appropriately */
+	switch(msg->buf[0] & 0xf)
+	{
+
+		/* continue to send */
+	case 0:
+		mftb->state = STATE_TX_CF;
+		mftb->bs = msg->buf[1];
+		mftb->bs_cnt = mftb->bs;
+
+		if(msg->buf[2] <= 0x7f)
+			mftb->st = msg->buf[2];
+		else if((msg->buf[2] >= 0xf1) && (msg->buf[2] <= 0xf9))
+			mftb->st = 0x01;
+		else
+			mftb->st = 0x7f;
+
+		/* convert to units of 100 microseconds (1ms) */
+		mftb->st *= ((uint16_t)1);
+
+		/* convert to ticks */
+		mftb->st /= ((uint8_t)I15765CFG_TICK_PERIOD);
+
+		mftb->st_cnt = mftb->st;
+		mftb->timeout = TIMEOUT_CF_S;
+		mftb->wt_cnt = 0;
+		break;
+
+		/* wait (NOTE - must be above "default" case) */
+	case 1:
+		mftb->state = STATE_WT_FC;
+		mftb->timeout = TIMEOUT_FC_S;
+
+		/* if too many waits, bail */
+		if(++mftb->wt_cnt < 5)
+			break;
+
+		/* all others */
+	default:
+		mftb->state = STATE_IDLE;
+		*mftb->status = I15765_FAILED;
+		mftb->status = &i15765_tmp;
+		break;
+	}
+}
+
+
+
+/*
+** Translates the CAN frame into an i15765 message
+** INPUT: can - pointer to the received CAN frame
+*/
+void i15765_rx_post(can_t *can)
+{
+	i15765_t msg;
+	uint8_t pdu_type;
+
+	if(!(can->id & B31))
+	{
+		msg.buf = &can->buf[0];
+		msg.buf_len = can->buf_len;
+		msg.pri = 0;
+
+		if(can->id == 0x7DF)
+		{
+
+			/* support incoming functional requests */
+			msg.tat = I15765_TAT_NF11;
+			//msg.sa = 0xf1;
+			msg.sa = I15765CFG_SA;
+
+		}
+		else if(can->id == UDS_RX_ID)//
+		{
+			/* support incoming requests (0xf1 is external test equipment) */
+			msg.tat = I15765_TAT_NP11;
+			//msg.sa = 0xf1;
+			msg.sa = I15765CFG_SA;	//
+			msg.ta = (can->id - 0x7e0) + 1;
+		}
+
+	}
+
+	/* SF, FF, CF, or FC? */
+	pdu_type = msg.buf[0] >> 4;
+
+	/* if this message is not for us or not functional, discard it */
+	if((ADDR_FUNC(msg.tat) && pdu_type != I15765_PDU_SF))
+	{
+		return;
+	}
+
+	if(pdu_type <= 3)
+	{
+		switch(pdu_type)
+		{
+		case I15765_PDU_SF:
+			i15765_rx_sf(&msg);
+			break;
+		case I15765_PDU_FF:
+			i15765_rx_ff(&msg);
+			break;
+		case I15765_PDU_CF:
+			i15765_rx_cf(&msg);
+			break;
+		case I15765_PDU_FC:
+			i15765_rx_fc(&msg);
+			break;
+		}
+	}
+}
+
+/*
+** Requests a message to be transmitted, either single or multi-frame
+** INPUT: msg - the message to transmit
+**        status - pointer to user RAM location for status feedback
+*/
+void i15765_tx_app(i15765_t *msg, uint8_t *status)
+{
+
+	/* status always has to point somewhere */
+	if(status == 0)
+		status = &i15765_tmp;
+
+	/* load in source address into out going message */
+	msg->sa = i15765_sa;
+
+	/* if its small enough to send in a SF, pack and transmit */
+	if(msg->buf_len <= 7)
+	{
+
+		*status = (i15765_tx_sf(msg) == 0) ? I15765_SENT : I15765_FAILED;
+
+	}
+	else if(msg->buf_len <= I15765CFG_MF_TX_BUF_SIZE)
+	{
+
+		/* multiframe - only support physical addressing */
+		i15765_tx_mf(msg, status);
+
+	}
+	else
+	{
+
+		/* too big or no available buffers */
+		*status = I15765_FAILED;
+	}
+}
+
+
+
+/*
+** Cycle through our active messages and attempt to continue
+** transmitting.  Also, check for timeouts as we go.
+*/
+void i15765_tx_update(void)
+{
+
+	uint8_t i;
+
+	/* for each currently transmitting message, continue */
+	for(i = 0; i < I15765CFG_MF_TX_BUF_NUM; i++)
+	{
+
+		/* if we are waiting on a transmission to complete, try it again */
+		switch(i15765_mftb[i].state)
+		{
+
+		case STATE_TX_FF:
+			i15765_tx_ff(&i15765_mftb[i]);
+			break;
+		case STATE_TX_CF:
+			i15765_tx_cf(&i15765_mftb[i]);
+			break;
+		}
+
+		/* update timeout */
+		if(i15765_mftb[i].timeout)
+		{
+
+			i15765_mftb[i].timeout--;
+
+		}
+		else
+		{
+
+			i15765_mftb[i].state = STATE_IDLE;
+			*i15765_mftb[i].status = I15765_FAILED;
+			i15765_mftb[i].status = &i15765_tmp;
+//			i15765_mftb[i].status = 0;
+
+		}
+	}
+}
+
+/*
+** Cycle through our active messages and attempt to continue
+** reception checking for timeouts as we go.
+*/
+void i15765_rx_update(void)
+{
+
+	can_t can;
+	uint8_t i;
+
+	/* read all the CAN frames and pass them up */
+	while(can_rx(0, &can) == 0)
+		i15765_rx_post(&can);
+
+	/* for each active message, check for expiration and cancel if needed */
+	for(i = 0; i < I15765CFG_MF_RX_BUF_NUM; i++)
+	{
+
+		/* if we are waiting to send an FC frame, try it again */
+		if((i15765_mfrb[i].state == STATE_TX_CTS)
+		        || (i15765_mfrb[i].state == STATE_TX_OVFLW))
+			i15765_tx_fc(&i15765_mfrb[i]);
+
+		/* update timeout */
+		if(i15765_mfrb[i].timeout)
+			i15765_mfrb[i].timeout--;
+		else
+			i15765_mfrb[i].state = STATE_IDLE;
+	}
+}
+
+/*
+** This function is the time base for the entire i15765 module.
+*/
+void i15765_update(void)
+{
+	i15765_rx_update();
+	i15765_tx_update();
+}

Core/can_tp/i15765.h

@@ -0,0 +1,63 @@
+#ifndef I15765_H
+#define I15765_H
+
+#include <stdint.h>
+
+
+/* status */
+#define I15765_SENT             (0)
+#define I15765_SENDING          (1)
+#define I15765_FAILED           (2)
+
+
+/* target address types */
+#define I15765_TAT_NP11         (118)  // Normal physical 11-bit
+#define I15765_TAT_NF11         (119)  // Normal functional 11-bit
+#define I15765_TAT_NP29         (218)  // Normal physical 29-bit
+#define I15765_TAT_NF29         (219)  // Normal functional 29-bit
+
+
+typedef struct
+{
+    uint8_t sa;         /* source address */
+    uint8_t ta;         /* target address */
+    uint8_t pri;        /* priority of message */
+    uint8_t tat;        /* target address type */
+    uint8_t *buf;       /* pointer to data */
+    uint16_t buf_len;   /* size of data */
+    uint32_t ID;        //qiaoxu
+} i15765_t;
+
+extern const uint16_t TIMEOUT_TX_S;// ((uint16_t)700/I15765CFG_TICK_PERIOD)  /* tx of CAN frm */
+extern const uint16_t TIMEOUT_TX_R;// ((uint16_t)700/I15765CFG_TICK_PERIOD)  /* tx of CAN frm */ ֵ
+extern const uint16_t TIMEOUT_FC_S;//((uint16_t)1500/I15765CFG_TICK_PERIOD) /* rx of FC */
+extern const uint16_t TIMEOUT_FC_R;//((uint16_t)200/I15765CFG_TICK_PERIOD)  /* tx of FC */
+extern const uint16_t TIMEOUT_CF_S;//((uint16_t)250/I15765CFG_TICK_PERIOD)  /* tx of CF */
+extern const uint16_t TIMEOUT_CF_R;//((uint16_t)1500/I15765CFG_TICK_PERIOD) /* rx of CF */
+
+/* update period (1 ms units) */
+extern const uint16_t I15765CFG_TICK_PERIOD;
+
+
+extern const uint8_t UDS_CAN_COM;
+extern const uint32_t UDS_ECU_TX_MAILBOX;
+extern const uint32_t UDS_ECU_RX_MAILBOX;
+
+extern const uint32_t UDS_TX_MAILBOX;
+extern const uint32_t UDS_ECU_RX_MAILBOX;
+extern const uint32_t UDS_RX_MAILBOX_FUNCTION;
+extern const uint32_t UDS_RX_MAILBOX_PHYSICAL;
+
+extern const uint32_t UDS_RX_ID;
+extern const uint32_t UDS_TX_ID;
+extern const uint8_t  BUFFER_DATA_LAST;
+extern const uint8_t  BS;
+extern const uint8_t  STmin;
+//
+extern void i15765_init(void);
+
+extern void i15765_update(void);
+
+extern void i15765_tx_app(i15765_t *msg, uint8_t *status);
+
+#endif

Core/can_tp/i15765app.c

@@ -0,0 +1,262 @@
+
+#include "UDS.h"
+#include <string.h>
+
+uint8_t status_rq;
+
+const uint16_t TIMEOUT_TX_S = 70;// ((uint16_t)700/I15765CFG_TICK_PERIOD)  /* tx of CAN frm */
+const uint16_t TIMEOUT_TX_R = 70;// ((uint16_t)700/I15765CFG_TICK_PERIOD)  /* tx of CAN frm */
+const uint16_t TIMEOUT_FC_S = 150;//((uint16_t)1500/I15765CFG_TICK_PERIOD) /* rx of FC */
+const uint16_t TIMEOUT_FC_R = 20;//((uint16_t)200/I15765CFG_TICK_PERIOD)  /* tx of FC */
+const uint16_t TIMEOUT_CF_S = 70;//((uint16_t)700/I15765CFG_TICK_PERIOD)  /* tx of CF */
+const uint16_t TIMEOUT_CF_R = 150;//((uint16_t)1500/I15765CFG_TICK_PERIOD) /* rx of CF */
+
+
+/* update period (1 ms units) */
+const uint16_t I15765CFG_TICK_PERIOD = 1;   //ms
+
+const uint8_t UDS_CAN_COM = 0;
+
+const uint32_t UDS_TX_MAILBOX = 0;
+
+const uint32_t UDS_ECU_RX_MAILBOX = 13;
+const uint32_t UDS_RX_MAILBOX_FUNCTION = 14;        //UDS
+const uint32_t UDS_RX_MAILBOX_PHYSICAL = 15;        //UDS mailbox 0x7DF
+
+const uint32_t UDS_RX_ID = 0x701;
+const uint32_t UDS_TX_ID = 0x709;
+
+const uint8_t  BUFFER_DATA_LAST = 0x55;
+const uint8_t  BS = 0;//0x08;                   //Block size
+const uint8_t  STmin = 1;//0x14;                //Minimum Separation Time
+
+const uint64_t Error_DTC_All = B0 | B1 | B2 | B3 | B4 | B5 | B6 | B7 | B8 | B9 | B10 | B11 | B12 | B13 | B14 | B15 | B16 | B17 | B18 | B19 | B20 | B21 | B22;
+
+/*
+** Initialization routine.
+*/
+void i15765app_init(void)
+{
+    DiagnosticSessionType = 0x02;
+}
+
+
+
+/*
+** Indicates a message has been received
+** INPUT: msg - pointer to the message
+*/
+#if  0
+void i15765app_process(i15765_t *msg)
+{
+
+    //SID ������ж� data[1]
+    switch (msg->buf[0])
+    {
+        //��ϻỰ����
+        case 0x10:
+        {
+            SID_10_function(msg);
+            break;
+        }
+        //��ص�Ԫ��λ
+        case 0x11:
+        {
+            SID_11_function(msg);
+            break;
+        }
+        //��������Ϣ
+        case 0x14:
+        {
+            SID_14_function(msg);
+            break;
+        }
+        //��ȡ DTC ��Ϣ
+        case 0x19:
+        {
+            SID_19_function(msg);
+            break;
+        }
+        //��ȡ����
+        case 0x22:
+        {
+            SID_22_function(msg);
+            break;
+        }
+        //��ȫ����
+        case 0x27:
+        {
+            SID_27_function(msg);
+            break;
+        }
+        //ͨ�ſ���
+        case 0x28:
+        {
+            SID_28_function(msg);
+            break;
+        }
+        //д������    �谲ȫ����
+        case 0x2E:
+        {
+            SID_2E_function(msg);
+            break;
+        }
+        /*
+        //�����������   �谲ȫ����
+        case 0x2F:
+        {
+            SID_2F_function(msg);
+        }
+        */
+        //���̿���    �谲ȫ����
+        case 0x31:
+        {
+
+            SID_31_function(msg);
+            break;
+        }
+        //��������    �谲ȫ����
+        case 0x34:
+        {
+            SID_34_function(msg);
+            break;
+        }
+        //���ݴ���    �谲ȫ����
+        case 0x36:
+        {
+            SID_36_function(msg);
+            break;
+        }
+        //�����˳�����    �谲ȫ����
+        case 0x37:
+        {
+            SID_37_function(msg);
+            break;
+        }
+        //����豸����    �谲ȫ����
+        case 0x3E:
+        {
+            SID_3E_function(msg);
+            break;
+        }
+        //���� DTC ����
+        case 0x85:
+        {
+            SID_85_function(msg);
+            break;
+        }
+
+        default:
+        {
+            if (msg->tat == I15765_TAT_NP11)
+            {
+                NegativeResponse(msg->buf[0], 0x11); //���ij��ȴ�����߸�ʽ�Ƿ�
+                break;
+            }
+
+        }
+
+    }
+}
+#else
+
+#define MAX_MSG_LENGTH 4096
+
+i15765_t msg_new = {0};
+uint8_t msg_new_buf[MAX_MSG_LENGTH];
+
+uint8_t SID_11_flag = 0;
+uint8_t SID_2E_flag = 0;
+uint8_t SID_31_flag = 0;
+uint8_t SID_34_flag = 0;
+uint8_t SID_36_flag = 0;
+uint8_t SID_37_flag = 0;
+
+void i15765app_process(i15765_t *msg)
+{
+    msg_new.buf_len = msg->buf_len;
+    msg_new.ID = msg->ID;
+
+    // 深拷贝缓冲区
+    memcpy(msg_new_buf, msg->buf, msg->buf_len);
+    msg_new.buf = msg_new_buf;  // 指向我们的缓冲区
+
+    switch (msg->buf[0])
+    {
+        case 0x11:
+        {
+        	SID_11_flag = 1;
+//            SID_11_function(msg);
+            break;
+        }
+        case 0x2E:
+        {
+        	SID_2E_flag = 1;
+//            SID_2E_function(msg);
+            break;
+        }
+        case 0x31:
+        {
+        	SID_31_flag = 1;
+//            SID_31_function(msg);
+            break;
+        }
+        case 0x34:
+        {
+        	SID_34_flag = 1;
+//            SID_34_function(msg);
+            break;
+        }
+        case 0x36:
+        {
+        	SID_36_flag = 1;
+//            SID_36_function(msg);
+            break;
+        }
+        case 0x37:
+        {
+        	SID_37_flag = 1;
+//            SID_37_function(msg);
+            break;
+        }
+        default:
+        {
+            if (msg->tat == I15765_TAT_NP11)
+            {
+                NegativeResponse(msg->buf[0], 0x11);
+                break;
+            }
+        }
+    }
+}
+
+void check_SID_run(void)
+{
+	if(SID_11_flag == 1)
+	{
+		SID_11_flag = 0;
+		SID_11_function(&msg_new);
+	}
+	if(SID_31_flag == 1)
+	{
+		SID_31_flag = 0;
+		SID_31_function(&msg_new);
+	}
+	if(SID_34_flag == 1)
+	{
+		SID_34_flag = 0;
+		SID_34_function(&msg_new);
+	}
+	if(SID_36_flag == 1)
+	{
+		SID_36_flag = 0;
+		SID_36_function(&msg_new);
+	}
+	if(SID_37_flag == 1)
+	{
+		SID_37_flag = 0;
+		SID_37_function(&msg_new);
+	}
+}
+#endif
+

Core/can_tp/i15765app.h

@@ -0,0 +1,17 @@
+#ifndef I15765APP_H
+#define I15765APP_H
+
+#include "hal_stdtypes.h"
+
+#define P2server                        50
+#define P2_server                       500
+#define S3server                        5000
+#define SECURITY_ACCESS_TIME            10000
+
+extern void i15765app_init(void);
+
+extern void i15765app_process(i15765_t *msg);
+
+extern void check_SID_run(void);
+
+#endif

Core/can_tp/i15765sid_function.c

@@ -0,0 +1,651 @@
+#include "UDS.h"
+#include <stdio.h>
+
+//bootloader
+uint8_t DataFormatIdentifier = 0;
+uint8_t addressAndLengthFormatIdentifier = 0;
+
+const uint16_t MaxNumberOfBlockLength = 128;
+
+uint32_t load_MemoryAddress = 0;
+uint32_t load_MemorySize = 0;
+uint32_t load_BlockNum = 0;
+uint32_t load_BlockCount = 0;
+
+uint32_t earse_MemoryAddress = 0;
+uint32_t earse_MemorySize = 0;
+
+uint8_t load_sequence_state = 0;//0=请求升级，1=擦除成功进入数据传输流程，2=请求下载数据，3=正在下载数据，
+uint16_t BlockSequenceCounter = 0;
+uint16_t BlockSequenceCounter_pre = 0;
+
+uint32 CRC32_value = 0;
+uint32 CRC32_value_app2 = 0;
+uint32 WriteFlashAlreadySize = 0;
+
+uint8_t	DiagnosticSessionType = 0x02;
+
+extern uint8_t ota_start_flag;
+
+uint8_t app2_crc_flag = 0;//crc校验成功标志位，成功后应答版本号位新的。
+
+void NegativeResponse(uint8_t sid,uint8_t NegativeResponseCode)
+{
+	i15765_t msg_req;
+	uint8_t buf[8];
+	uint8_t status_rq;
+
+	msg_req.ID = UDS_TX_ID;
+	msg_req.buf = buf;
+
+	buf[0] = 0x7F;//NegativeResponseServiceIdentifier
+	buf[1] = sid;
+	buf[2] = NegativeResponseCode;
+
+	msg_req.buf_len = 3;
+
+	/* transmit message */
+	i15765_tx_app(&msg_req, &status_rq);
+}
+
+void SID_11_function(i15765_t *msg)
+{
+	i15765_t msg_req;
+	uint8_t buf[8];
+	uint8_t status_rq;
+	uint8_t PositiveResponseEnable = 0;
+
+	uint8_t SuppressPosRspMsgIndicationBit;
+	uint8_t ResetType;
+
+	/* basic stuff */
+	msg_req.buf = buf;
+	msg_req.pri = 6;
+	msg_req.ta = 0x0C;
+
+	if(msg->tat == I15765_TAT_NF11)
+	{
+		msg_req.tat = I15765_TAT_NF11;
+	}
+	else
+	{
+		msg_req.tat = I15765_TAT_NP11;
+	}
+
+#if    0
+	if(DiagnosticSessionType==0x02)
+	{
+		NegativeResponse(msg->buf[0],0x7F);
+		return;
+	}
+#endif
+
+	if(DiagnosticSessionType==0x01)
+	{
+		NegativeResponse(msg->buf[0],0x7F);
+		return;
+	}
+
+
+	if(msg->buf_len!=2)
+	{
+		NegativeResponse(msg->buf[0],0x13);
+		return;
+	}
+
+	SuppressPosRspMsgIndicationBit = msg->buf[1]&0x80;
+	ResetType = msg->buf[1]&0x7F;
+
+	switch(ResetType)
+	{
+		case 0x01:
+		{
+			if(1)
+			{
+				PositiveResponseEnable = 1;
+				buf[0] = msg->buf[0]+0x40;// PositiveResponseServiceIdentifier
+				buf[1] = msg->buf[1];// Sub-Function=ResetType
+
+				msg_req.buf_len = 2;
+				if(SuppressPosRspMsgIndicationBit != 0x80)
+				{
+					i15765_tx_app(&msg_req, &status_rq);
+				}
+			}
+			else
+			{
+				PositiveResponseEnable = 0;
+				NegativeResponse(msg->buf[0],0x22);
+				return;
+			}
+
+			break;
+		}
+		case 0x03:
+		{
+
+			if(1)
+			{
+				PositiveResponseEnable = 1;
+				buf[0] = msg->buf[0]+0x40;// PositiveResponseServiceIdentifier
+				buf[1] = msg->buf[1];// Sub-Function=ResetType
+
+				msg_req.buf_len = 2;
+				if(SuppressPosRspMsgIndicationBit != 0x80)
+				{
+					i15765_tx_app(&msg_req, &status_rq);
+				}
+			}
+			else
+			{
+				PositiveResponseEnable = 0;
+				NegativeResponse(msg->buf[0],0x22);
+				return;
+			}
+
+			break;
+		}
+		default:
+		{
+			NegativeResponse(msg->buf[0],0x12);
+			return;
+		}
+	}
+
+
+	if(PositiveResponseEnable==1)
+	{
+		if(ResetType == 0x01)//HardReset
+		{
+			//JumpReset();
+		}
+
+		if(ResetType == 0x03)//SoftReset
+		{
+			//JumpReset();
+		}
+	}
+}
+
+void SID_2E_function(i15765_t *msg)
+{
+	//用于应答
+	i15765_t msg_req;
+	uint8_t buf[8];
+	uint8_t status_rq;
+	uint8_t PositiveResponseEnable = 0;//判断是否为肯定响应  1：肯定响应  0：否定响应
+	uint16_t DID = 0;
+
+	msg_req.buf = buf;
+
+	//2 数据长度错误
+	if(msg->buf_len < 4)
+	{
+		NegativeResponse(msg->buf[0],0x13);
+	}
+
+	//扩展诊断回话 或 编程会话
+	if((DiagnosticSessionType==0x02)||(DiagnosticSessionType==0x03))
+	{
+		DID = (uint16_t)msg->buf[1]<<8 | msg->buf[2];
+
+		//版本信息全读
+		//EEPROM_read(VERSION_ADRESS,256,VersionInfo);
+
+		switch(DID)
+		{
+			//VIN: 17 byte
+			case 0xF190:
+			{
+
+				break;
+			}
+			default:
+			{
+				NegativeResponse(msg->buf[0],0x31);//请求超出范围
+				break;
+			}
+		}
+	}
+
+	if(PositiveResponseEnable==1)
+	{
+//		EEPROM_write(VERSION_ADRESS,256,VersionInfo);
+
+		buf[0] = msg->buf[0]+0x40;	// PositiveResponseServiceIdentifier
+		buf[1] = msg->buf[1];		// DID MSB
+		buf[2] = msg->buf[2];		// DID LSB
+
+		msg_req.buf_len = 3;
+
+		/* transmit message */
+		i15765_tx_app(&msg_req, &status_rq);
+	}
+}
+
+void SID_31_function(i15765_t *msg)
+{
+    i15765_t msg_req = {0};
+    uint8_t response_buf[20] = {0};
+    uint8_t status_rq = 0;
+    uint8_t PositiveResponseEnable = 0;
+	int oReturnCheck;//
+    uint8_t result_code = 0x00;
+    // 初始化请求消息
+	msg_req.pri = 6;
+	msg_req.ta = 0x0C;
+	msg_req.buf = response_buf;
+	if(msg->tat == I15765_TAT_NF11)
+	{
+		msg_req.tat = I15765_TAT_NF11;
+	}
+	else
+	{
+		msg_req.tat = I15765_TAT_NP11;
+	}
+
+
+    // 参数检查
+    if (msg == NULL || msg->buf == NULL || msg->buf_len < 4)
+    {
+        NegativeResponse(0x31, 0x13); // 参数长度错误
+        return;
+    }
+
+    // 检查RoutineControl类型
+    uint8_t RoutineControlType = msg->buf[1] & 0x7F;
+    if (RoutineControlType != 0x01) // 只支持StartRoutine
+    {
+        NegativeResponse(msg->buf[0], 0x12); // 不支持的服务类型
+        return;
+    }
+
+    uint16_t RoutineIdentifier = (uint16_t)msg->buf[2] << 8 | msg->buf[3];
+
+    // 处理不同的RoutineIdentifier
+    switch (RoutineIdentifier)
+    {
+        case 0x0203: // 请求升级
+            if (msg->buf_len != 4)
+            {
+                NegativeResponse(msg->buf[0], 0x13);
+                return;
+            }
+            ota_start_flag = 1;
+            result_code = 0x00;
+            load_sequence_state = 0x00;
+            app2_crc_flag = 0;
+            PositiveResponseEnable = 1;
+            break;
+
+        case 0xFF00: // 擦除Flash
+            if (msg->buf_len != 13)
+            {
+                NegativeResponse(msg->buf[0], 0x13);
+                return;
+            }
+
+            // 提取擦除地址和大小
+            earse_MemoryAddress = (uint32_t)((msg->buf[5] << 24) | (msg->buf[6] << 16) | (msg->buf[7] << 8) | msg->buf[8]);
+            earse_MemorySize = (uint32_t)((msg->buf[9] << 24) | (msg->buf[10] << 16) | (msg->buf[11] << 8) | msg->buf[12]);
+
+            // 验证地址范围
+            //if ((earse_MemoryAddress != APP_START_ADDRESS) || (earse_MemorySize > (APP_STOP_ADDRESS - APP_START_ADDRESS)))
+			//if ((earse_MemoryAddress != APP2_ADDRESS) || (earse_MemorySize > (APP2_ADDRESS - APP1_ADDRESS)))
+			if ((earse_MemoryAddress != APP1_ADDRESS) || (earse_MemorySize > (APP2_ADDRESS - APP1_ADDRESS)))
+            {
+                NegativeResponse(msg->buf[0], 0x31);
+                return;
+            }
+
+            // 执行擦除操作
+            oReturnCheck = flash_erase_app(2);
+
+            // 根据擦除结果设置响应
+            result_code = (oReturnCheck == 0) ? 0x00 : 0x01;
+            if (result_code == 0x00)
+            {
+                load_sequence_state = 0x01; // 进入数据传输流程
+            }
+
+            PositiveResponseEnable = 1;
+            break;
+
+        case 0x0202: // CRC32验证
+            if (msg->buf_len != 8)
+            {
+                NegativeResponse(msg->buf[0], 0x13);
+                return;
+            }
+
+            // 提取CRC32值
+            CRC32_value = (uint32_t)(
+                (msg->buf[4] << 24) |
+                (msg->buf[5] << 16) |
+                (msg->buf[6] << 8) |
+                msg->buf[7]
+            );
+
+            // 验证CRC32
+            result_code = (CRC32_value == crc32val) ? 0x00 : 0x01;
+            if(result_code==0)//校验成功
+            {
+            	app2_crc_flag = 1;
+            }
+            else
+            {
+            	app2_crc_flag = 0;
+            }
+            PositiveResponseEnable = 1;
+            break;
+
+        case 0x0E0E: // 切换旧app版本
+            if (msg->buf_len != 4)
+            {
+                NegativeResponse(msg->buf[0], 0x13);
+                return;
+            }
+
+			response_buf[0] = msg->buf[0] + 0x40; // 正响应服务ID
+			response_buf[1] = msg->buf[1];        // RoutineControlType
+			response_buf[2] = msg->buf[2];        // RoutineIdentifier高字节
+			response_buf[3] = msg->buf[3];        // RoutineIdentifier低字节
+			response_buf[4] = 0;        // 结果代码
+
+			// 设置响应消息长度
+			msg_req.buf_len = 5;
+
+			// 发送响应
+			i15765_tx_app(&msg_req, &status_rq);
+			jump_to_app(APP1_ADDRESS);
+            break;
+
+        case 0x0E0F: // 切换新app版本
+            if (msg->buf_len != 4)
+            {
+                NegativeResponse(msg->buf[0], 0x13);
+                return;
+            }
+#if 1
+			//计算固件大小，判断是否可以双备份升级
+			if(earse_MemorySize < (APP2_ADDRESS - APP1_ADDRESS))
+			{
+				//flash_copy_app();
+				app2_copy_to_app1();
+				//校验CRC
+				crc32val = 0xFFFFFFFF;
+				uint8_t app2_data[1];
+				for(uint32_t i = 0;i < earse_MemorySize; i++)
+				{
+					app2_data[0] = *(volatile uint8_t*)(APP1_ADDRESS + i);
+					crc32val = crc32(crc32val, app2_data, 1);
+				}
+				if(CRC32_value == crc32val)
+				{
+	                response_buf[0] = msg->buf[0] + 0x40; // 正响应服务ID
+	                response_buf[1] = msg->buf[1];        // RoutineControlType
+	                response_buf[2] = msg->buf[2];        // RoutineIdentifier高字节
+	                response_buf[3] = msg->buf[3];        // RoutineIdentifier低字节
+	                response_buf[4] = 0;        // 结果代码
+
+	                // 设置响应消息长度
+	                msg_req.buf_len = 5;
+
+	                // 发送响应
+	                i15765_tx_app(&msg_req, &status_rq);
+
+					app_status_set(1,true);
+					jump_to_app(APP1_ADDRESS);
+				}
+				else
+				{
+	                response_buf[0] = msg->buf[0] + 0x40; // 正响应服务ID
+	                response_buf[1] = msg->buf[1];        // RoutineControlType
+	                response_buf[2] = msg->buf[2];        // RoutineIdentifier高字节
+	                response_buf[3] = msg->buf[3];        // RoutineIdentifier低字节
+	                response_buf[4] = 1;        // 结果代码
+
+	                // 设置响应消息长度
+	                msg_req.buf_len = 5;
+
+	                // 发送响应
+	                i15765_tx_app(&msg_req, &status_rq);
+	                return;
+				}
+			}
+#endif
+
+        default:
+            NegativeResponse(msg->buf[0], 0x31); // 不支持的服务
+            return;
+    }
+
+    // 发送正响应
+    if (PositiveResponseEnable == 1)
+    {
+        // 构建响应数据
+        response_buf[0] = msg->buf[0] + 0x40; // 正响应服务ID
+        response_buf[1] = msg->buf[1];        // RoutineControlType
+        response_buf[2] = msg->buf[2];        // RoutineIdentifier高字节
+        response_buf[3] = msg->buf[3];        // RoutineIdentifier低字节
+        response_buf[4] = result_code;        // 结果代码
+
+        // 设置响应消息长度
+        msg_req.buf_len = 5;
+
+        // 发送响应
+        i15765_tx_app(&msg_req, &status_rq);
+    }
+}
+
+
+void SID_34_function(i15765_t *msg)
+{
+	i15765_t msg_req;
+	uint8_t buf[8];
+	uint8_t status_rq;
+	uint8_t PositiveResponseEnable = 0;
+
+	msg_req.buf = buf;
+
+	if(msg->buf_len!=11)
+	{
+		NegativeResponse(msg->buf[0],0x13);
+		return;
+	}
+
+	//3
+	if(load_sequence_state != 0x01)
+	{
+		NegativeResponse(msg->buf[0],0x24);	//(24)
+		return;
+	}
+
+	DataFormatIdentifier = msg->buf[1];
+	addressAndLengthFormatIdentifier = msg->buf[2];//0x44
+	//Flashַ
+	load_MemoryAddress = (uint32_t)((uint32_t)msg->buf[3]<<24)|((uint32_t)msg->buf[4]<<16)|((uint32_t)msg->buf[5]<<8)|msg->buf[6];
+	load_MemorySize = (uint32_t)((uint32_t)msg->buf[7]<<24)|((uint32_t)msg->buf[8]<<16)|((uint32_t)msg->buf[9]<<8)|msg->buf[10];
+
+	if(load_MemorySize%MaxNumberOfBlockLength == 0)
+	{
+		load_BlockNum = load_MemorySize/MaxNumberOfBlockLength;
+	}
+	else
+	{
+		load_BlockNum = load_MemorySize/MaxNumberOfBlockLength + 1;
+	}
+
+#if   0
+	//
+	if(load_MemoryAddress != load_MemoryAddress_next)
+	{
+		NegativeResponse(msg->buf[0],0x31);	//
+		return;
+	}
+	load_MemoryAddress_next = load_MemoryAddress + load_MemorySize;
+	//////////////////////////////////////////////////////////////////////////////////////////////////////////////
+
+#endif
+
+	if((load_MemoryAddress == APP1_ADDRESS)&& load_MemorySize <= (APP2_ADDRESS - APP1_ADDRESS))
+	{
+		load_MemoryAddress = APP2_ADDRESS;//虽是APP1的固件地址，但写在备份区APP2地址
+		PositiveResponseEnable = 1;
+		buf[0] = msg->buf[0]+0x40;	// PositiveResponseServiceIdentifier
+		buf[1] = msg->buf[1];		// LengthFormatIdentifier
+
+		if(MaxNumberOfBlockLength > 0xFF)
+		{
+			//MaxNumberOfBlockLength
+			buf[2] = (uint8)((MaxNumberOfBlockLength>>8)&0xFF);
+			buf[3] = (uint8)(MaxNumberOfBlockLength&0xFF);
+			msg_req.buf_len = 4;
+		}
+		else
+		{
+			//MaxNumberOfBlockLength
+			buf[2] = (uint8) MaxNumberOfBlockLength;
+			msg_req.buf_len = 3;
+		}
+
+		load_sequence_state = 0x02;
+		BlockSequenceCounter_pre = 0;
+		crc32val = 0xFFFFFFFF;
+		load_BlockCount = 0;
+	}
+	else
+	{
+		NegativeResponse(msg->buf[0],31);//
+		return;
+	}
+
+
+	if(PositiveResponseEnable==1)
+	{
+		/* transmit message */
+		i15765_tx_app(&msg_req, &status_rq);
+	}
+}
+
+void SID_36_function(i15765_t *msg)
+{
+	i15765_t msg_req;
+	uint8_t buf[8];
+	uint8_t status_rq;
+	uint8_t PositiveResponseEnable = 0;
+
+	uint16_t i = 0;
+
+	int oReturnCheck;
+
+	uint8_t TransferRequestParameterRecord[4096];
+
+	msg_req.buf = buf;
+
+	if(load_sequence_state != 0x02)
+	{
+		NegativeResponse(msg->buf[0],0x24);
+		return;
+	}
+
+	BlockSequenceCounter = msg->buf[1];
+	if(BlockSequenceCounter == 0x00)
+	{
+		if(BlockSequenceCounter_pre != 0xFF)
+		{
+			NegativeResponse(msg->buf[0],0x73);//
+			return;
+		}
+	}
+	else if(BlockSequenceCounter != (BlockSequenceCounter_pre+1))
+	{
+		NegativeResponse(msg->buf[0],0x73);//
+		return;
+	}
+	BlockSequenceCounter_pre = BlockSequenceCounter;
+	//////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
+
+	for(i=0; i < msg->buf_len-2;i++)
+	{
+		TransferRequestParameterRecord[i] = msg->buf[2+i];
+	}
+	crc32val = crc32(crc32val, TransferRequestParameterRecord, msg->buf_len-2);
+	oReturnCheck = flash_write_page((load_MemoryAddress + load_BlockCount*MaxNumberOfBlockLength), TransferRequestParameterRecord, msg->buf_len-2, false);
+
+	if(!oReturnCheck)
+	{
+		WriteFlashAlreadySize = WriteFlashAlreadySize + msg->buf_len-2;
+		//
+		PositiveResponseEnable = 1;
+		buf[0] = msg->buf[0]+0x40;	// PositiveResponseServiceIdentifier
+		buf[1] = msg->buf[1];		// BlockSequenceCounter
+		buf[2] = (uint8)((crc32val>>24)&0xFF);
+		buf[3] = (uint8)((crc32val>>16)&0xFF);
+		buf[4] = (uint8)((crc32val>>8)&0xFF);
+		buf[5] = (uint8)((crc32val>>0)&0xFF);
+		msg_req.buf_len = 6;
+		/////////////////////////////////////////////////////////////////
+
+		load_BlockCount++;
+		if(load_BlockCount==load_BlockNum)
+		{
+			load_sequence_state = 0x03;
+		}
+		else
+		{
+			load_sequence_state = 0x02;
+		}
+	}
+	else
+	{
+		// Indicate that the flash programming failed.
+		NegativeResponse(msg->buf[0],0x70);//
+		return;
+	}
+	////////////////////////////////////////////////////////////////////
+
+	if(PositiveResponseEnable==1)
+	{
+		/* transmit message */
+		i15765_tx_app(&msg_req, &status_rq);
+	}
+}
+
+void SID_37_function(i15765_t *msg)
+{
+	i15765_t msg_req;
+	uint8_t buf[8];
+	uint8_t status_rq;
+
+	/* basic stuff */
+	msg_req.buf = buf;
+	msg_req.pri = 6;
+	msg_req.ta = 0x0C;
+
+	if(msg->buf_len != 1)
+	{
+		NegativeResponse(msg->buf[0],0x13);	//
+		return;
+	}
+
+//	if(load_sequence_state != 0x02)
+	if(load_sequence_state != 0x03)
+	{
+		NegativeResponse(msg->buf[0],0x24);	//(24)
+		return;
+	}
+	else
+	{
+		buf[0] = msg->buf[0]+0x40;	// PositiveResponseServiceIdentifier
+
+		msg_req.buf_len = 1;
+		/* transmit message */
+		i15765_tx_app(&msg_req, &status_rq);
+
+		//
+		load_sequence_state = 0x00;
+		load_BlockCount = 0;
+		BlockSequenceCounter_pre = 0;
+	}
+}

Core/can_tp/i15765sid_function.h

@@ -0,0 +1,21 @@
+#ifndef I15765SID_FUNCTION_H_
+#define I15765SID_FUNCTION_H_
+
+extern uint8_t	DiagnosticSessionType;
+
+//bootloader
+extern uint8_t DataFormatIdentifier;
+extern uint8_t addressAndLengthFormatIdentifier;
+extern uint32_t MemoryAddress;
+extern uint32_t MemorySize;
+
+void NegativeResponse(uint8_t sid,uint8_t NegativeResponseCode);
+
+void SID_11_function(i15765_t *msg);
+void SID_2E_function(i15765_t *msg);
+void SID_31_function(i15765_t *msg);
+void SID_34_function(i15765_t *msg);
+void SID_36_function(i15765_t *msg);
+void SID_37_function(i15765_t *msg);
+
+#endif

Debug/Core/Src/can.cyclo

@@ -0,0 +1,9 @@
+../Core/Src/can.c:34:6:MX_CAN1_Init	2
+../Core/Src/can.c:68:6:HAL_CAN_MspInit	2
+../Core/Src/can.c:101:6:HAL_CAN_MspDeInit	2
+../Core/Src/can.c:130:10:get_hardware_version	1
+../Core/Src/can.c:135:10:get_software_version	2
+../Core/Src/can.c:147:10:get_publish_data	2
+../Core/Src/can.c:158:6:CAN_Filter_config	2
+../Core/Src/can.c:183:6:CAN_SendData	4
+../Core/Src/can.c:217:6:HAL_CAN_RxFifo0MsgPendingCallback	7

Debug/Core/Src/can.d

@@ -0,0 +1,80 @@
+Core/Src/can.o: ../Core/Src/can.c ../Core/Inc/can.h ../Core/Inc/main.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal.h \
+ ../Core/Inc/stm32f4xx_hal_conf.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h \
+ ../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h \
+ ../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f405xx.h \
+ ../Drivers/CMSIS/Include/core_cm4.h \
+ ../Drivers/CMSIS/Include/cmsis_version.h \
+ ../Drivers/CMSIS/Include/cmsis_compiler.h \
+ ../Drivers/CMSIS/Include/cmsis_gcc.h \
+ ../Drivers/CMSIS/Include/mpu_armv7.h \
+ ../Drivers/CMSIS/Device/ST/STM32F4xx/Include/system_stm32f4xx.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc_ex.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio_ex.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_exti.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma_ex.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cortex.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_can.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ex.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr_ex.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim_ex.h \
+ D:/ODrive_STM32F405/stm32F405_bootloader/stm32f405_boot/Core/can_tp/UDS.h \
+ D:/ODrive_STM32F405/stm32F405_bootloader/stm32f405_boot/Core/can_tp/i15765.h \
+ D:/ODrive_STM32F405/stm32F405_bootloader/stm32f405_boot/Core/can_tp/i15765sid_function.h \
+ D:/ODrive_STM32F405/stm32F405_bootloader/stm32f405_boot/Core/can_tp/i15765app.h \
+ D:/ODrive_STM32F405/stm32F405_bootloader/stm32f405_boot/Core/can_tp/hal_stdtypes.h \
+ D:/ODrive_STM32F405/stm32F405_bootloader/stm32f405_boot/Core/can_tp/MCU_CAN.h \
+ ../Core/Inc/stm32f4xx_board.h \
+ D:/ODrive_STM32F405/stm32F405_bootloader/stm32f405_boot/Core/can_tp/bits.h \
+ D:/ODrive_STM32F405/stm32F405_bootloader/stm32f405_boot/Core/can_tp/CRC32.h \
+ ../Core/Inc/flash.h ../Core/Inc/stm32f4xx_board.h
+../Core/Inc/can.h:
+../Core/Inc/main.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal.h:
+../Core/Inc/stm32f4xx_hal_conf.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h:
+../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h:
+../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f405xx.h:
+../Drivers/CMSIS/Include/core_cm4.h:
+../Drivers/CMSIS/Include/cmsis_version.h:
+../Drivers/CMSIS/Include/cmsis_compiler.h:
+../Drivers/CMSIS/Include/cmsis_gcc.h:
+../Drivers/CMSIS/Include/mpu_armv7.h:
+../Drivers/CMSIS/Device/ST/STM32F4xx/Include/system_stm32f4xx.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc_ex.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio_ex.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_exti.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma_ex.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cortex.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_can.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ex.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr_ex.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim_ex.h:
+D:/ODrive_STM32F405/stm32F405_bootloader/stm32f405_boot/Core/can_tp/UDS.h:
+D:/ODrive_STM32F405/stm32F405_bootloader/stm32f405_boot/Core/can_tp/i15765.h:
+D:/ODrive_STM32F405/stm32F405_bootloader/stm32f405_boot/Core/can_tp/i15765sid_function.h:
+D:/ODrive_STM32F405/stm32F405_bootloader/stm32f405_boot/Core/can_tp/i15765app.h:
+D:/ODrive_STM32F405/stm32F405_bootloader/stm32f405_boot/Core/can_tp/hal_stdtypes.h:
+D:/ODrive_STM32F405/stm32F405_bootloader/stm32f405_boot/Core/can_tp/MCU_CAN.h:
+../Core/Inc/stm32f4xx_board.h:
+D:/ODrive_STM32F405/stm32F405_bootloader/stm32f405_boot/Core/can_tp/bits.h:
+D:/ODrive_STM32F405/stm32F405_bootloader/stm32f405_boot/Core/can_tp/CRC32.h:
+../Core/Inc/flash.h:
+../Core/Inc/stm32f4xx_board.h:

Debug/Core/Src/can.su

@@ -0,0 +1,9 @@
+../Core/Src/can.c:34:6:MX_CAN1_Init	8	static
+../Core/Src/can.c:68:6:HAL_CAN_MspInit	48	static
+../Core/Src/can.c:101:6:HAL_CAN_MspDeInit	16	static
+../Core/Src/can.c:130:10:get_hardware_version	4	static
+../Core/Src/can.c:135:10:get_software_version	4	static
+../Core/Src/can.c:147:10:get_publish_data	4	static
+../Core/Src/can.c:158:6:CAN_Filter_config	48	static
+../Core/Src/can.c:183:6:CAN_SendData	32	static
+../Core/Src/can.c:217:6:HAL_CAN_RxFifo0MsgPendingCallback	48	static

Debug/Core/Src/flash.cyclo

@@ -0,0 +1,17 @@
+../Core/Src/flash.c:72:6:HAL_FLASH_ClearError	1
+../Core/Src/flash.c:76:17:_sector_frame_address	23
+../Core/Src/flash.c:129:6:flash_unlock	1
+../Core/Src/flash.c:140:6:flash_lock	1
+../Core/Src/flash.c:146:6:flash_wait_ready	6
+../Core/Src/flash.c:171:6:flash_erase_sector	5
+../Core/Src/flash.c:211:13:flash_write_word	1
+../Core/Src/flash.c:225:13:flash_write_byte	1
+../Core/Src/flash.c:242:5:flash_erase_page	1
+../Core/Src/flash.c:252:5:flash_erase_pages	2
+../Core/Src/flash.c:262:5:flash_erase_app	3
+../Core/Src/flash.c:283:6:app_status_set	3
+../Core/Src/flash.c:299:5:flash_write_page	7
+../Core/Src/flash.c:326:5:flash_test	1
+../Core/Src/flash.c:348:6:app1_copy_to_app2	2
+../Core/Src/flash.c:358:6:app2_copy_to_app1	2
+../Core/Src/flash.c:403:6:jump_to_app	2

Debug/Core/Src/flash.d

@@ -0,0 +1,66 @@
+Core/Src/flash.o: ../Core/Src/flash.c ../Core/Inc/flash.h \
+ ../Core/Inc/stm32f4xx_board.h \
+ ../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h \
+ ../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f405xx.h \
+ ../Drivers/CMSIS/Include/core_cm4.h \
+ ../Drivers/CMSIS/Include/cmsis_version.h \
+ ../Drivers/CMSIS/Include/cmsis_compiler.h \
+ ../Drivers/CMSIS/Include/cmsis_gcc.h \
+ ../Drivers/CMSIS/Include/mpu_armv7.h \
+ ../Drivers/CMSIS/Device/ST/STM32F4xx/Include/system_stm32f4xx.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal.h \
+ ../Core/Inc/stm32f4xx_hal_conf.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc_ex.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio_ex.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_exti.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma_ex.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cortex.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_can.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ex.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr_ex.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim_ex.h \
+ ../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f405xx.h \
+ ../Core/Inc/stm32f4xx_board.h ../Core/Inc/can.h ../Core/Inc/main.h
+../Core/Inc/flash.h:
+../Core/Inc/stm32f4xx_board.h:
+../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h:
+../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f405xx.h:
+../Drivers/CMSIS/Include/core_cm4.h:
+../Drivers/CMSIS/Include/cmsis_version.h:
+../Drivers/CMSIS/Include/cmsis_compiler.h:
+../Drivers/CMSIS/Include/cmsis_gcc.h:
+../Drivers/CMSIS/Include/mpu_armv7.h:
+../Drivers/CMSIS/Device/ST/STM32F4xx/Include/system_stm32f4xx.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal.h:
+../Core/Inc/stm32f4xx_hal_conf.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc_ex.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio_ex.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_exti.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma_ex.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cortex.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_can.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ex.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr_ex.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim_ex.h:
+../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f405xx.h:
+../Core/Inc/stm32f4xx_board.h:
+../Core/Inc/can.h:
+../Core/Inc/main.h:

Debug/Core/Src/flash.su

@@ -0,0 +1,17 @@
+../Core/Src/flash.c:72:6:HAL_FLASH_ClearError	4	static
+../Core/Src/flash.c:76:17:_sector_frame_address	24	static
+../Core/Src/flash.c:129:6:flash_unlock	4	static
+../Core/Src/flash.c:140:6:flash_lock	4	static
+../Core/Src/flash.c:146:6:flash_wait_ready	24	static
+../Core/Src/flash.c:171:6:flash_erase_sector	24	static
+../Core/Src/flash.c:211:13:flash_write_word	16	static
+../Core/Src/flash.c:225:13:flash_write_byte	16	static
+../Core/Src/flash.c:242:5:flash_erase_page	16	static
+../Core/Src/flash.c:252:5:flash_erase_pages	24	static
+../Core/Src/flash.c:262:5:flash_erase_app	16	static
+../Core/Src/flash.c:283:6:app_status_set	24	static
+../Core/Src/flash.c:299:5:flash_write_page	32	static
+../Core/Src/flash.c:326:5:flash_test	1040	static
+../Core/Src/flash.c:348:6:app1_copy_to_app2	16	static
+../Core/Src/flash.c:358:6:app2_copy_to_app1	16	static
+../Core/Src/flash.c:403:6:jump_to_app	24	static,ignoring_inline_asm

Debug/Core/Src/gpio.cyclo

@@ -0,0 +1 @@
+../Core/Src/gpio.c:42:6:MX_GPIO_Init	1

Debug/Core/Src/gpio.d

@@ -0,0 +1,59 @@
+Core/Src/gpio.o: ../Core/Src/gpio.c ../Core/Inc/gpio.h ../Core/Inc/main.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal.h \
+ ../Core/Inc/stm32f4xx_hal_conf.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h \
+ ../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h \
+ ../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f405xx.h \
+ ../Drivers/CMSIS/Include/core_cm4.h \
+ ../Drivers/CMSIS/Include/cmsis_version.h \
+ ../Drivers/CMSIS/Include/cmsis_compiler.h \
+ ../Drivers/CMSIS/Include/cmsis_gcc.h \
+ ../Drivers/CMSIS/Include/mpu_armv7.h \
+ ../Drivers/CMSIS/Device/ST/STM32F4xx/Include/system_stm32f4xx.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc_ex.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio_ex.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_exti.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma_ex.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cortex.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_can.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ex.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr_ex.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim_ex.h
+../Core/Inc/gpio.h:
+../Core/Inc/main.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal.h:
+../Core/Inc/stm32f4xx_hal_conf.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h:
+../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h:
+../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f405xx.h:
+../Drivers/CMSIS/Include/core_cm4.h:
+../Drivers/CMSIS/Include/cmsis_version.h:
+../Drivers/CMSIS/Include/cmsis_compiler.h:
+../Drivers/CMSIS/Include/cmsis_gcc.h:
+../Drivers/CMSIS/Include/mpu_armv7.h:
+../Drivers/CMSIS/Device/ST/STM32F4xx/Include/system_stm32f4xx.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc_ex.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio_ex.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_exti.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma_ex.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cortex.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_can.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ex.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr_ex.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim_ex.h:

Debug/Core/Src/gpio.su

@@ -0,0 +1 @@
+../Core/Src/gpio.c:42:6:MX_GPIO_Init	48	static

Debug/Core/Src/main.cyclo

@@ -0,0 +1,4 @@
+../Core/Src/main.c:78:10:get_app_version	5
+../Core/Src/main.c:112:5:main	5
+../Core/Src/main.c:239:6:SystemClock_Config	3
+../Core/Src/main.c:288:6:Error_Handler	1

Debug/Core/Src/main.d

@@ -0,0 +1,84 @@
+Core/Src/main.o: ../Core/Src/main.c ../Core/Inc/main.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal.h \
+ ../Core/Inc/stm32f4xx_hal_conf.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h \
+ ../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h \
+ ../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f405xx.h \
+ ../Drivers/CMSIS/Include/core_cm4.h \
+ ../Drivers/CMSIS/Include/cmsis_version.h \
+ ../Drivers/CMSIS/Include/cmsis_compiler.h \
+ ../Drivers/CMSIS/Include/cmsis_gcc.h \
+ ../Drivers/CMSIS/Include/mpu_armv7.h \
+ ../Drivers/CMSIS/Device/ST/STM32F4xx/Include/system_stm32f4xx.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc_ex.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio_ex.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_exti.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma_ex.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cortex.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_can.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ex.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr_ex.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim_ex.h \
+ ../Core/Inc/can.h ../Core/Inc/main.h ../Core/Inc/tim.h \
+ ../Core/Inc/gpio.h ../Core/Inc/flash.h ../Core/Inc/stm32f4xx_board.h \
+ D:/ODrive_STM32F405/stm32F405_bootloader/stm32f405_boot/Core/can_tp/UDS.h \
+ D:/ODrive_STM32F405/stm32F405_bootloader/stm32f405_boot/Core/can_tp/i15765.h \
+ D:/ODrive_STM32F405/stm32F405_bootloader/stm32f405_boot/Core/can_tp/i15765sid_function.h \
+ D:/ODrive_STM32F405/stm32F405_bootloader/stm32f405_boot/Core/can_tp/i15765app.h \
+ D:/ODrive_STM32F405/stm32F405_bootloader/stm32f405_boot/Core/can_tp/hal_stdtypes.h \
+ D:/ODrive_STM32F405/stm32F405_bootloader/stm32f405_boot/Core/can_tp/MCU_CAN.h \
+ ../Core/Inc/stm32f4xx_board.h \
+ D:/ODrive_STM32F405/stm32F405_bootloader/stm32f405_boot/Core/can_tp/bits.h \
+ D:/ODrive_STM32F405/stm32F405_bootloader/stm32f405_boot/Core/can_tp/CRC32.h
+../Core/Inc/main.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal.h:
+../Core/Inc/stm32f4xx_hal_conf.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h:
+../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h:
+../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f405xx.h:
+../Drivers/CMSIS/Include/core_cm4.h:
+../Drivers/CMSIS/Include/cmsis_version.h:
+../Drivers/CMSIS/Include/cmsis_compiler.h:
+../Drivers/CMSIS/Include/cmsis_gcc.h:
+../Drivers/CMSIS/Include/mpu_armv7.h:
+../Drivers/CMSIS/Device/ST/STM32F4xx/Include/system_stm32f4xx.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc_ex.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio_ex.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_exti.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma_ex.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cortex.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_can.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ex.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr_ex.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim_ex.h:
+../Core/Inc/can.h:
+../Core/Inc/main.h:
+../Core/Inc/tim.h:
+../Core/Inc/gpio.h:
+../Core/Inc/flash.h:
+../Core/Inc/stm32f4xx_board.h:
+D:/ODrive_STM32F405/stm32F405_bootloader/stm32f405_boot/Core/can_tp/UDS.h:
+D:/ODrive_STM32F405/stm32F405_bootloader/stm32f405_boot/Core/can_tp/i15765.h:
+D:/ODrive_STM32F405/stm32F405_bootloader/stm32f405_boot/Core/can_tp/i15765sid_function.h:
+D:/ODrive_STM32F405/stm32F405_bootloader/stm32f405_boot/Core/can_tp/i15765app.h:
+D:/ODrive_STM32F405/stm32F405_bootloader/stm32f405_boot/Core/can_tp/hal_stdtypes.h:
+D:/ODrive_STM32F405/stm32F405_bootloader/stm32f405_boot/Core/can_tp/MCU_CAN.h:
+../Core/Inc/stm32f4xx_board.h:
+D:/ODrive_STM32F405/stm32F405_bootloader/stm32f405_boot/Core/can_tp/bits.h:
+D:/ODrive_STM32F405/stm32F405_bootloader/stm32f405_boot/Core/can_tp/CRC32.h:

Debug/Core/Src/main.su

@@ -0,0 +1,4 @@
+../Core/Src/main.c:78:10:get_app_version	24	static
+../Core/Src/main.c:112:5:main	16	static
+../Core/Src/main.c:239:6:SystemClock_Config	88	static
+../Core/Src/main.c:288:6:Error_Handler	4	static,ignoring_inline_asm

Debug/Core/Src/stm32f4xx_hal_msp.cyclo

@@ -0,0 +1 @@
+../Core/Src/stm32f4xx_hal_msp.c:63:6:HAL_MspInit	1

Debug/Core/Src/stm32f4xx_hal_msp.d

@@ -0,0 +1,58 @@
+Core/Src/stm32f4xx_hal_msp.o: ../Core/Src/stm32f4xx_hal_msp.c \
+ ../Core/Inc/main.h ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal.h \
+ ../Core/Inc/stm32f4xx_hal_conf.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h \
+ ../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h \
+ ../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f405xx.h \
+ ../Drivers/CMSIS/Include/core_cm4.h \
+ ../Drivers/CMSIS/Include/cmsis_version.h \
+ ../Drivers/CMSIS/Include/cmsis_compiler.h \
+ ../Drivers/CMSIS/Include/cmsis_gcc.h \
+ ../Drivers/CMSIS/Include/mpu_armv7.h \
+ ../Drivers/CMSIS/Device/ST/STM32F4xx/Include/system_stm32f4xx.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc_ex.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio_ex.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_exti.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma_ex.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cortex.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_can.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ex.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr_ex.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim_ex.h
+../Core/Inc/main.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal.h:
+../Core/Inc/stm32f4xx_hal_conf.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h:
+../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h:
+../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f405xx.h:
+../Drivers/CMSIS/Include/core_cm4.h:
+../Drivers/CMSIS/Include/cmsis_version.h:
+../Drivers/CMSIS/Include/cmsis_compiler.h:
+../Drivers/CMSIS/Include/cmsis_gcc.h:
+../Drivers/CMSIS/Include/mpu_armv7.h:
+../Drivers/CMSIS/Device/ST/STM32F4xx/Include/system_stm32f4xx.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc_ex.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio_ex.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_exti.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma_ex.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cortex.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_can.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ex.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr_ex.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim_ex.h:

Debug/Core/Src/stm32f4xx_hal_msp.su

@@ -0,0 +1 @@
+../Core/Src/stm32f4xx_hal_msp.c:63:6:HAL_MspInit	16	static

Debug/Core/Src/stm32f4xx_it.cyclo

@@ -0,0 +1,11 @@
+../Core/Src/stm32f4xx_it.c:70:6:NMI_Handler	1
+../Core/Src/stm32f4xx_it.c:85:6:HardFault_Handler	1
+../Core/Src/stm32f4xx_it.c:100:6:MemManage_Handler	1
+../Core/Src/stm32f4xx_it.c:115:6:BusFault_Handler	1
+../Core/Src/stm32f4xx_it.c:130:6:UsageFault_Handler	1
+../Core/Src/stm32f4xx_it.c:145:6:SVC_Handler	1
+../Core/Src/stm32f4xx_it.c:158:6:DebugMon_Handler	1
+../Core/Src/stm32f4xx_it.c:171:6:PendSV_Handler	1
+../Core/Src/stm32f4xx_it.c:184:6:SysTick_Handler	1
+../Core/Src/stm32f4xx_it.c:205:6:CAN1_RX0_IRQHandler	1
+../Core/Src/stm32f4xx_it.c:219:6:TIM2_IRQHandler	1

Debug/Core/Src/stm32f4xx_it.d

@@ -0,0 +1,60 @@
+Core/Src/stm32f4xx_it.o: ../Core/Src/stm32f4xx_it.c ../Core/Inc/main.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal.h \
+ ../Core/Inc/stm32f4xx_hal_conf.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h \
+ ../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h \
+ ../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f405xx.h \
+ ../Drivers/CMSIS/Include/core_cm4.h \
+ ../Drivers/CMSIS/Include/cmsis_version.h \
+ ../Drivers/CMSIS/Include/cmsis_compiler.h \
+ ../Drivers/CMSIS/Include/cmsis_gcc.h \
+ ../Drivers/CMSIS/Include/mpu_armv7.h \
+ ../Drivers/CMSIS/Device/ST/STM32F4xx/Include/system_stm32f4xx.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc_ex.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio_ex.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_exti.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma_ex.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cortex.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_can.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ex.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr_ex.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim_ex.h \
+ ../Core/Inc/stm32f4xx_it.h
+../Core/Inc/main.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal.h:
+../Core/Inc/stm32f4xx_hal_conf.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h:
+../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h:
+../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f405xx.h:
+../Drivers/CMSIS/Include/core_cm4.h:
+../Drivers/CMSIS/Include/cmsis_version.h:
+../Drivers/CMSIS/Include/cmsis_compiler.h:
+../Drivers/CMSIS/Include/cmsis_gcc.h:
+../Drivers/CMSIS/Include/mpu_armv7.h:
+../Drivers/CMSIS/Device/ST/STM32F4xx/Include/system_stm32f4xx.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc_ex.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio_ex.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_exti.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma_ex.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cortex.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_can.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ex.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr_ex.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim_ex.h:
+../Core/Inc/stm32f4xx_it.h:

Debug/Core/Src/stm32f4xx_it.su

@@ -0,0 +1,11 @@
+../Core/Src/stm32f4xx_it.c:70:6:NMI_Handler	4	static
+../Core/Src/stm32f4xx_it.c:85:6:HardFault_Handler	4	static
+../Core/Src/stm32f4xx_it.c:100:6:MemManage_Handler	4	static
+../Core/Src/stm32f4xx_it.c:115:6:BusFault_Handler	4	static
+../Core/Src/stm32f4xx_it.c:130:6:UsageFault_Handler	4	static
+../Core/Src/stm32f4xx_it.c:145:6:SVC_Handler	4	static
+../Core/Src/stm32f4xx_it.c:158:6:DebugMon_Handler	4	static
+../Core/Src/stm32f4xx_it.c:171:6:PendSV_Handler	4	static
+../Core/Src/stm32f4xx_it.c:184:6:SysTick_Handler	8	static
+../Core/Src/stm32f4xx_it.c:205:6:CAN1_RX0_IRQHandler	8	static
+../Core/Src/stm32f4xx_it.c:219:6:TIM2_IRQHandler	8	static

Debug/Core/Src/subdir.mk

@@ -0,0 +1,54 @@
+################################################################################
+# Automatically-generated file. Do not edit!
+# Toolchain: GNU Tools for STM32 (13.3.rel1)
+################################################################################
+
+# Add inputs and outputs from these tool invocations to the build variables 
+C_SRCS += \
+../Core/Src/can.c \
+../Core/Src/flash.c \
+../Core/Src/gpio.c \
+../Core/Src/main.c \
+../Core/Src/stm32f4xx_hal_msp.c \
+../Core/Src/stm32f4xx_it.c \
+../Core/Src/syscalls.c \
+../Core/Src/sysmem.c \
+../Core/Src/system_stm32f4xx.c \
+../Core/Src/tim.c 
+
+OBJS += \
+./Core/Src/can.o \
+./Core/Src/flash.o \
+./Core/Src/gpio.o \
+./Core/Src/main.o \
+./Core/Src/stm32f4xx_hal_msp.o \
+./Core/Src/stm32f4xx_it.o \
+./Core/Src/syscalls.o \
+./Core/Src/sysmem.o \
+./Core/Src/system_stm32f4xx.o \
+./Core/Src/tim.o 
+
+C_DEPS += \
+./Core/Src/can.d \
+./Core/Src/flash.d \
+./Core/Src/gpio.d \
+./Core/Src/main.d \
+./Core/Src/stm32f4xx_hal_msp.d \
+./Core/Src/stm32f4xx_it.d \
+./Core/Src/syscalls.d \
+./Core/Src/sysmem.d \
+./Core/Src/system_stm32f4xx.d \
+./Core/Src/tim.d 
+
+
+# Each subdirectory must supply rules for building sources it contributes
+Core/Src/%.o Core/Src/%.su Core/Src/%.cyclo: ../Core/Src/%.c Core/Src/subdir.mk
+	arm-none-eabi-gcc "$<" -mcpu=cortex-m4 -std=gnu11 -g3 -DDEBUG -DUSE_HAL_DRIVER -DSTM32F405xx -c -I../Core/Inc -I../Drivers/STM32F4xx_HAL_Driver/Inc -I../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy -I../Drivers/CMSIS/Device/ST/STM32F4xx/Include -I../Drivers/CMSIS/Include -I"D:/ODrive_STM32F405/stm32F405_bootloader/stm32f405_boot/Core/can_tp" -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -fcyclomatic-complexity -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" --specs=nano.specs -mfpu=fpv4-sp-d16 -mfloat-abi=hard -mthumb -o "$@"
+
+clean: clean-Core-2f-Src
+
+clean-Core-2f-Src:
+	-$(RM) ./Core/Src/can.cyclo ./Core/Src/can.d ./Core/Src/can.o ./Core/Src/can.su ./Core/Src/flash.cyclo ./Core/Src/flash.d ./Core/Src/flash.o ./Core/Src/flash.su ./Core/Src/gpio.cyclo ./Core/Src/gpio.d ./Core/Src/gpio.o ./Core/Src/gpio.su ./Core/Src/main.cyclo ./Core/Src/main.d ./Core/Src/main.o ./Core/Src/main.su ./Core/Src/stm32f4xx_hal_msp.cyclo ./Core/Src/stm32f4xx_hal_msp.d ./Core/Src/stm32f4xx_hal_msp.o ./Core/Src/stm32f4xx_hal_msp.su ./Core/Src/stm32f4xx_it.cyclo ./Core/Src/stm32f4xx_it.d ./Core/Src/stm32f4xx_it.o ./Core/Src/stm32f4xx_it.su ./Core/Src/syscalls.cyclo ./Core/Src/syscalls.d ./Core/Src/syscalls.o ./Core/Src/syscalls.su ./Core/Src/sysmem.cyclo ./Core/Src/sysmem.d ./Core/Src/sysmem.o ./Core/Src/sysmem.su ./Core/Src/system_stm32f4xx.cyclo ./Core/Src/system_stm32f4xx.d ./Core/Src/system_stm32f4xx.o ./Core/Src/system_stm32f4xx.su ./Core/Src/tim.cyclo ./Core/Src/tim.d ./Core/Src/tim.o ./Core/Src/tim.su
+
+.PHONY: clean-Core-2f-Src
+

Debug/Core/Src/syscalls.cyclo

@@ -0,0 +1,18 @@
+../Core/Src/syscalls.c:44:6:initialise_monitor_handles	1
+../Core/Src/syscalls.c:48:5:_getpid	1
+../Core/Src/syscalls.c:53:5:_kill	1
+../Core/Src/syscalls.c:61:6:_exit	1
+../Core/Src/syscalls.c:67:27:_read	2
+../Core/Src/syscalls.c:80:27:_write	2
+../Core/Src/syscalls.c:92:5:_close	1
+../Core/Src/syscalls.c:99:5:_fstat	1
+../Core/Src/syscalls.c:106:5:_isatty	1
+../Core/Src/syscalls.c:112:5:_lseek	1
+../Core/Src/syscalls.c:120:5:_open	1
+../Core/Src/syscalls.c:128:5:_wait	1
+../Core/Src/syscalls.c:135:5:_unlink	1
+../Core/Src/syscalls.c:142:5:_times	1
+../Core/Src/syscalls.c:148:5:_stat	1
+../Core/Src/syscalls.c:155:5:_link	1
+../Core/Src/syscalls.c:163:5:_fork	1
+../Core/Src/syscalls.c:169:5:_execve	1

Debug/Core/Src/syscalls.d

@@ -0,0 +1 @@
+Core/Src/syscalls.o: ../Core/Src/syscalls.c

Debug/Core/Src/syscalls.su

@@ -0,0 +1,18 @@
+../Core/Src/syscalls.c:44:6:initialise_monitor_handles	4	static
+../Core/Src/syscalls.c:48:5:_getpid	4	static
+../Core/Src/syscalls.c:53:5:_kill	16	static
+../Core/Src/syscalls.c:61:6:_exit	16	static
+../Core/Src/syscalls.c:67:27:_read	32	static
+../Core/Src/syscalls.c:80:27:_write	32	static
+../Core/Src/syscalls.c:92:5:_close	16	static
+../Core/Src/syscalls.c:99:5:_fstat	16	static
+../Core/Src/syscalls.c:106:5:_isatty	16	static
+../Core/Src/syscalls.c:112:5:_lseek	24	static
+../Core/Src/syscalls.c:120:5:_open	12	static
+../Core/Src/syscalls.c:128:5:_wait	16	static
+../Core/Src/syscalls.c:135:5:_unlink	16	static
+../Core/Src/syscalls.c:142:5:_times	16	static
+../Core/Src/syscalls.c:148:5:_stat	16	static
+../Core/Src/syscalls.c:155:5:_link	16	static
+../Core/Src/syscalls.c:163:5:_fork	8	static
+../Core/Src/syscalls.c:169:5:_execve	24	static

Debug/Core/Src/sysmem.cyclo

@@ -0,0 +1 @@
+../Core/Src/sysmem.c:53:7:_sbrk	3

Debug/Core/Src/sysmem.d

@@ -0,0 +1 @@
+Core/Src/sysmem.o: ../Core/Src/sysmem.c

Debug/Core/Src/sysmem.su

@@ -0,0 +1 @@
+../Core/Src/sysmem.c:53:7:_sbrk	32	static

Debug/Core/Src/system_stm32f4xx.cyclo

@@ -0,0 +1,2 @@
+../Core/Src/system_stm32f4xx.c:167:6:SystemInit	1
+../Core/Src/system_stm32f4xx.c:220:6:SystemCoreClockUpdate	6

Debug/Core/Src/system_stm32f4xx.d

@@ -0,0 +1,57 @@
+Core/Src/system_stm32f4xx.o: ../Core/Src/system_stm32f4xx.c \
+ ../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h \
+ ../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f405xx.h \
+ ../Drivers/CMSIS/Include/core_cm4.h \
+ ../Drivers/CMSIS/Include/cmsis_version.h \
+ ../Drivers/CMSIS/Include/cmsis_compiler.h \
+ ../Drivers/CMSIS/Include/cmsis_gcc.h \
+ ../Drivers/CMSIS/Include/mpu_armv7.h \
+ ../Drivers/CMSIS/Device/ST/STM32F4xx/Include/system_stm32f4xx.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal.h \
+ ../Core/Inc/stm32f4xx_hal_conf.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc_ex.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio_ex.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_exti.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma_ex.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cortex.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_can.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ex.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr_ex.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim_ex.h
+../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h:
+../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f405xx.h:
+../Drivers/CMSIS/Include/core_cm4.h:
+../Drivers/CMSIS/Include/cmsis_version.h:
+../Drivers/CMSIS/Include/cmsis_compiler.h:
+../Drivers/CMSIS/Include/cmsis_gcc.h:
+../Drivers/CMSIS/Include/mpu_armv7.h:
+../Drivers/CMSIS/Device/ST/STM32F4xx/Include/system_stm32f4xx.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal.h:
+../Core/Inc/stm32f4xx_hal_conf.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc_ex.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio_ex.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_exti.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma_ex.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cortex.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_can.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ex.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr_ex.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim_ex.h:

Debug/Core/Src/system_stm32f4xx.su

@@ -0,0 +1,2 @@
+../Core/Src/system_stm32f4xx.c:167:6:SystemInit	4	static
+../Core/Src/system_stm32f4xx.c:220:6:SystemCoreClockUpdate	32	static

Debug/Core/Src/tim.cyclo

@@ -0,0 +1,4 @@
+../Core/Src/tim.c:32:6:MX_TIM2_Init	4
+../Core/Src/tim.c:72:6:HAL_TIM_Base_MspInit	2
+../Core/Src/tim.c:92:6:HAL_TIM_Base_MspDeInit	2
+../Core/Src/tim.c:117:6:HAL_TIM_PeriodElapsedCallback	6

Debug/Core/Src/tim.d

@@ -0,0 +1,82 @@
+Core/Src/tim.o: ../Core/Src/tim.c ../Core/Inc/tim.h ../Core/Inc/main.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal.h \
+ ../Core/Inc/stm32f4xx_hal_conf.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h \
+ ../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h \
+ ../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f405xx.h \
+ ../Drivers/CMSIS/Include/core_cm4.h \
+ ../Drivers/CMSIS/Include/cmsis_version.h \
+ ../Drivers/CMSIS/Include/cmsis_compiler.h \
+ ../Drivers/CMSIS/Include/cmsis_gcc.h \
+ ../Drivers/CMSIS/Include/mpu_armv7.h \
+ ../Drivers/CMSIS/Device/ST/STM32F4xx/Include/system_stm32f4xx.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc_ex.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio_ex.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_exti.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma_ex.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cortex.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_can.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ex.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr_ex.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim_ex.h \
+ ../Core/Inc/can.h \
+ D:/ODrive_STM32F405/stm32F405_bootloader/stm32f405_boot/Core/can_tp/UDS.h \
+ D:/ODrive_STM32F405/stm32F405_bootloader/stm32f405_boot/Core/can_tp/i15765.h \
+ D:/ODrive_STM32F405/stm32F405_bootloader/stm32f405_boot/Core/can_tp/i15765sid_function.h \
+ D:/ODrive_STM32F405/stm32F405_bootloader/stm32f405_boot/Core/can_tp/i15765app.h \
+ D:/ODrive_STM32F405/stm32F405_bootloader/stm32f405_boot/Core/can_tp/hal_stdtypes.h \
+ D:/ODrive_STM32F405/stm32F405_bootloader/stm32f405_boot/Core/can_tp/MCU_CAN.h \
+ ../Core/Inc/stm32f4xx_board.h \
+ D:/ODrive_STM32F405/stm32F405_bootloader/stm32f405_boot/Core/can_tp/bits.h \
+ D:/ODrive_STM32F405/stm32F405_bootloader/stm32f405_boot/Core/can_tp/CRC32.h \
+ ../Core/Inc/flash.h ../Core/Inc/stm32f4xx_board.h
+../Core/Inc/tim.h:
+../Core/Inc/main.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal.h:
+../Core/Inc/stm32f4xx_hal_conf.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h:
+../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h:
+../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f405xx.h:
+../Drivers/CMSIS/Include/core_cm4.h:
+../Drivers/CMSIS/Include/cmsis_version.h:
+../Drivers/CMSIS/Include/cmsis_compiler.h:
+../Drivers/CMSIS/Include/cmsis_gcc.h:
+../Drivers/CMSIS/Include/mpu_armv7.h:
+../Drivers/CMSIS/Device/ST/STM32F4xx/Include/system_stm32f4xx.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc_ex.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio_ex.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_exti.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma_ex.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cortex.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_can.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ex.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr_ex.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim_ex.h:
+../Core/Inc/can.h:
+D:/ODrive_STM32F405/stm32F405_bootloader/stm32f405_boot/Core/can_tp/UDS.h:
+D:/ODrive_STM32F405/stm32F405_bootloader/stm32f405_boot/Core/can_tp/i15765.h:
+D:/ODrive_STM32F405/stm32F405_bootloader/stm32f405_boot/Core/can_tp/i15765sid_function.h:
+D:/ODrive_STM32F405/stm32F405_bootloader/stm32f405_boot/Core/can_tp/i15765app.h:
+D:/ODrive_STM32F405/stm32F405_bootloader/stm32f405_boot/Core/can_tp/hal_stdtypes.h:
+D:/ODrive_STM32F405/stm32F405_bootloader/stm32f405_boot/Core/can_tp/MCU_CAN.h:
+../Core/Inc/stm32f4xx_board.h:
+D:/ODrive_STM32F405/stm32F405_bootloader/stm32f405_boot/Core/can_tp/bits.h:
+D:/ODrive_STM32F405/stm32F405_bootloader/stm32f405_boot/Core/can_tp/CRC32.h:
+../Core/Inc/flash.h:
+../Core/Inc/stm32f4xx_board.h:

Debug/Core/Src/tim.su

@@ -0,0 +1,4 @@
+../Core/Src/tim.c:32:6:MX_TIM2_Init	32	static
+../Core/Src/tim.c:72:6:HAL_TIM_Base_MspInit	24	static
+../Core/Src/tim.c:92:6:HAL_TIM_Base_MspDeInit	16	static
+../Core/Src/tim.c:117:6:HAL_TIM_PeriodElapsedCallback	32	static

Debug/Core/Startup/startup_stm32f405rgtx.d

@@ -0,0 +1,2 @@
+Core/Startup/startup_stm32f405rgtx.o: \
+ ../Core/Startup/startup_stm32f405rgtx.s

Debug/Core/Startup/subdir.mk

@@ -0,0 +1,27 @@
+################################################################################
+# Automatically-generated file. Do not edit!
+# Toolchain: GNU Tools for STM32 (13.3.rel1)
+################################################################################
+
+# Add inputs and outputs from these tool invocations to the build variables 
+S_SRCS += \
+../Core/Startup/startup_stm32f405rgtx.s 
+
+OBJS += \
+./Core/Startup/startup_stm32f405rgtx.o 
+
+S_DEPS += \
+./Core/Startup/startup_stm32f405rgtx.d 
+
+
+# Each subdirectory must supply rules for building sources it contributes
+Core/Startup/%.o: ../Core/Startup/%.s Core/Startup/subdir.mk
+	arm-none-eabi-gcc -mcpu=cortex-m4 -g3 -DDEBUG -c -x assembler-with-cpp -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" --specs=nano.specs -mfpu=fpv4-sp-d16 -mfloat-abi=hard -mthumb -o "$@" "$<"
+
+clean: clean-Core-2f-Startup
+
+clean-Core-2f-Startup:
+	-$(RM) ./Core/Startup/startup_stm32f405rgtx.d ./Core/Startup/startup_stm32f405rgtx.o
+
+.PHONY: clean-Core-2f-Startup
+

Debug/Core/can_tp/CRC32.cyclo

@@ -0,0 +1 @@
+../Core/can_tp/CRC32.c:46:14:crc32	2

Debug/Core/can_tp/CRC32.d

@@ -0,0 +1,2 @@
+Core/can_tp/CRC32.o: ../Core/can_tp/CRC32.c ../Core/can_tp/CRC32.h
+../Core/can_tp/CRC32.h:

Debug/Core/can_tp/CRC32.su

@@ -0,0 +1 @@
+../Core/can_tp/CRC32.c:46:14:crc32	32	static

Debug/Core/can_tp/MCU_CAN.cyclo

@@ -0,0 +1,3 @@
+../Core/can_tp/MCU_CAN.c:29:9:can_rx	3
+../Core/can_tp/MCU_CAN.c:61:6:can_tx_isr_i	3
+../Core/can_tp/MCU_CAN.c:92:6:can_rx_isr_i	4

Debug/Core/can_tp/MCU_CAN.d

@@ -0,0 +1,62 @@
+Core/can_tp/MCU_CAN.o: ../Core/can_tp/MCU_CAN.c ../Core/can_tp/MCU_CAN.h \
+ ../Core/Inc/stm32f4xx_board.h \
+ ../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h \
+ ../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f405xx.h \
+ ../Drivers/CMSIS/Include/core_cm4.h \
+ ../Drivers/CMSIS/Include/cmsis_version.h \
+ ../Drivers/CMSIS/Include/cmsis_compiler.h \
+ ../Drivers/CMSIS/Include/cmsis_gcc.h \
+ ../Drivers/CMSIS/Include/mpu_armv7.h \
+ ../Drivers/CMSIS/Device/ST/STM32F4xx/Include/system_stm32f4xx.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal.h \
+ ../Core/Inc/stm32f4xx_hal_conf.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc_ex.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio_ex.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_exti.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma_ex.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cortex.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_can.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ex.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr_ex.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim_ex.h \
+ ../Core/can_tp/i15765.h
+../Core/can_tp/MCU_CAN.h:
+../Core/Inc/stm32f4xx_board.h:
+../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h:
+../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f405xx.h:
+../Drivers/CMSIS/Include/core_cm4.h:
+../Drivers/CMSIS/Include/cmsis_version.h:
+../Drivers/CMSIS/Include/cmsis_compiler.h:
+../Drivers/CMSIS/Include/cmsis_gcc.h:
+../Drivers/CMSIS/Include/mpu_armv7.h:
+../Drivers/CMSIS/Device/ST/STM32F4xx/Include/system_stm32f4xx.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal.h:
+../Core/Inc/stm32f4xx_hal_conf.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc_ex.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio_ex.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_exti.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma_ex.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cortex.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_can.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ex.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr_ex.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim_ex.h:
+../Core/can_tp/i15765.h:

Debug/Core/can_tp/MCU_CAN.su

@@ -0,0 +1,3 @@
+../Core/can_tp/MCU_CAN.c:29:9:can_rx	24	static
+../Core/can_tp/MCU_CAN.c:61:6:can_tx_isr_i	16	static
+../Core/can_tp/MCU_CAN.c:92:6:can_rx_isr_i	48	static

Debug/Core/can_tp/i15765.cyclo

@@ -0,0 +1,23 @@
+../Core/can_tp/i15765.c:102:9:i15765_ai_cmp	4
+../Core/can_tp/i15765.c:114:6:i15765_init	3
+../Core/can_tp/i15765.c:144:9:i15765_mfrb_get	3
+../Core/can_tp/i15765.c:172:9:i15765_mftb_get	3
+../Core/can_tp/i15765.c:197:6:i15765_mfrb_del	3
+../Core/can_tp/i15765.c:216:6:i15765_mftb_del	4
+../Core/can_tp/i15765.c:249:9:i15765_mftb_seek	3
+../Core/can_tp/i15765.c:276:9:i15765_mfrb_seek	3
+../Core/can_tp/i15765.c:301:9:i15765_tx	3
+../Core/can_tp/i15765.c:333:9:i15765_tx_sf	2
+../Core/can_tp/i15765.c:366:6:i15765_tx_ff	3
+../Core/can_tp/i15765.c:408:6:i15765_tx_cf	6
+../Core/can_tp/i15765.c:491:6:i15765_tx_mf	3
+../Core/can_tp/i15765.c:536:6:i15765_tx_fc	4
+../Core/can_tp/i15765.c:586:6:i15765_rx_sf	3
+../Core/can_tp/i15765.c:608:6:i15765_rx_ff	4
+../Core/can_tp/i15765.c:655:6:i15765_rx_cf	7
+../Core/can_tp/i15765.c:716:6:i15765_rx_fc	10
+../Core/can_tp/i15765.c:788:6:i15765_rx_post	12
+../Core/can_tp/i15765.c:853:6:i15765_tx_app	5
+../Core/can_tp/i15765.c:891:6:i15765_tx_update	5
+../Core/can_tp/i15765.c:935:6:i15765_rx_update	6
+../Core/can_tp/i15765.c:965:6:i15765_update	1

Debug/Core/can_tp/i15765.d

@@ -0,0 +1,63 @@
+Core/can_tp/i15765.o: ../Core/can_tp/i15765.c ../Core/can_tp/MCU_CAN.h \
+ ../Core/Inc/stm32f4xx_board.h \
+ ../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h \
+ ../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f405xx.h \
+ ../Drivers/CMSIS/Include/core_cm4.h \
+ ../Drivers/CMSIS/Include/cmsis_version.h \
+ ../Drivers/CMSIS/Include/cmsis_compiler.h \
+ ../Drivers/CMSIS/Include/cmsis_gcc.h \
+ ../Drivers/CMSIS/Include/mpu_armv7.h \
+ ../Drivers/CMSIS/Device/ST/STM32F4xx/Include/system_stm32f4xx.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal.h \
+ ../Core/Inc/stm32f4xx_hal_conf.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc_ex.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio_ex.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_exti.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma_ex.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cortex.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_can.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ex.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr_ex.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim_ex.h \
+ ../Core/can_tp/i15765.h ../Core/can_tp/bits.h
+../Core/can_tp/MCU_CAN.h:
+../Core/Inc/stm32f4xx_board.h:
+../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h:
+../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f405xx.h:
+../Drivers/CMSIS/Include/core_cm4.h:
+../Drivers/CMSIS/Include/cmsis_version.h:
+../Drivers/CMSIS/Include/cmsis_compiler.h:
+../Drivers/CMSIS/Include/cmsis_gcc.h:
+../Drivers/CMSIS/Include/mpu_armv7.h:
+../Drivers/CMSIS/Device/ST/STM32F4xx/Include/system_stm32f4xx.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal.h:
+../Core/Inc/stm32f4xx_hal_conf.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc_ex.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio_ex.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_exti.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma_ex.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cortex.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_can.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ex.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr_ex.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim_ex.h:
+../Core/can_tp/i15765.h:
+../Core/can_tp/bits.h:

Debug/Core/can_tp/i15765.su

@@ -0,0 +1,23 @@
+../Core/can_tp/i15765.c:102:9:i15765_ai_cmp	16	static
+../Core/can_tp/i15765.c:114:6:i15765_init	16	static
+../Core/can_tp/i15765.c:144:9:i15765_mfrb_get	24	static
+../Core/can_tp/i15765.c:172:9:i15765_mftb_get	24	static
+../Core/can_tp/i15765.c:197:6:i15765_mfrb_del	24	static
+../Core/can_tp/i15765.c:216:6:i15765_mftb_del	24	static
+../Core/can_tp/i15765.c:249:9:i15765_mftb_seek	24	static
+../Core/can_tp/i15765.c:276:9:i15765_mfrb_seek	24	static
+../Core/can_tp/i15765.c:301:9:i15765_tx	56	static
+../Core/can_tp/i15765.c:333:9:i15765_tx_sf	56	static
+../Core/can_tp/i15765.c:366:6:i15765_tx_ff	56	static
+../Core/can_tp/i15765.c:408:6:i15765_tx_cf	64	static
+../Core/can_tp/i15765.c:491:6:i15765_tx_mf	32	static
+../Core/can_tp/i15765.c:536:6:i15765_tx_fc	48	static
+../Core/can_tp/i15765.c:586:6:i15765_rx_sf	16	static
+../Core/can_tp/i15765.c:608:6:i15765_rx_ff	32	static
+../Core/can_tp/i15765.c:655:6:i15765_rx_cf	32	static
+../Core/can_tp/i15765.c:716:6:i15765_rx_fc	24	static
+../Core/can_tp/i15765.c:788:6:i15765_rx_post	40	static
+../Core/can_tp/i15765.c:853:6:i15765_tx_app	16	static
+../Core/can_tp/i15765.c:891:6:i15765_tx_update	16	static
+../Core/can_tp/i15765.c:935:6:i15765_rx_update	32	static
+../Core/can_tp/i15765.c:965:6:i15765_update	8	static

Debug/Core/can_tp/i15765app.cyclo

@@ -0,0 +1,3 @@
+../Core/can_tp/i15765app.c:38:6:i15765app_init	1
+../Core/can_tp/i15765app.c:175:6:i15765app_process	8
+../Core/can_tp/i15765app.c:233:6:check_SID_run	6

Debug/Core/can_tp/i15765app.d

@@ -0,0 +1,73 @@
+Core/can_tp/i15765app.o: ../Core/can_tp/i15765app.c ../Core/can_tp/UDS.h \
+ ../Core/can_tp/i15765.h ../Core/can_tp/i15765sid_function.h \
+ ../Core/can_tp/i15765app.h ../Core/can_tp/hal_stdtypes.h \
+ ../Core/can_tp/MCU_CAN.h ../Core/Inc/stm32f4xx_board.h \
+ ../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h \
+ ../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f405xx.h \
+ ../Drivers/CMSIS/Include/core_cm4.h \
+ ../Drivers/CMSIS/Include/cmsis_version.h \
+ ../Drivers/CMSIS/Include/cmsis_compiler.h \
+ ../Drivers/CMSIS/Include/cmsis_gcc.h \
+ ../Drivers/CMSIS/Include/mpu_armv7.h \
+ ../Drivers/CMSIS/Device/ST/STM32F4xx/Include/system_stm32f4xx.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal.h \
+ ../Core/Inc/stm32f4xx_hal_conf.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc_ex.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio_ex.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_exti.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma_ex.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cortex.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_can.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ex.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr_ex.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim_ex.h \
+ ../Core/can_tp/bits.h ../Core/can_tp/CRC32.h ../Core/Inc/flash.h \
+ ../Core/Inc/stm32f4xx_board.h
+../Core/can_tp/UDS.h:
+../Core/can_tp/i15765.h:
+../Core/can_tp/i15765sid_function.h:
+../Core/can_tp/i15765app.h:
+../Core/can_tp/hal_stdtypes.h:
+../Core/can_tp/MCU_CAN.h:
+../Core/Inc/stm32f4xx_board.h:
+../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h:
+../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f405xx.h:
+../Drivers/CMSIS/Include/core_cm4.h:
+../Drivers/CMSIS/Include/cmsis_version.h:
+../Drivers/CMSIS/Include/cmsis_compiler.h:
+../Drivers/CMSIS/Include/cmsis_gcc.h:
+../Drivers/CMSIS/Include/mpu_armv7.h:
+../Drivers/CMSIS/Device/ST/STM32F4xx/Include/system_stm32f4xx.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal.h:
+../Core/Inc/stm32f4xx_hal_conf.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc_ex.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio_ex.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_exti.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma_ex.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cortex.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_can.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ex.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr_ex.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim_ex.h:
+../Core/can_tp/bits.h:
+../Core/can_tp/CRC32.h:
+../Core/Inc/flash.h:
+../Core/Inc/stm32f4xx_board.h:

Debug/Core/can_tp/i15765app.su

@@ -0,0 +1,3 @@
+../Core/can_tp/i15765app.c:38:6:i15765app_init	4	static
+../Core/can_tp/i15765app.c:175:6:i15765app_process	16	static
+../Core/can_tp/i15765app.c:233:6:check_SID_run	8	static