Freego_MC_BOOT/Debug/stm32f405_boot.list

stm32f405_boot.elf:     file format elf32-littlearm

Sections:
Idx Name          Size      VMA       LMA       File off  Algn
  0 .isr_vector   00000188  08000000  08000000  00001000  2**0
                  CONTENTS, ALLOC, LOAD, READONLY, DATA
  1 .version_info 00000004  08000188  08000188  00001188  2**2
                  CONTENTS, ALLOC, LOAD, READONLY, DATA
  2 .text         00005834  0800018c  0800018c  0000118c  2**2
                  CONTENTS, ALLOC, LOAD, READONLY, CODE
  3 .rodata       00000430  080059c0  080059c0  000069c0  2**2
                  CONTENTS, ALLOC, LOAD, READONLY, DATA
  4 .ARM.extab    00000000  08005df0  08005df0  00007014  2**0
                  CONTENTS, READONLY
  5 .ARM          00000008  08005df0  08005df0  00006df0  2**2
                  CONTENTS, ALLOC, LOAD, READONLY, DATA
  6 .preinit_array 00000000  08005df8  08005df8  00007014  2**0
                  CONTENTS, ALLOC, LOAD, DATA
  7 .init_array   00000004  08005df8  08005df8  00006df8  2**2
                  CONTENTS, ALLOC, LOAD, READONLY, DATA
  8 .fini_array   00000004  08005dfc  08005dfc  00006dfc  2**2
                  CONTENTS, ALLOC, LOAD, READONLY, DATA
  9 .data         00000014  20000000  08005e00  00007000  2**2
                  CONTENTS, ALLOC, LOAD, DATA
 10 .ccmram       00000000  10000000  10000000  00007014  2**0
                  CONTENTS
 11 .bss          00001eac  20000014  20000014  00007014  2**2
                  ALLOC
 12 ._user_heap_stack 00000600  20001ec0  20001ec0  00007014  2**0
                  ALLOC
 13 .ARM.attributes 00000030  00000000  00000000  00007014  2**0
                  CONTENTS, READONLY
 14 .debug_info   0000d684  00000000  00000000  00007044  2**0
                  CONTENTS, READONLY, DEBUGGING, OCTETS
 15 .debug_abbrev 00002875  00000000  00000000  000146c8  2**0
                  CONTENTS, READONLY, DEBUGGING, OCTETS
 16 .debug_aranges 00000d80  00000000  00000000  00016f40  2**3
                  CONTENTS, READONLY, DEBUGGING, OCTETS
 17 .debug_rnglists 00000a4b  00000000  00000000  00017cc0  2**0
                  CONTENTS, READONLY, DEBUGGING, OCTETS
 18 .debug_macro  0002079d  00000000  00000000  0001870b  2**0
                  CONTENTS, READONLY, DEBUGGING, OCTETS
 19 .debug_line   00011046  00000000  00000000  00038ea8  2**0
                  CONTENTS, READONLY, DEBUGGING, OCTETS
 20 .debug_str    000c1a67  00000000  00000000  00049eee  2**0
                  CONTENTS, READONLY, DEBUGGING, OCTETS
 21 .comment      00000043  00000000  00000000  0010b955  2**0
                  CONTENTS, READONLY
 22 .debug_frame  000036d0  00000000  00000000  0010b998  2**2
                  CONTENTS, READONLY, DEBUGGING, OCTETS
 23 .debug_line_str 00000066  00000000  00000000  0010f068  2**0
                  CONTENTS, READONLY, DEBUGGING, OCTETS

Disassembly of section .text:

0800018c <__do_global_dtors_aux>:
 800018c:	b510      	push	{r4, lr}
 800018e:	4c05      	ldr	r4, [pc, #20]	@ (80001a4 <__do_global_dtors_aux+0x18>)
 8000190:	7823      	ldrb	r3, [r4, #0]
 8000192:	b933      	cbnz	r3, 80001a2 <__do_global_dtors_aux+0x16>
 8000194:	4b04      	ldr	r3, [pc, #16]	@ (80001a8 <__do_global_dtors_aux+0x1c>)
 8000196:	b113      	cbz	r3, 800019e <__do_global_dtors_aux+0x12>
 8000198:	4804      	ldr	r0, [pc, #16]	@ (80001ac <__do_global_dtors_aux+0x20>)
 800019a:	f3af 8000 	nop.w
 800019e:	2301      	movs	r3, #1
 80001a0:	7023      	strb	r3, [r4, #0]
 80001a2:	bd10      	pop	{r4, pc}
 80001a4:	20000014 	.word	0x20000014
 80001a8:	00000000 	.word	0x00000000
 80001ac:	080059a8 	.word	0x080059a8

080001b0 <frame_dummy>:
 80001b0:	b508      	push	{r3, lr}
 80001b2:	4b03      	ldr	r3, [pc, #12]	@ (80001c0 <frame_dummy+0x10>)
 80001b4:	b11b      	cbz	r3, 80001be <frame_dummy+0xe>
 80001b6:	4903      	ldr	r1, [pc, #12]	@ (80001c4 <frame_dummy+0x14>)
 80001b8:	4803      	ldr	r0, [pc, #12]	@ (80001c8 <frame_dummy+0x18>)
 80001ba:	f3af 8000 	nop.w
 80001be:	bd08      	pop	{r3, pc}
 80001c0:	00000000 	.word	0x00000000
 80001c4:	20000018 	.word	0x20000018
 80001c8:	080059a8 	.word	0x080059a8

080001cc <__aeabi_uldivmod>:
 80001cc:	b953      	cbnz	r3, 80001e4 <__aeabi_uldivmod+0x18>
 80001ce:	b94a      	cbnz	r2, 80001e4 <__aeabi_uldivmod+0x18>
 80001d0:	2900      	cmp	r1, #0
 80001d2:	bf08      	it	eq
 80001d4:	2800      	cmpeq	r0, #0
 80001d6:	bf1c      	itt	ne
 80001d8:	f04f 31ff 	movne.w	r1, #4294967295
 80001dc:	f04f 30ff 	movne.w	r0, #4294967295
 80001e0:	f000 b988 	b.w	80004f4 <__aeabi_idiv0>
 80001e4:	f1ad 0c08 	sub.w	ip, sp, #8
 80001e8:	e96d ce04 	strd	ip, lr, [sp, #-16]!
 80001ec:	f000 f806 	bl	80001fc <__udivmoddi4>
 80001f0:	f8dd e004 	ldr.w	lr, [sp, #4]
 80001f4:	e9dd 2302 	ldrd	r2, r3, [sp, #8]
 80001f8:	b004      	add	sp, #16
 80001fa:	4770      	bx	lr

080001fc <__udivmoddi4>:
 80001fc:	e92d 47f0 	stmdb	sp!, {r4, r5, r6, r7, r8, r9, sl, lr}
 8000200:	9d08      	ldr	r5, [sp, #32]
 8000202:	468e      	mov	lr, r1
 8000204:	4604      	mov	r4, r0
 8000206:	4688      	mov	r8, r1
 8000208:	2b00      	cmp	r3, #0
 800020a:	d14a      	bne.n	80002a2 <__udivmoddi4+0xa6>
 800020c:	428a      	cmp	r2, r1
 800020e:	4617      	mov	r7, r2
 8000210:	d962      	bls.n	80002d8 <__udivmoddi4+0xdc>
 8000212:	fab2 f682 	clz	r6, r2
 8000216:	b14e      	cbz	r6, 800022c <__udivmoddi4+0x30>
 8000218:	f1c6 0320 	rsb	r3, r6, #32
 800021c:	fa01 f806 	lsl.w	r8, r1, r6
 8000220:	fa20 f303 	lsr.w	r3, r0, r3
 8000224:	40b7      	lsls	r7, r6
 8000226:	ea43 0808 	orr.w	r8, r3, r8
 800022a:	40b4      	lsls	r4, r6
 800022c:	ea4f 4e17 	mov.w	lr, r7, lsr #16
 8000230:	fa1f fc87 	uxth.w	ip, r7
 8000234:	fbb8 f1fe 	udiv	r1, r8, lr
 8000238:	0c23      	lsrs	r3, r4, #16
 800023a:	fb0e 8811 	mls	r8, lr, r1, r8
 800023e:	ea43 4308 	orr.w	r3, r3, r8, lsl #16
 8000242:	fb01 f20c 	mul.w	r2, r1, ip
 8000246:	429a      	cmp	r2, r3
 8000248:	d909      	bls.n	800025e <__udivmoddi4+0x62>
 800024a:	18fb      	adds	r3, r7, r3
 800024c:	f101 30ff 	add.w	r0, r1, #4294967295
 8000250:	f080 80ea 	bcs.w	8000428 <__udivmoddi4+0x22c>
 8000254:	429a      	cmp	r2, r3
 8000256:	f240 80e7 	bls.w	8000428 <__udivmoddi4+0x22c>
 800025a:	3902      	subs	r1, #2
 800025c:	443b      	add	r3, r7
 800025e:	1a9a      	subs	r2, r3, r2
 8000260:	b2a3      	uxth	r3, r4
 8000262:	fbb2 f0fe 	udiv	r0, r2, lr
 8000266:	fb0e 2210 	mls	r2, lr, r0, r2
 800026a:	ea43 4302 	orr.w	r3, r3, r2, lsl #16
 800026e:	fb00 fc0c 	mul.w	ip, r0, ip
 8000272:	459c      	cmp	ip, r3
 8000274:	d909      	bls.n	800028a <__udivmoddi4+0x8e>
 8000276:	18fb      	adds	r3, r7, r3
 8000278:	f100 32ff 	add.w	r2, r0, #4294967295
 800027c:	f080 80d6 	bcs.w	800042c <__udivmoddi4+0x230>
 8000280:	459c      	cmp	ip, r3
 8000282:	f240 80d3 	bls.w	800042c <__udivmoddi4+0x230>
 8000286:	443b      	add	r3, r7
 8000288:	3802      	subs	r0, #2
 800028a:	ea40 4001 	orr.w	r0, r0, r1, lsl #16
 800028e:	eba3 030c 	sub.w	r3, r3, ip
 8000292:	2100      	movs	r1, #0
 8000294:	b11d      	cbz	r5, 800029e <__udivmoddi4+0xa2>
 8000296:	40f3      	lsrs	r3, r6
 8000298:	2200      	movs	r2, #0
 800029a:	e9c5 3200 	strd	r3, r2, [r5]
 800029e:	e8bd 87f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, r9, sl, pc}
 80002a2:	428b      	cmp	r3, r1
 80002a4:	d905      	bls.n	80002b2 <__udivmoddi4+0xb6>
 80002a6:	b10d      	cbz	r5, 80002ac <__udivmoddi4+0xb0>
 80002a8:	e9c5 0100 	strd	r0, r1, [r5]
 80002ac:	2100      	movs	r1, #0
 80002ae:	4608      	mov	r0, r1
 80002b0:	e7f5      	b.n	800029e <__udivmoddi4+0xa2>
 80002b2:	fab3 f183 	clz	r1, r3
 80002b6:	2900      	cmp	r1, #0
 80002b8:	d146      	bne.n	8000348 <__udivmoddi4+0x14c>
 80002ba:	4573      	cmp	r3, lr
 80002bc:	d302      	bcc.n	80002c4 <__udivmoddi4+0xc8>
 80002be:	4282      	cmp	r2, r0
 80002c0:	f200 8105 	bhi.w	80004ce <__udivmoddi4+0x2d2>
 80002c4:	1a84      	subs	r4, r0, r2
 80002c6:	eb6e 0203 	sbc.w	r2, lr, r3
 80002ca:	2001      	movs	r0, #1
 80002cc:	4690      	mov	r8, r2
 80002ce:	2d00      	cmp	r5, #0
 80002d0:	d0e5      	beq.n	800029e <__udivmoddi4+0xa2>
 80002d2:	e9c5 4800 	strd	r4, r8, [r5]
 80002d6:	e7e2      	b.n	800029e <__udivmoddi4+0xa2>
 80002d8:	2a00      	cmp	r2, #0
 80002da:	f000 8090 	beq.w	80003fe <__udivmoddi4+0x202>
 80002de:	fab2 f682 	clz	r6, r2
 80002e2:	2e00      	cmp	r6, #0
 80002e4:	f040 80a4 	bne.w	8000430 <__udivmoddi4+0x234>
 80002e8:	1a8a      	subs	r2, r1, r2
 80002ea:	0c03      	lsrs	r3, r0, #16
 80002ec:	ea4f 4e17 	mov.w	lr, r7, lsr #16
 80002f0:	b280      	uxth	r0, r0
 80002f2:	b2bc      	uxth	r4, r7
 80002f4:	2101      	movs	r1, #1
 80002f6:	fbb2 fcfe 	udiv	ip, r2, lr
 80002fa:	fb0e 221c 	mls	r2, lr, ip, r2
 80002fe:	ea43 4302 	orr.w	r3, r3, r2, lsl #16
 8000302:	fb04 f20c 	mul.w	r2, r4, ip
 8000306:	429a      	cmp	r2, r3
 8000308:	d907      	bls.n	800031a <__udivmoddi4+0x11e>
 800030a:	18fb      	adds	r3, r7, r3
 800030c:	f10c 38ff 	add.w	r8, ip, #4294967295
 8000310:	d202      	bcs.n	8000318 <__udivmoddi4+0x11c>
 8000312:	429a      	cmp	r2, r3
 8000314:	f200 80e0 	bhi.w	80004d8 <__udivmoddi4+0x2dc>
 8000318:	46c4      	mov	ip, r8
 800031a:	1a9b      	subs	r3, r3, r2
 800031c:	fbb3 f2fe 	udiv	r2, r3, lr
 8000320:	fb0e 3312 	mls	r3, lr, r2, r3
 8000324:	ea40 4303 	orr.w	r3, r0, r3, lsl #16
 8000328:	fb02 f404 	mul.w	r4, r2, r4
 800032c:	429c      	cmp	r4, r3
 800032e:	d907      	bls.n	8000340 <__udivmoddi4+0x144>
 8000330:	18fb      	adds	r3, r7, r3
 8000332:	f102 30ff 	add.w	r0, r2, #4294967295
 8000336:	d202      	bcs.n	800033e <__udivmoddi4+0x142>
 8000338:	429c      	cmp	r4, r3
 800033a:	f200 80ca 	bhi.w	80004d2 <__udivmoddi4+0x2d6>
 800033e:	4602      	mov	r2, r0
 8000340:	1b1b      	subs	r3, r3, r4
 8000342:	ea42 400c 	orr.w	r0, r2, ip, lsl #16
 8000346:	e7a5      	b.n	8000294 <__udivmoddi4+0x98>
 8000348:	f1c1 0620 	rsb	r6, r1, #32
 800034c:	408b      	lsls	r3, r1
 800034e:	fa22 f706 	lsr.w	r7, r2, r6
 8000352:	431f      	orrs	r7, r3
 8000354:	fa0e f401 	lsl.w	r4, lr, r1
 8000358:	fa20 f306 	lsr.w	r3, r0, r6
 800035c:	fa2e fe06 	lsr.w	lr, lr, r6
 8000360:	ea4f 4917 	mov.w	r9, r7, lsr #16
 8000364:	4323      	orrs	r3, r4
 8000366:	fa00 f801 	lsl.w	r8, r0, r1
 800036a:	fa1f fc87 	uxth.w	ip, r7
 800036e:	fbbe f0f9 	udiv	r0, lr, r9
 8000372:	0c1c      	lsrs	r4, r3, #16
 8000374:	fb09 ee10 	mls	lr, r9, r0, lr
 8000378:	ea44 440e 	orr.w	r4, r4, lr, lsl #16
 800037c:	fb00 fe0c 	mul.w	lr, r0, ip
 8000380:	45a6      	cmp	lr, r4
 8000382:	fa02 f201 	lsl.w	r2, r2, r1
 8000386:	d909      	bls.n	800039c <__udivmoddi4+0x1a0>
 8000388:	193c      	adds	r4, r7, r4
 800038a:	f100 3aff 	add.w	sl, r0, #4294967295
 800038e:	f080 809c 	bcs.w	80004ca <__udivmoddi4+0x2ce>
 8000392:	45a6      	cmp	lr, r4
 8000394:	f240 8099 	bls.w	80004ca <__udivmoddi4+0x2ce>
 8000398:	3802      	subs	r0, #2
 800039a:	443c      	add	r4, r7
 800039c:	eba4 040e 	sub.w	r4, r4, lr
 80003a0:	fa1f fe83 	uxth.w	lr, r3
 80003a4:	fbb4 f3f9 	udiv	r3, r4, r9
 80003a8:	fb09 4413 	mls	r4, r9, r3, r4
 80003ac:	ea4e 4404 	orr.w	r4, lr, r4, lsl #16
 80003b0:	fb03 fc0c 	mul.w	ip, r3, ip
 80003b4:	45a4      	cmp	ip, r4
 80003b6:	d908      	bls.n	80003ca <__udivmoddi4+0x1ce>
 80003b8:	193c      	adds	r4, r7, r4
 80003ba:	f103 3eff 	add.w	lr, r3, #4294967295
 80003be:	f080 8082 	bcs.w	80004c6 <__udivmoddi4+0x2ca>
 80003c2:	45a4      	cmp	ip, r4
 80003c4:	d97f      	bls.n	80004c6 <__udivmoddi4+0x2ca>
 80003c6:	3b02      	subs	r3, #2
 80003c8:	443c      	add	r4, r7
 80003ca:	ea43 4000 	orr.w	r0, r3, r0, lsl #16
 80003ce:	eba4 040c 	sub.w	r4, r4, ip
 80003d2:	fba0 ec02 	umull	lr, ip, r0, r2
 80003d6:	4564      	cmp	r4, ip
 80003d8:	4673      	mov	r3, lr
 80003da:	46e1      	mov	r9, ip
 80003dc:	d362      	bcc.n	80004a4 <__udivmoddi4+0x2a8>
 80003de:	d05f      	beq.n	80004a0 <__udivmoddi4+0x2a4>
 80003e0:	b15d      	cbz	r5, 80003fa <__udivmoddi4+0x1fe>
 80003e2:	ebb8 0203 	subs.w	r2, r8, r3
 80003e6:	eb64 0409 	sbc.w	r4, r4, r9
 80003ea:	fa04 f606 	lsl.w	r6, r4, r6
 80003ee:	fa22 f301 	lsr.w	r3, r2, r1
 80003f2:	431e      	orrs	r6, r3
 80003f4:	40cc      	lsrs	r4, r1
 80003f6:	e9c5 6400 	strd	r6, r4, [r5]
 80003fa:	2100      	movs	r1, #0
 80003fc:	e74f      	b.n	800029e <__udivmoddi4+0xa2>
 80003fe:	fbb1 fcf2 	udiv	ip, r1, r2
 8000402:	0c01      	lsrs	r1, r0, #16
 8000404:	ea41 410e 	orr.w	r1, r1, lr, lsl #16
 8000408:	b280      	uxth	r0, r0
 800040a:	ea40 4201 	orr.w	r2, r0, r1, lsl #16
 800040e:	463b      	mov	r3, r7
 8000410:	4638      	mov	r0, r7
 8000412:	463c      	mov	r4, r7
 8000414:	46b8      	mov	r8, r7
 8000416:	46be      	mov	lr, r7
 8000418:	2620      	movs	r6, #32
 800041a:	fbb1 f1f7 	udiv	r1, r1, r7
 800041e:	eba2 0208 	sub.w	r2, r2, r8
 8000422:	ea41 410c 	orr.w	r1, r1, ip, lsl #16
 8000426:	e766      	b.n	80002f6 <__udivmoddi4+0xfa>
 8000428:	4601      	mov	r1, r0
 800042a:	e718      	b.n	800025e <__udivmoddi4+0x62>
 800042c:	4610      	mov	r0, r2
 800042e:	e72c      	b.n	800028a <__udivmoddi4+0x8e>
 8000430:	f1c6 0220 	rsb	r2, r6, #32
 8000434:	fa2e f302 	lsr.w	r3, lr, r2
 8000438:	40b7      	lsls	r7, r6
 800043a:	40b1      	lsls	r1, r6
 800043c:	fa20 f202 	lsr.w	r2, r0, r2
 8000440:	ea4f 4e17 	mov.w	lr, r7, lsr #16
 8000444:	430a      	orrs	r2, r1
 8000446:	fbb3 f8fe 	udiv	r8, r3, lr
 800044a:	b2bc      	uxth	r4, r7
 800044c:	fb0e 3318 	mls	r3, lr, r8, r3
 8000450:	0c11      	lsrs	r1, r2, #16
 8000452:	ea41 4103 	orr.w	r1, r1, r3, lsl #16
 8000456:	fb08 f904 	mul.w	r9, r8, r4
 800045a:	40b0      	lsls	r0, r6
 800045c:	4589      	cmp	r9, r1
 800045e:	ea4f 4310 	mov.w	r3, r0, lsr #16
 8000462:	b280      	uxth	r0, r0
 8000464:	d93e      	bls.n	80004e4 <__udivmoddi4+0x2e8>
 8000466:	1879      	adds	r1, r7, r1
 8000468:	f108 3cff 	add.w	ip, r8, #4294967295
 800046c:	d201      	bcs.n	8000472 <__udivmoddi4+0x276>
 800046e:	4589      	cmp	r9, r1
 8000470:	d81f      	bhi.n	80004b2 <__udivmoddi4+0x2b6>
 8000472:	eba1 0109 	sub.w	r1, r1, r9
 8000476:	fbb1 f9fe 	udiv	r9, r1, lr
 800047a:	fb09 f804 	mul.w	r8, r9, r4
 800047e:	fb0e 1119 	mls	r1, lr, r9, r1
 8000482:	b292      	uxth	r2, r2
 8000484:	ea42 4201 	orr.w	r2, r2, r1, lsl #16
 8000488:	4542      	cmp	r2, r8
 800048a:	d229      	bcs.n	80004e0 <__udivmoddi4+0x2e4>
 800048c:	18ba      	adds	r2, r7, r2
 800048e:	f109 31ff 	add.w	r1, r9, #4294967295
 8000492:	d2c4      	bcs.n	800041e <__udivmoddi4+0x222>
 8000494:	4542      	cmp	r2, r8
 8000496:	d2c2      	bcs.n	800041e <__udivmoddi4+0x222>
 8000498:	f1a9 0102 	sub.w	r1, r9, #2
 800049c:	443a      	add	r2, r7
 800049e:	e7be      	b.n	800041e <__udivmoddi4+0x222>
 80004a0:	45f0      	cmp	r8, lr
 80004a2:	d29d      	bcs.n	80003e0 <__udivmoddi4+0x1e4>
 80004a4:	ebbe 0302 	subs.w	r3, lr, r2
 80004a8:	eb6c 0c07 	sbc.w	ip, ip, r7
 80004ac:	3801      	subs	r0, #1
 80004ae:	46e1      	mov	r9, ip
 80004b0:	e796      	b.n	80003e0 <__udivmoddi4+0x1e4>
 80004b2:	eba7 0909 	sub.w	r9, r7, r9
 80004b6:	4449      	add	r1, r9
 80004b8:	f1a8 0c02 	sub.w	ip, r8, #2
 80004bc:	fbb1 f9fe 	udiv	r9, r1, lr
 80004c0:	fb09 f804 	mul.w	r8, r9, r4
 80004c4:	e7db      	b.n	800047e <__udivmoddi4+0x282>
 80004c6:	4673      	mov	r3, lr
 80004c8:	e77f      	b.n	80003ca <__udivmoddi4+0x1ce>
 80004ca:	4650      	mov	r0, sl
 80004cc:	e766      	b.n	800039c <__udivmoddi4+0x1a0>
 80004ce:	4608      	mov	r0, r1
 80004d0:	e6fd      	b.n	80002ce <__udivmoddi4+0xd2>
 80004d2:	443b      	add	r3, r7
 80004d4:	3a02      	subs	r2, #2
 80004d6:	e733      	b.n	8000340 <__udivmoddi4+0x144>
 80004d8:	f1ac 0c02 	sub.w	ip, ip, #2
 80004dc:	443b      	add	r3, r7
 80004de:	e71c      	b.n	800031a <__udivmoddi4+0x11e>
 80004e0:	4649      	mov	r1, r9
 80004e2:	e79c      	b.n	800041e <__udivmoddi4+0x222>
 80004e4:	eba1 0109 	sub.w	r1, r1, r9
 80004e8:	46c4      	mov	ip, r8
 80004ea:	fbb1 f9fe 	udiv	r9, r1, lr
 80004ee:	fb09 f804 	mul.w	r8, r9, r4
 80004f2:	e7c4      	b.n	800047e <__udivmoddi4+0x282>

080004f4 <__aeabi_idiv0>:
 80004f4:	4770      	bx	lr
 80004f6:	bf00      	nop

080004f8 <MX_CAN1_Init>:

CAN_HandleTypeDef hcan1;

/* CAN1 init function */
void MX_CAN1_Init(void)
{
 80004f8:	b580      	push	{r7, lr}
 80004fa:	af00      	add	r7, sp, #0
  /* USER CODE END CAN1_Init 0 */

  /* USER CODE BEGIN CAN1_Init 1 */

  /* USER CODE END CAN1_Init 1 */
  hcan1.Instance = CAN1;
 80004fc:	4b17      	ldr	r3, [pc, #92]	@ (800055c <MX_CAN1_Init+0x64>)
 80004fe:	4a18      	ldr	r2, [pc, #96]	@ (8000560 <MX_CAN1_Init+0x68>)
 8000500:	601a      	str	r2, [r3, #0]
//  hcan1.Init.Prescaler = 12;//250k
  hcan1.Init.Prescaler = 6;//500k
 8000502:	4b16      	ldr	r3, [pc, #88]	@ (800055c <MX_CAN1_Init+0x64>)
 8000504:	2206      	movs	r2, #6
 8000506:	605a      	str	r2, [r3, #4]
//  hcan1.Init.Prescaler = 3;//1000k
  hcan1.Init.Mode = CAN_MODE_NORMAL;
 8000508:	4b14      	ldr	r3, [pc, #80]	@ (800055c <MX_CAN1_Init+0x64>)
 800050a:	2200      	movs	r2, #0
 800050c:	609a      	str	r2, [r3, #8]
  hcan1.Init.SyncJumpWidth = CAN_SJW_1TQ;
 800050e:	4b13      	ldr	r3, [pc, #76]	@ (800055c <MX_CAN1_Init+0x64>)
 8000510:	2200      	movs	r2, #0
 8000512:	60da      	str	r2, [r3, #12]
  hcan1.Init.TimeSeg1 = CAN_BS1_11TQ;
 8000514:	4b11      	ldr	r3, [pc, #68]	@ (800055c <MX_CAN1_Init+0x64>)
 8000516:	f44f 2220 	mov.w	r2, #655360	@ 0xa0000
 800051a:	611a      	str	r2, [r3, #16]
  hcan1.Init.TimeSeg2 = CAN_BS2_2TQ;
 800051c:	4b0f      	ldr	r3, [pc, #60]	@ (800055c <MX_CAN1_Init+0x64>)
 800051e:	f44f 1280 	mov.w	r2, #1048576	@ 0x100000
 8000522:	615a      	str	r2, [r3, #20]
  hcan1.Init.TimeTriggeredMode = DISABLE;
 8000524:	4b0d      	ldr	r3, [pc, #52]	@ (800055c <MX_CAN1_Init+0x64>)
 8000526:	2200      	movs	r2, #0
 8000528:	761a      	strb	r2, [r3, #24]
  hcan1.Init.AutoBusOff = ENABLE;
 800052a:	4b0c      	ldr	r3, [pc, #48]	@ (800055c <MX_CAN1_Init+0x64>)
 800052c:	2201      	movs	r2, #1
 800052e:	765a      	strb	r2, [r3, #25]
  hcan1.Init.AutoWakeUp = ENABLE;
 8000530:	4b0a      	ldr	r3, [pc, #40]	@ (800055c <MX_CAN1_Init+0x64>)
 8000532:	2201      	movs	r2, #1
 8000534:	769a      	strb	r2, [r3, #26]
  hcan1.Init.AutoRetransmission = ENABLE;
 8000536:	4b09      	ldr	r3, [pc, #36]	@ (800055c <MX_CAN1_Init+0x64>)
 8000538:	2201      	movs	r2, #1
 800053a:	76da      	strb	r2, [r3, #27]
  hcan1.Init.ReceiveFifoLocked = DISABLE;
 800053c:	4b07      	ldr	r3, [pc, #28]	@ (800055c <MX_CAN1_Init+0x64>)
 800053e:	2200      	movs	r2, #0
 8000540:	771a      	strb	r2, [r3, #28]
  hcan1.Init.TransmitFifoPriority = DISABLE;
 8000542:	4b06      	ldr	r3, [pc, #24]	@ (800055c <MX_CAN1_Init+0x64>)
 8000544:	2200      	movs	r2, #0
 8000546:	775a      	strb	r2, [r3, #29]
  if (HAL_CAN_Init(&hcan1) != HAL_OK)
 8000548:	4804      	ldr	r0, [pc, #16]	@ (800055c <MX_CAN1_Init+0x64>)
 800054a:	f002 fe09 	bl	8003160 <HAL_CAN_Init>
 800054e:	4603      	mov	r3, r0
 8000550:	2b00      	cmp	r3, #0
 8000552:	d001      	beq.n	8000558 <MX_CAN1_Init+0x60>
  {
    Error_Handler();
 8000554:	f000 fdf6 	bl	8001144 <Error_Handler>
  }
  /* USER CODE BEGIN CAN1_Init 2 */

  /* USER CODE END CAN1_Init 2 */

}
 8000558:	bf00      	nop
 800055a:	bd80      	pop	{r7, pc}
 800055c:	20000064 	.word	0x20000064
 8000560:	40006400 	.word	0x40006400

08000564 <HAL_CAN_MspInit>:

void HAL_CAN_MspInit(CAN_HandleTypeDef* canHandle)
{
 8000564:	b580      	push	{r7, lr}
 8000566:	b08a      	sub	sp, #40	@ 0x28
 8000568:	af00      	add	r7, sp, #0
 800056a:	6078      	str	r0, [r7, #4]

  GPIO_InitTypeDef GPIO_InitStruct = {0};
 800056c:	f107 0314 	add.w	r3, r7, #20
 8000570:	2200      	movs	r2, #0
 8000572:	601a      	str	r2, [r3, #0]
 8000574:	605a      	str	r2, [r3, #4]
 8000576:	609a      	str	r2, [r3, #8]
 8000578:	60da      	str	r2, [r3, #12]
 800057a:	611a      	str	r2, [r3, #16]
  if(canHandle->Instance==CAN1)
 800057c:	687b      	ldr	r3, [r7, #4]
 800057e:	681b      	ldr	r3, [r3, #0]
 8000580:	4a1d      	ldr	r2, [pc, #116]	@ (80005f8 <HAL_CAN_MspInit+0x94>)
 8000582:	4293      	cmp	r3, r2
 8000584:	d134      	bne.n	80005f0 <HAL_CAN_MspInit+0x8c>
  {
  /* USER CODE BEGIN CAN1_MspInit 0 */

  /* USER CODE END CAN1_MspInit 0 */
    /* CAN1 clock enable */
    __HAL_RCC_CAN1_CLK_ENABLE();
 8000586:	2300      	movs	r3, #0
 8000588:	613b      	str	r3, [r7, #16]
 800058a:	4b1c      	ldr	r3, [pc, #112]	@ (80005fc <HAL_CAN_MspInit+0x98>)
 800058c:	6c1b      	ldr	r3, [r3, #64]	@ 0x40
 800058e:	4a1b      	ldr	r2, [pc, #108]	@ (80005fc <HAL_CAN_MspInit+0x98>)
 8000590:	f043 7300 	orr.w	r3, r3, #33554432	@ 0x2000000
 8000594:	6413      	str	r3, [r2, #64]	@ 0x40
 8000596:	4b19      	ldr	r3, [pc, #100]	@ (80005fc <HAL_CAN_MspInit+0x98>)
 8000598:	6c1b      	ldr	r3, [r3, #64]	@ 0x40
 800059a:	f003 7300 	and.w	r3, r3, #33554432	@ 0x2000000
 800059e:	613b      	str	r3, [r7, #16]
 80005a0:	693b      	ldr	r3, [r7, #16]

    __HAL_RCC_GPIOB_CLK_ENABLE();
 80005a2:	2300      	movs	r3, #0
 80005a4:	60fb      	str	r3, [r7, #12]
 80005a6:	4b15      	ldr	r3, [pc, #84]	@ (80005fc <HAL_CAN_MspInit+0x98>)
 80005a8:	6b1b      	ldr	r3, [r3, #48]	@ 0x30
 80005aa:	4a14      	ldr	r2, [pc, #80]	@ (80005fc <HAL_CAN_MspInit+0x98>)
 80005ac:	f043 0302 	orr.w	r3, r3, #2
 80005b0:	6313      	str	r3, [r2, #48]	@ 0x30
 80005b2:	4b12      	ldr	r3, [pc, #72]	@ (80005fc <HAL_CAN_MspInit+0x98>)
 80005b4:	6b1b      	ldr	r3, [r3, #48]	@ 0x30
 80005b6:	f003 0302 	and.w	r3, r3, #2
 80005ba:	60fb      	str	r3, [r7, #12]
 80005bc:	68fb      	ldr	r3, [r7, #12]
    /**CAN1 GPIO Configuration
    PB8     ------> CAN1_RX
    PB9     ------> CAN1_TX
    */
    GPIO_InitStruct.Pin = GPIO_PIN_8|GPIO_PIN_9;
 80005be:	f44f 7340 	mov.w	r3, #768	@ 0x300
 80005c2:	617b      	str	r3, [r7, #20]
    GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
 80005c4:	2302      	movs	r3, #2
 80005c6:	61bb      	str	r3, [r7, #24]
    GPIO_InitStruct.Pull = GPIO_NOPULL;
 80005c8:	2300      	movs	r3, #0
 80005ca:	61fb      	str	r3, [r7, #28]
    GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
 80005cc:	2303      	movs	r3, #3
 80005ce:	623b      	str	r3, [r7, #32]
    GPIO_InitStruct.Alternate = GPIO_AF9_CAN1;
 80005d0:	2309      	movs	r3, #9
 80005d2:	627b      	str	r3, [r7, #36]	@ 0x24
    HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
 80005d4:	f107 0314 	add.w	r3, r7, #20
 80005d8:	4619      	mov	r1, r3
 80005da:	4809      	ldr	r0, [pc, #36]	@ (8000600 <HAL_CAN_MspInit+0x9c>)
 80005dc:	f003 fe3e 	bl	800425c <HAL_GPIO_Init>

    /* CAN1 interrupt Init */
    HAL_NVIC_SetPriority(CAN1_RX0_IRQn, 0, 0);
 80005e0:	2200      	movs	r2, #0
 80005e2:	2100      	movs	r1, #0
 80005e4:	2014      	movs	r0, #20
 80005e6:	f003 fdf4 	bl	80041d2 <HAL_NVIC_SetPriority>
    HAL_NVIC_EnableIRQ(CAN1_RX0_IRQn);
 80005ea:	2014      	movs	r0, #20
 80005ec:	f003 fe0d 	bl	800420a <HAL_NVIC_EnableIRQ>
  /* USER CODE BEGIN CAN1_MspInit 1 */

  /* USER CODE END CAN1_MspInit 1 */
  }
}
 80005f0:	bf00      	nop
 80005f2:	3728      	adds	r7, #40	@ 0x28
 80005f4:	46bd      	mov	sp, r7
 80005f6:	bd80      	pop	{r7, pc}
 80005f8:	40006400 	.word	0x40006400
 80005fc:	40023800 	.word	0x40023800
 8000600:	40020400 	.word	0x40020400

08000604 <HAL_CAN_MspDeInit>:

void HAL_CAN_MspDeInit(CAN_HandleTypeDef* canHandle)
{
 8000604:	b580      	push	{r7, lr}
 8000606:	b082      	sub	sp, #8
 8000608:	af00      	add	r7, sp, #0
 800060a:	6078      	str	r0, [r7, #4]

  if(canHandle->Instance==CAN1)
 800060c:	687b      	ldr	r3, [r7, #4]
 800060e:	681b      	ldr	r3, [r3, #0]
 8000610:	4a0a      	ldr	r2, [pc, #40]	@ (800063c <HAL_CAN_MspDeInit+0x38>)
 8000612:	4293      	cmp	r3, r2
 8000614:	d10d      	bne.n	8000632 <HAL_CAN_MspDeInit+0x2e>
  {
  /* USER CODE BEGIN CAN1_MspDeInit 0 */

  /* USER CODE END CAN1_MspDeInit 0 */
    /* Peripheral clock disable */
    __HAL_RCC_CAN1_CLK_DISABLE();
 8000616:	4b0a      	ldr	r3, [pc, #40]	@ (8000640 <HAL_CAN_MspDeInit+0x3c>)
 8000618:	6c1b      	ldr	r3, [r3, #64]	@ 0x40
 800061a:	4a09      	ldr	r2, [pc, #36]	@ (8000640 <HAL_CAN_MspDeInit+0x3c>)
 800061c:	f023 7300 	bic.w	r3, r3, #33554432	@ 0x2000000
 8000620:	6413      	str	r3, [r2, #64]	@ 0x40

    /**CAN1 GPIO Configuration
    PB8     ------> CAN1_RX
    PB9     ------> CAN1_TX
    */
    HAL_GPIO_DeInit(GPIOB, GPIO_PIN_8|GPIO_PIN_9);
 8000622:	f44f 7140 	mov.w	r1, #768	@ 0x300
 8000626:	4807      	ldr	r0, [pc, #28]	@ (8000644 <HAL_CAN_MspDeInit+0x40>)
 8000628:	f003 ffb4 	bl	8004594 <HAL_GPIO_DeInit>

    /* CAN1 interrupt Deinit */
    HAL_NVIC_DisableIRQ(CAN1_RX0_IRQn);
 800062c:	2014      	movs	r0, #20
 800062e:	f003 fdfa 	bl	8004226 <HAL_NVIC_DisableIRQ>
  /* USER CODE BEGIN CAN1_MspDeInit 1 */

  /* USER CODE END CAN1_MspDeInit 1 */
  }
}
 8000632:	bf00      	nop
 8000634:	3708      	adds	r7, #8
 8000636:	46bd      	mov	sp, r7
 8000638:	bd80      	pop	{r7, pc}
 800063a:	bf00      	nop
 800063c:	40006400 	.word	0x40006400
 8000640:	40023800 	.word	0x40023800
 8000644:	40020400 	.word	0x40020400

08000648 <get_hardware_version>:

/* USER CODE BEGIN 1 */

extern uint8_t app2_crc_flag;//crc校验成功标志位，成功后应答版本号位新的。

uint16_t get_hardware_version(void) {
 8000648:	b480      	push	{r7}
 800064a:	af00      	add	r7, sp, #0
    return *(volatile uint16_t*)(0x08000188);
 800064c:	4b03      	ldr	r3, [pc, #12]	@ (800065c <get_hardware_version+0x14>)
 800064e:	881b      	ldrh	r3, [r3, #0]
 8000650:	b29b      	uxth	r3, r3
}
 8000652:	4618      	mov	r0, r3
 8000654:	46bd      	mov	sp, r7
 8000656:	f85d 7b04 	ldr.w	r7, [sp], #4
 800065a:	4770      	bx	lr
 800065c:	08000188 	.word	0x08000188

08000660 <get_publish_data>:
    {
        return *(volatile uint32_t*)0x0800C188;
    }
}

uint32_t get_publish_data(void) {
 8000660:	b480      	push	{r7}
 8000662:	af00      	add	r7, sp, #0
    if(*(volatile uint32_t*)(0x0800C188+4) == 0xFFFFFFFF)
 8000664:	4b07      	ldr	r3, [pc, #28]	@ (8000684 <get_publish_data+0x24>)
 8000666:	681b      	ldr	r3, [r3, #0]
 8000668:	f1b3 3fff 	cmp.w	r3, #4294967295
 800066c:	d102      	bne.n	8000674 <get_publish_data+0x14>
    {
        return *(volatile uint32_t*)(0x08060188+4);
 800066e:	4b06      	ldr	r3, [pc, #24]	@ (8000688 <get_publish_data+0x28>)
 8000670:	681b      	ldr	r3, [r3, #0]
 8000672:	e001      	b.n	8000678 <get_publish_data+0x18>
    }
    else
    {
        return *(volatile uint32_t*)(0x0800C188+4);
 8000674:	4b03      	ldr	r3, [pc, #12]	@ (8000684 <get_publish_data+0x24>)
 8000676:	681b      	ldr	r3, [r3, #0]
    }
}
 8000678:	4618      	mov	r0, r3
 800067a:	46bd      	mov	sp, r7
 800067c:	f85d 7b04 	ldr.w	r7, [sp], #4
 8000680:	4770      	bx	lr
 8000682:	bf00      	nop
 8000684:	0800c18c 	.word	0x0800c18c
 8000688:	0806018c 	.word	0x0806018c

0800068c <CAN_Filter_config>:

void CAN_Filter_config(void)
{
 800068c:	b580      	push	{r7, lr}
 800068e:	b08a      	sub	sp, #40	@ 0x28
 8000690:	af00      	add	r7, sp, #0
    CAN_FilterTypeDef sFilterConfig;

    /* 配置CAN过滤器 */
    sFilterConfig.FilterBank = 0;                             /* 过滤器0 */
 8000692:	2300      	movs	r3, #0
 8000694:	617b      	str	r3, [r7, #20]
    sFilterConfig.FilterMode = CAN_FILTERMODE_IDMASK;
 8000696:	2300      	movs	r3, #0
 8000698:	61bb      	str	r3, [r7, #24]
    sFilterConfig.FilterScale = CAN_FILTERSCALE_32BIT;
 800069a:	2301      	movs	r3, #1
 800069c:	61fb      	str	r3, [r7, #28]
    sFilterConfig.FilterIdHigh = 0x0000;                      /* 32位ID */
 800069e:	2300      	movs	r3, #0
 80006a0:	603b      	str	r3, [r7, #0]
    sFilterConfig.FilterIdLow = 0x0000;
 80006a2:	2300      	movs	r3, #0
 80006a4:	607b      	str	r3, [r7, #4]
    sFilterConfig.FilterMaskIdHigh = 0x0000;                  /* 32位MASK */
 80006a6:	2300      	movs	r3, #0
 80006a8:	60bb      	str	r3, [r7, #8]
    sFilterConfig.FilterMaskIdLow = 0x0000;
 80006aa:	2300      	movs	r3, #0
 80006ac:	60fb      	str	r3, [r7, #12]
    sFilterConfig.FilterFIFOAssignment = CAN_FILTER_FIFO0;    /* 过滤器0关联到FIFO0 */
 80006ae:	2300      	movs	r3, #0
 80006b0:	613b      	str	r3, [r7, #16]
    sFilterConfig.FilterActivation = CAN_FILTER_ENABLE;       /* 激活滤波器0 */
 80006b2:	2301      	movs	r3, #1
 80006b4:	623b      	str	r3, [r7, #32]
    sFilterConfig.SlaveStartFilterBank = 14;
 80006b6:	230e      	movs	r3, #14
 80006b8:	627b      	str	r3, [r7, #36]	@ 0x24

    /* 过滤器配置 */
    if (HAL_CAN_ConfigFilter(&hcan1, &sFilterConfig) != HAL_OK)
 80006ba:	463b      	mov	r3, r7
 80006bc:	4619      	mov	r1, r3
 80006be:	4809      	ldr	r0, [pc, #36]	@ (80006e4 <CAN_Filter_config+0x58>)
 80006c0:	f002 fe6c 	bl	800339c <HAL_CAN_ConfigFilter>
 80006c4:	4603      	mov	r3, r0
 80006c6:	2b00      	cmp	r3, #0
 80006c8:	d001      	beq.n	80006ce <CAN_Filter_config+0x42>
    {
        Error_Handler();
 80006ca:	f000 fd3b 	bl	8001144 <Error_Handler>
    }
	HAL_CAN_Start(&hcan1);//开启CAN
 80006ce:	4805      	ldr	r0, [pc, #20]	@ (80006e4 <CAN_Filter_config+0x58>)
 80006d0:	f002 ff42 	bl	8003558 <HAL_CAN_Start>
	HAL_CAN_ActivateNotification(&hcan1 ,CAN_IT_RX_FIFO0_MSG_PENDING);//开启CAN的中断
 80006d4:	2102      	movs	r1, #2
 80006d6:	4803      	ldr	r0, [pc, #12]	@ (80006e4 <CAN_Filter_config+0x58>)
 80006d8:	f003 fa26 	bl	8003b28 <HAL_CAN_ActivateNotification>
}
 80006dc:	bf00      	nop
 80006de:	3728      	adds	r7, #40	@ 0x28
 80006e0:	46bd      	mov	sp, r7
 80006e2:	bd80      	pop	{r7, pc}
 80006e4:	20000064 	.word	0x20000064

080006e8 <CAN_SendData>:

void CAN_SendData(uint8_t canCom, uint32_t mailbox, uint32_t messageId, uint8_t * data, uint32_t len)
{
 80006e8:	b580      	push	{r7, lr}
 80006ea:	b086      	sub	sp, #24
 80006ec:	af00      	add	r7, sp, #0
 80006ee:	60b9      	str	r1, [r7, #8]
 80006f0:	607a      	str	r2, [r7, #4]
 80006f2:	603b      	str	r3, [r7, #0]
 80006f4:	4603      	mov	r3, r0
 80006f6:	73fb      	strb	r3, [r7, #15]
	uint32_t start_time = HAL_GetTick();  // 使用系统时间戳，更精确
 80006f8:	f002 fd26 	bl	8003148 <HAL_GetTick>
 80006fc:	6178      	str	r0, [r7, #20]
	uint32_t TxMailbox = CAN_TX_MAILBOX0;
 80006fe:	2301      	movs	r3, #1
 8000700:	613b      	str	r3, [r7, #16]

    TxHeader.StdId = messageId;         /* 标准标识符 */
 8000702:	4a1a      	ldr	r2, [pc, #104]	@ (800076c <CAN_SendData+0x84>)
 8000704:	687b      	ldr	r3, [r7, #4]
 8000706:	6013      	str	r3, [r2, #0]
    TxHeader.ExtId = messageId;         /* 扩展标识符(29位) */
 8000708:	4a18      	ldr	r2, [pc, #96]	@ (800076c <CAN_SendData+0x84>)
 800070a:	687b      	ldr	r3, [r7, #4]
 800070c:	6053      	str	r3, [r2, #4]
    TxHeader.IDE = CAN_ID_EXT;   /* 使用标准帧 or 扩展帧 */
 800070e:	4b17      	ldr	r3, [pc, #92]	@ (800076c <CAN_SendData+0x84>)
 8000710:	2204      	movs	r2, #4
 8000712:	609a      	str	r2, [r3, #8]
    TxHeader.RTR = CAN_RTR_DATA; /* 数据帧 */
 8000714:	4b15      	ldr	r3, [pc, #84]	@ (800076c <CAN_SendData+0x84>)
 8000716:	2200      	movs	r2, #0
 8000718:	60da      	str	r2, [r3, #12]
    if(len > 8)
 800071a:	6a3b      	ldr	r3, [r7, #32]
 800071c:	2b08      	cmp	r3, #8
 800071e:	d901      	bls.n	8000724 <CAN_SendData+0x3c>
    {
    	len=8;
 8000720:	2308      	movs	r3, #8
 8000722:	623b      	str	r3, [r7, #32]
    }
    TxHeader.DLC = len;
 8000724:	4a11      	ldr	r2, [pc, #68]	@ (800076c <CAN_SendData+0x84>)
 8000726:	6a3b      	ldr	r3, [r7, #32]
 8000728:	6113      	str	r3, [r2, #16]

    if (HAL_CAN_AddTxMessage(&hcan1 , &TxHeader, data, &TxMailbox) != HAL_OK) /* 发送消息 */
 800072a:	f107 0310 	add.w	r3, r7, #16
 800072e:	683a      	ldr	r2, [r7, #0]
 8000730:	490e      	ldr	r1, [pc, #56]	@ (800076c <CAN_SendData+0x84>)
 8000732:	480f      	ldr	r0, [pc, #60]	@ (8000770 <CAN_SendData+0x88>)
 8000734:	f002 ff9d 	bl	8003672 <HAL_CAN_AddTxMessage>
    {
        //return 1;
    }

    // 超时时间：100ms
	while (HAL_CAN_IsTxMessagePending(&hcan1, TxMailbox))
 8000738:	e00b      	b.n	8000752 <CAN_SendData+0x6a>
    {
		if (HAL_GetTick() - start_time > 100)  // 100ms超时
 800073a:	f002 fd05 	bl	8003148 <HAL_GetTick>
 800073e:	4602      	mov	r2, r0
 8000740:	697b      	ldr	r3, [r7, #20]
 8000742:	1ad3      	subs	r3, r2, r3
 8000744:	2b64      	cmp	r3, #100	@ 0x64
 8000746:	d904      	bls.n	8000752 <CAN_SendData+0x6a>
        {
            HAL_CAN_AbortTxRequest(&hcan1, TxMailbox);     /* 超时，直接中止邮箱的发送请求 */
 8000748:	693b      	ldr	r3, [r7, #16]
 800074a:	4619      	mov	r1, r3
 800074c:	4808      	ldr	r0, [pc, #32]	@ (8000770 <CAN_SendData+0x88>)
 800074e:	f003 f860 	bl	8003812 <HAL_CAN_AbortTxRequest>
	while (HAL_CAN_IsTxMessagePending(&hcan1, TxMailbox))
 8000752:	693b      	ldr	r3, [r7, #16]
 8000754:	4619      	mov	r1, r3
 8000756:	4806      	ldr	r0, [pc, #24]	@ (8000770 <CAN_SendData+0x88>)
 8000758:	f003 f8a0 	bl	800389c <HAL_CAN_IsTxMessagePending>
 800075c:	4603      	mov	r3, r0
 800075e:	2b00      	cmp	r3, #0
 8000760:	d1eb      	bne.n	800073a <CAN_SendData+0x52>
        }
    }

    //return 0;

}
 8000762:	bf00      	nop
 8000764:	bf00      	nop
 8000766:	3718      	adds	r7, #24
 8000768:	46bd      	mov	sp, r7
 800076a:	bd80      	pop	{r7, pc}
 800076c:	20000030 	.word	0x20000030
 8000770:	20000064 	.word	0x20000064

08000774 <HAL_CAN_RxFifo0MsgPendingCallback>:
/*CAN接收中断函数*/
void HAL_CAN_RxFifo0MsgPendingCallback(CAN_HandleTypeDef *hcan){
 8000774:	b580      	push	{r7, lr}
 8000776:	b08a      	sub	sp, #40	@ 0x28
 8000778:	af02      	add	r7, sp, #8
 800077a:	6078      	str	r0, [r7, #4]
	uint8_t RxData[8];
	if(hcan->Instance == CAN1){
 800077c:	687b      	ldr	r3, [r7, #4]
 800077e:	681b      	ldr	r3, [r3, #0]
 8000780:	4a33      	ldr	r2, [pc, #204]	@ (8000850 <HAL_CAN_RxFifo0MsgPendingCallback+0xdc>)
 8000782:	4293      	cmp	r3, r2
 8000784:	d15f      	bne.n	8000846 <HAL_CAN_RxFifo0MsgPendingCallback+0xd2>
		HAL_CAN_GetRxMessage(&hcan1, CAN_RX_FIFO0, &RxHeader, RxData);
 8000786:	f107 0310 	add.w	r3, r7, #16
 800078a:	4a32      	ldr	r2, [pc, #200]	@ (8000854 <HAL_CAN_RxFifo0MsgPendingCallback+0xe0>)
 800078c:	2100      	movs	r1, #0
 800078e:	4832      	ldr	r0, [pc, #200]	@ (8000858 <HAL_CAN_RxFifo0MsgPendingCallback+0xe4>)
 8000790:	f003 f8a8 	bl	80038e4 <HAL_CAN_GetRxMessage>
		if (RxHeader.ExtId == 0x701 && RxHeader.IDE == CAN_ID_EXT) {
 8000794:	4b2f      	ldr	r3, [pc, #188]	@ (8000854 <HAL_CAN_RxFifo0MsgPendingCallback+0xe0>)
 8000796:	685b      	ldr	r3, [r3, #4]
 8000798:	f240 7201 	movw	r2, #1793	@ 0x701
 800079c:	4293      	cmp	r3, r2
 800079e:	d10d      	bne.n	80007bc <HAL_CAN_RxFifo0MsgPendingCallback+0x48>
 80007a0:	4b2c      	ldr	r3, [pc, #176]	@ (8000854 <HAL_CAN_RxFifo0MsgPendingCallback+0xe0>)
 80007a2:	689b      	ldr	r3, [r3, #8]
 80007a4:	2b04      	cmp	r3, #4
 80007a6:	d109      	bne.n	80007bc <HAL_CAN_RxFifo0MsgPendingCallback+0x48>
			can_rx_isr_i(0,RxHeader.ExtId,RxData, RxHeader.DLC);
 80007a8:	4b2a      	ldr	r3, [pc, #168]	@ (8000854 <HAL_CAN_RxFifo0MsgPendingCallback+0xe0>)
 80007aa:	6859      	ldr	r1, [r3, #4]
 80007ac:	4b29      	ldr	r3, [pc, #164]	@ (8000854 <HAL_CAN_RxFifo0MsgPendingCallback+0xe0>)
 80007ae:	691b      	ldr	r3, [r3, #16]
 80007b0:	b2db      	uxtb	r3, r3
 80007b2:	f107 0210 	add.w	r2, r7, #16
 80007b6:	2000      	movs	r0, #0
 80007b8:	f000 febe 	bl	8001538 <can_rx_isr_i>
			//can_rx_isr_i(0,,id,data,len);
		}
		//读取版本号
		if (RxHeader.ExtId == 0x21D && RxHeader.IDE == CAN_ID_EXT) {
 80007bc:	4b25      	ldr	r3, [pc, #148]	@ (8000854 <HAL_CAN_RxFifo0MsgPendingCallback+0xe0>)
 80007be:	685b      	ldr	r3, [r3, #4]
 80007c0:	f240 221d 	movw	r2, #541	@ 0x21d
 80007c4:	4293      	cmp	r3, r2
 80007c6:	d13e      	bne.n	8000846 <HAL_CAN_RxFifo0MsgPendingCallback+0xd2>
 80007c8:	4b22      	ldr	r3, [pc, #136]	@ (8000854 <HAL_CAN_RxFifo0MsgPendingCallback+0xe0>)
 80007ca:	689b      	ldr	r3, [r3, #8]
 80007cc:	2b04      	cmp	r3, #4
 80007ce:	d13a      	bne.n	8000846 <HAL_CAN_RxFifo0MsgPendingCallback+0xd2>
		    uint16_t hardware_version = get_hardware_version();
 80007d0:	f7ff ff3a 	bl	8000648 <get_hardware_version>
 80007d4:	4603      	mov	r3, r0
 80007d6:	83bb      	strh	r3, [r7, #28]
		    uint16_t software_version;
			if(app2_crc_flag == 1)//crc校验成功标志位，成功后应答版本号位新的。
 80007d8:	4b20      	ldr	r3, [pc, #128]	@ (800085c <HAL_CAN_RxFifo0MsgPendingCallback+0xe8>)
 80007da:	781b      	ldrb	r3, [r3, #0]
 80007dc:	2b01      	cmp	r3, #1
 80007de:	d103      	bne.n	80007e8 <HAL_CAN_RxFifo0MsgPendingCallback+0x74>
			{
				software_version = *(volatile uint32_t*)0x08060188;
 80007e0:	4b1f      	ldr	r3, [pc, #124]	@ (8000860 <HAL_CAN_RxFifo0MsgPendingCallback+0xec>)
 80007e2:	681b      	ldr	r3, [r3, #0]
 80007e4:	83fb      	strh	r3, [r7, #30]
 80007e6:	e002      	b.n	80007ee <HAL_CAN_RxFifo0MsgPendingCallback+0x7a>
			}
			else
			{
				software_version = *(volatile uint32_t*)0x0800C188;
 80007e8:	4b1e      	ldr	r3, [pc, #120]	@ (8000864 <HAL_CAN_RxFifo0MsgPendingCallback+0xf0>)
 80007ea:	681b      	ldr	r3, [r3, #0]
 80007ec:	83fb      	strh	r3, [r7, #30]
			}

		    uint32_t publish_data = get_publish_data();
 80007ee:	f7ff ff37 	bl	8000660 <get_publish_data>
 80007f2:	61b8      	str	r0, [r7, #24]

		    uint8_t version[8];
		    version[0] = hardware_version >> 8;
 80007f4:	8bbb      	ldrh	r3, [r7, #28]
 80007f6:	0a1b      	lsrs	r3, r3, #8
 80007f8:	b29b      	uxth	r3, r3
 80007fa:	b2db      	uxtb	r3, r3
 80007fc:	723b      	strb	r3, [r7, #8]
		    version[1] = hardware_version & 0xFF;
 80007fe:	8bbb      	ldrh	r3, [r7, #28]
 8000800:	b2db      	uxtb	r3, r3
 8000802:	727b      	strb	r3, [r7, #9]
		    version[2] = software_version >> 8;
 8000804:	8bfb      	ldrh	r3, [r7, #30]
 8000806:	0a1b      	lsrs	r3, r3, #8
 8000808:	b29b      	uxth	r3, r3
 800080a:	b2db      	uxtb	r3, r3
 800080c:	72bb      	strb	r3, [r7, #10]
		    version[3] = software_version & 0xFF;
 800080e:	8bfb      	ldrh	r3, [r7, #30]
 8000810:	b2db      	uxtb	r3, r3
 8000812:	72fb      	strb	r3, [r7, #11]
		    version[4] = publish_data >> 24;
 8000814:	69bb      	ldr	r3, [r7, #24]
 8000816:	0e1b      	lsrs	r3, r3, #24
 8000818:	b2db      	uxtb	r3, r3
 800081a:	733b      	strb	r3, [r7, #12]
		    version[5] = publish_data >> 16;
 800081c:	69bb      	ldr	r3, [r7, #24]
 800081e:	0c1b      	lsrs	r3, r3, #16
 8000820:	b2db      	uxtb	r3, r3
 8000822:	737b      	strb	r3, [r7, #13]
		    version[6] = publish_data >> 8;
 8000824:	69bb      	ldr	r3, [r7, #24]
 8000826:	0a1b      	lsrs	r3, r3, #8
 8000828:	b2db      	uxtb	r3, r3
 800082a:	73bb      	strb	r3, [r7, #14]
		    version[7] = publish_data & 0xFF;
 800082c:	69bb      	ldr	r3, [r7, #24]
 800082e:	b2db      	uxtb	r3, r3
 8000830:	73fb      	strb	r3, [r7, #15]
		    CAN_SendData(1, 2, 0x21D, version,8);
 8000832:	f107 0308 	add.w	r3, r7, #8
 8000836:	2208      	movs	r2, #8
 8000838:	9200      	str	r2, [sp, #0]
 800083a:	f240 221d 	movw	r2, #541	@ 0x21d
 800083e:	2102      	movs	r1, #2
 8000840:	2001      	movs	r0, #1
 8000842:	f7ff ff51 	bl	80006e8 <CAN_SendData>
		}
	}
}
 8000846:	bf00      	nop
 8000848:	3720      	adds	r7, #32
 800084a:	46bd      	mov	sp, r7
 800084c:	bd80      	pop	{r7, pc}
 800084e:	bf00      	nop
 8000850:	40006400 	.word	0x40006400
 8000854:	20000048 	.word	0x20000048
 8000858:	20000064 	.word	0x20000064
 800085c:	20001eb8 	.word	0x20001eb8
 8000860:	08060188 	.word	0x08060188
 8000864:	0800c188 	.word	0x0800c188

08000868 <HAL_FLASH_ClearError>:
#if defined(FLASH_FLAG_PGPERR)
        FLASH_FLAG_PGPERR |
#endif
        0;

void HAL_FLASH_ClearError() {
 8000868:	b480      	push	{r7}
 800086a:	af00      	add	r7, sp, #0
    __HAL_FLASH_CLEAR_FLAG(FLASH_ERR_FLAGS);
 800086c:	4b03      	ldr	r3, [pc, #12]	@ (800087c <HAL_FLASH_ClearError+0x14>)
 800086e:	22f3      	movs	r2, #243	@ 0xf3
 8000870:	60da      	str	r2, [r3, #12]
}
 8000872:	bf00      	nop
 8000874:	46bd      	mov	sp, r7
 8000876:	f85d 7b04 	ldr.w	r7, [sp], #4
 800087a:	4770      	bx	lr
 800087c:	40023c00 	.word	0x40023c00

08000880 <_sector_frame_address>:

static uint32_t _sector_frame_address(uint32_t Address)
{
 8000880:	b480      	push	{r7}
 8000882:	b085      	sub	sp, #20
 8000884:	af00      	add	r7, sp, #0
 8000886:	6078      	str	r0, [r7, #4]
  uint32_t sector = 0;
 8000888:	2300      	movs	r3, #0
 800088a:	60fb      	str	r3, [r7, #12]

  if((Address < ADDR_FLASH_SECTOR_1) && (Address >= ADDR_FLASH_SECTOR_0))
 800088c:	687b      	ldr	r3, [r7, #4]
 800088e:	4a40      	ldr	r2, [pc, #256]	@ (8000990 <_sector_frame_address+0x110>)
 8000890:	4293      	cmp	r3, r2
 8000892:	d206      	bcs.n	80008a2 <_sector_frame_address+0x22>
 8000894:	687b      	ldr	r3, [r7, #4]
 8000896:	f1b3 6f00 	cmp.w	r3, #134217728	@ 0x8000000
 800089a:	d302      	bcc.n	80008a2 <_sector_frame_address+0x22>
  {
    sector = FLASH_SECTOR_0;
 800089c:	2300      	movs	r3, #0
 800089e:	60fb      	str	r3, [r7, #12]
 80008a0:	e06f      	b.n	8000982 <_sector_frame_address+0x102>
  }
  else if((Address < ADDR_FLASH_SECTOR_2) && (Address >= ADDR_FLASH_SECTOR_1))
 80008a2:	687b      	ldr	r3, [r7, #4]
 80008a4:	4a3b      	ldr	r2, [pc, #236]	@ (8000994 <_sector_frame_address+0x114>)
 80008a6:	4293      	cmp	r3, r2
 80008a8:	d206      	bcs.n	80008b8 <_sector_frame_address+0x38>
 80008aa:	687b      	ldr	r3, [r7, #4]
 80008ac:	4a38      	ldr	r2, [pc, #224]	@ (8000990 <_sector_frame_address+0x110>)
 80008ae:	4293      	cmp	r3, r2
 80008b0:	d302      	bcc.n	80008b8 <_sector_frame_address+0x38>
  {
    sector = FLASH_SECTOR_1;
 80008b2:	2301      	movs	r3, #1
 80008b4:	60fb      	str	r3, [r7, #12]
 80008b6:	e064      	b.n	8000982 <_sector_frame_address+0x102>
  }
  else if((Address < ADDR_FLASH_SECTOR_3) && (Address >= ADDR_FLASH_SECTOR_2))
 80008b8:	687b      	ldr	r3, [r7, #4]
 80008ba:	4a37      	ldr	r2, [pc, #220]	@ (8000998 <_sector_frame_address+0x118>)
 80008bc:	4293      	cmp	r3, r2
 80008be:	d206      	bcs.n	80008ce <_sector_frame_address+0x4e>
 80008c0:	687b      	ldr	r3, [r7, #4]
 80008c2:	4a34      	ldr	r2, [pc, #208]	@ (8000994 <_sector_frame_address+0x114>)
 80008c4:	4293      	cmp	r3, r2
 80008c6:	d302      	bcc.n	80008ce <_sector_frame_address+0x4e>
  {
    sector = FLASH_SECTOR_2;
 80008c8:	2302      	movs	r3, #2
 80008ca:	60fb      	str	r3, [r7, #12]
 80008cc:	e059      	b.n	8000982 <_sector_frame_address+0x102>
  }
  else if((Address < ADDR_FLASH_SECTOR_4) && (Address >= ADDR_FLASH_SECTOR_3))
 80008ce:	687b      	ldr	r3, [r7, #4]
 80008d0:	4a32      	ldr	r2, [pc, #200]	@ (800099c <_sector_frame_address+0x11c>)
 80008d2:	4293      	cmp	r3, r2
 80008d4:	d806      	bhi.n	80008e4 <_sector_frame_address+0x64>
 80008d6:	687b      	ldr	r3, [r7, #4]
 80008d8:	4a2f      	ldr	r2, [pc, #188]	@ (8000998 <_sector_frame_address+0x118>)
 80008da:	4293      	cmp	r3, r2
 80008dc:	d302      	bcc.n	80008e4 <_sector_frame_address+0x64>
  {
    sector = FLASH_SECTOR_3;
 80008de:	2303      	movs	r3, #3
 80008e0:	60fb      	str	r3, [r7, #12]
 80008e2:	e04e      	b.n	8000982 <_sector_frame_address+0x102>
  }
  else if((Address < ADDR_FLASH_SECTOR_5) && (Address >= ADDR_FLASH_SECTOR_4))
 80008e4:	687b      	ldr	r3, [r7, #4]
 80008e6:	4a2e      	ldr	r2, [pc, #184]	@ (80009a0 <_sector_frame_address+0x120>)
 80008e8:	4293      	cmp	r3, r2
 80008ea:	d806      	bhi.n	80008fa <_sector_frame_address+0x7a>
 80008ec:	687b      	ldr	r3, [r7, #4]
 80008ee:	4a2b      	ldr	r2, [pc, #172]	@ (800099c <_sector_frame_address+0x11c>)
 80008f0:	4293      	cmp	r3, r2
 80008f2:	d902      	bls.n	80008fa <_sector_frame_address+0x7a>
  {
    sector = FLASH_SECTOR_4;
 80008f4:	2304      	movs	r3, #4
 80008f6:	60fb      	str	r3, [r7, #12]
 80008f8:	e043      	b.n	8000982 <_sector_frame_address+0x102>
  }
  else if((Address < ADDR_FLASH_SECTOR_6) && (Address >= ADDR_FLASH_SECTOR_5))
 80008fa:	687b      	ldr	r3, [r7, #4]
 80008fc:	4a29      	ldr	r2, [pc, #164]	@ (80009a4 <_sector_frame_address+0x124>)
 80008fe:	4293      	cmp	r3, r2
 8000900:	d806      	bhi.n	8000910 <_sector_frame_address+0x90>
 8000902:	687b      	ldr	r3, [r7, #4]
 8000904:	4a26      	ldr	r2, [pc, #152]	@ (80009a0 <_sector_frame_address+0x120>)
 8000906:	4293      	cmp	r3, r2
 8000908:	d902      	bls.n	8000910 <_sector_frame_address+0x90>
  {
    sector = FLASH_SECTOR_5;
 800090a:	2305      	movs	r3, #5
 800090c:	60fb      	str	r3, [r7, #12]
 800090e:	e038      	b.n	8000982 <_sector_frame_address+0x102>
  }
  else if((Address < ADDR_FLASH_SECTOR_7) && (Address >= ADDR_FLASH_SECTOR_6))
 8000910:	687b      	ldr	r3, [r7, #4]
 8000912:	4a25      	ldr	r2, [pc, #148]	@ (80009a8 <_sector_frame_address+0x128>)
 8000914:	4293      	cmp	r3, r2
 8000916:	d806      	bhi.n	8000926 <_sector_frame_address+0xa6>
 8000918:	687b      	ldr	r3, [r7, #4]
 800091a:	4a22      	ldr	r2, [pc, #136]	@ (80009a4 <_sector_frame_address+0x124>)
 800091c:	4293      	cmp	r3, r2
 800091e:	d902      	bls.n	8000926 <_sector_frame_address+0xa6>
  {
    sector = FLASH_SECTOR_6;
 8000920:	2306      	movs	r3, #6
 8000922:	60fb      	str	r3, [r7, #12]
 8000924:	e02d      	b.n	8000982 <_sector_frame_address+0x102>
  }
  else if((Address < ADDR_FLASH_SECTOR_8) && (Address >= ADDR_FLASH_SECTOR_7))
 8000926:	687b      	ldr	r3, [r7, #4]
 8000928:	4a20      	ldr	r2, [pc, #128]	@ (80009ac <_sector_frame_address+0x12c>)
 800092a:	4293      	cmp	r3, r2
 800092c:	d806      	bhi.n	800093c <_sector_frame_address+0xbc>
 800092e:	687b      	ldr	r3, [r7, #4]
 8000930:	4a1d      	ldr	r2, [pc, #116]	@ (80009a8 <_sector_frame_address+0x128>)
 8000932:	4293      	cmp	r3, r2
 8000934:	d902      	bls.n	800093c <_sector_frame_address+0xbc>
  {
    sector = FLASH_SECTOR_7;
 8000936:	2307      	movs	r3, #7
 8000938:	60fb      	str	r3, [r7, #12]
 800093a:	e022      	b.n	8000982 <_sector_frame_address+0x102>
  }
  else if((Address < ADDR_FLASH_SECTOR_9) && (Address >= ADDR_FLASH_SECTOR_8))
 800093c:	687b      	ldr	r3, [r7, #4]
 800093e:	4a1c      	ldr	r2, [pc, #112]	@ (80009b0 <_sector_frame_address+0x130>)
 8000940:	4293      	cmp	r3, r2
 8000942:	d806      	bhi.n	8000952 <_sector_frame_address+0xd2>
 8000944:	687b      	ldr	r3, [r7, #4]
 8000946:	4a19      	ldr	r2, [pc, #100]	@ (80009ac <_sector_frame_address+0x12c>)
 8000948:	4293      	cmp	r3, r2
 800094a:	d902      	bls.n	8000952 <_sector_frame_address+0xd2>
  {
    sector = FLASH_SECTOR_8;
 800094c:	2308      	movs	r3, #8
 800094e:	60fb      	str	r3, [r7, #12]
 8000950:	e017      	b.n	8000982 <_sector_frame_address+0x102>
  }
  else if((Address < ADDR_FLASH_SECTOR_10) && (Address >= ADDR_FLASH_SECTOR_9))
 8000952:	687b      	ldr	r3, [r7, #4]
 8000954:	4a17      	ldr	r2, [pc, #92]	@ (80009b4 <_sector_frame_address+0x134>)
 8000956:	4293      	cmp	r3, r2
 8000958:	d806      	bhi.n	8000968 <_sector_frame_address+0xe8>
 800095a:	687b      	ldr	r3, [r7, #4]
 800095c:	4a14      	ldr	r2, [pc, #80]	@ (80009b0 <_sector_frame_address+0x130>)
 800095e:	4293      	cmp	r3, r2
 8000960:	d902      	bls.n	8000968 <_sector_frame_address+0xe8>
  {
    sector = FLASH_SECTOR_9;
 8000962:	2309      	movs	r3, #9
 8000964:	60fb      	str	r3, [r7, #12]
 8000966:	e00c      	b.n	8000982 <_sector_frame_address+0x102>
  }
  else if((Address < ADDR_FLASH_SECTOR_11) && (Address >= ADDR_FLASH_SECTOR_10))
 8000968:	687b      	ldr	r3, [r7, #4]
 800096a:	4a13      	ldr	r2, [pc, #76]	@ (80009b8 <_sector_frame_address+0x138>)
 800096c:	4293      	cmp	r3, r2
 800096e:	d806      	bhi.n	800097e <_sector_frame_address+0xfe>
 8000970:	687b      	ldr	r3, [r7, #4]
 8000972:	4a10      	ldr	r2, [pc, #64]	@ (80009b4 <_sector_frame_address+0x134>)
 8000974:	4293      	cmp	r3, r2
 8000976:	d902      	bls.n	800097e <_sector_frame_address+0xfe>
  {
    sector = FLASH_SECTOR_10;
 8000978:	230a      	movs	r3, #10
 800097a:	60fb      	str	r3, [r7, #12]
 800097c:	e001      	b.n	8000982 <_sector_frame_address+0x102>
  }else {
    sector = FLASH_SECTOR_11;
 800097e:	230b      	movs	r3, #11
 8000980:	60fb      	str	r3, [r7, #12]
  }
  return sector;
 8000982:	68fb      	ldr	r3, [r7, #12]
}
 8000984:	4618      	mov	r0, r3
 8000986:	3714      	adds	r7, #20
 8000988:	46bd      	mov	sp, r7
 800098a:	f85d 7b04 	ldr.w	r7, [sp], #4
 800098e:	4770      	bx	lr
 8000990:	08004000 	.word	0x08004000
 8000994:	08008000 	.word	0x08008000
 8000998:	0800c000 	.word	0x0800c000
 800099c:	0800ffff 	.word	0x0800ffff
 80009a0:	0801ffff 	.word	0x0801ffff
 80009a4:	0803ffff 	.word	0x0803ffff
 80009a8:	0805ffff 	.word	0x0805ffff
 80009ac:	0807ffff 	.word	0x0807ffff
 80009b0:	0809ffff 	.word	0x0809ffff
 80009b4:	080bffff 	.word	0x080bffff
 80009b8:	080dffff 	.word	0x080dffff

080009bc <flash_unlock>:

void flash_unlock(void)
{
 80009bc:	b480      	push	{r7}
 80009be:	af00      	add	r7, sp, #0
    /* Authorize the FLASH Registers access */
    WRITE_REG(FLASH->KEYR, FLASH_KEY1);
 80009c0:	4b05      	ldr	r3, [pc, #20]	@ (80009d8 <flash_unlock+0x1c>)
 80009c2:	4a06      	ldr	r2, [pc, #24]	@ (80009dc <flash_unlock+0x20>)
 80009c4:	605a      	str	r2, [r3, #4]
    WRITE_REG(FLASH->KEYR, FLASH_KEY2);
 80009c6:	4b04      	ldr	r3, [pc, #16]	@ (80009d8 <flash_unlock+0x1c>)
 80009c8:	4a05      	ldr	r2, [pc, #20]	@ (80009e0 <flash_unlock+0x24>)
 80009ca:	605a      	str	r2, [r3, #4]
}
 80009cc:	bf00      	nop
 80009ce:	46bd      	mov	sp, r7
 80009d0:	f85d 7b04 	ldr.w	r7, [sp], #4
 80009d4:	4770      	bx	lr
 80009d6:	bf00      	nop
 80009d8:	40023c00 	.word	0x40023c00
 80009dc:	45670123 	.word	0x45670123
 80009e0:	cdef89ab 	.word	0xcdef89ab

080009e4 <flash_lock>:
/**
  * @brief  Locks the FLASH control register access
  * @retval HAL Status
  */
void flash_lock(void)
{
 80009e4:	b480      	push	{r7}
 80009e6:	af00      	add	r7, sp, #0
  /* Set the LOCK Bit to lock the FLASH Registers access */
  FLASH->CR |= FLASH_CR_LOCK;
 80009e8:	4b05      	ldr	r3, [pc, #20]	@ (8000a00 <flash_lock+0x1c>)
 80009ea:	691b      	ldr	r3, [r3, #16]
 80009ec:	4a04      	ldr	r2, [pc, #16]	@ (8000a00 <flash_lock+0x1c>)
 80009ee:	f043 4300 	orr.w	r3, r3, #2147483648	@ 0x80000000
 80009f2:	6113      	str	r3, [r2, #16]
}
 80009f4:	bf00      	nop
 80009f6:	46bd      	mov	sp, r7
 80009f8:	f85d 7b04 	ldr.w	r7, [sp], #4
 80009fc:	4770      	bx	lr
 80009fe:	bf00      	nop
 8000a00:	40023c00 	.word	0x40023c00

08000a04 <flash_wait_ready>:

void flash_wait_ready(uint32_t Timeout)
{
 8000a04:	b580      	push	{r7, lr}
 8000a06:	b084      	sub	sp, #16
 8000a08:	af00      	add	r7, sp, #0
 8000a0a:	6078      	str	r0, [r7, #4]
  uint32_t tickstart = 0U;
 8000a0c:	2300      	movs	r3, #0
 8000a0e:	60fb      	str	r3, [r7, #12]

  tickstart = HAL_GetTick();
 8000a10:	f002 fb9a 	bl	8003148 <HAL_GetTick>
 8000a14:	60f8      	str	r0, [r7, #12]

  while(__HAL_FLASH_GET_FLAG(FLASH_FLAG_BSY) != RESET)
 8000a16:	e00e      	b.n	8000a36 <flash_wait_ready+0x32>
  {
//  	wdog_reload();
    if(Timeout != HAL_MAX_DELAY)
 8000a18:	687b      	ldr	r3, [r7, #4]
 8000a1a:	f1b3 3fff 	cmp.w	r3, #4294967295
 8000a1e:	d00a      	beq.n	8000a36 <flash_wait_ready+0x32>
    {
      if((Timeout == 0U)||((HAL_GetTick() - tickstart ) > Timeout))
 8000a20:	687b      	ldr	r3, [r7, #4]
 8000a22:	2b00      	cmp	r3, #0
 8000a24:	d017      	beq.n	8000a56 <flash_wait_ready+0x52>
 8000a26:	f002 fb8f 	bl	8003148 <HAL_GetTick>
 8000a2a:	4602      	mov	r2, r0
 8000a2c:	68fb      	ldr	r3, [r7, #12]
 8000a2e:	1ad3      	subs	r3, r2, r3
 8000a30:	687a      	ldr	r2, [r7, #4]
 8000a32:	429a      	cmp	r2, r3
 8000a34:	d30f      	bcc.n	8000a56 <flash_wait_ready+0x52>
  while(__HAL_FLASH_GET_FLAG(FLASH_FLAG_BSY) != RESET)
 8000a36:	4b0a      	ldr	r3, [pc, #40]	@ (8000a60 <flash_wait_ready+0x5c>)
 8000a38:	68db      	ldr	r3, [r3, #12]
 8000a3a:	f403 3380 	and.w	r3, r3, #65536	@ 0x10000
 8000a3e:	2b00      	cmp	r3, #0
 8000a40:	d1ea      	bne.n	8000a18 <flash_wait_ready+0x14>
        return;
      }
    }
  }
  /* Check FLASH End of Operation flag  */
  if (__HAL_FLASH_GET_FLAG(FLASH_FLAG_EOP) != RESET)
 8000a42:	4b07      	ldr	r3, [pc, #28]	@ (8000a60 <flash_wait_ready+0x5c>)
 8000a44:	68db      	ldr	r3, [r3, #12]
 8000a46:	f003 0301 	and.w	r3, r3, #1
 8000a4a:	2b00      	cmp	r3, #0
 8000a4c:	d004      	beq.n	8000a58 <flash_wait_ready+0x54>
  {
    /* Clear FLASH End of Operation pending bit */
    __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP);
 8000a4e:	4b04      	ldr	r3, [pc, #16]	@ (8000a60 <flash_wait_ready+0x5c>)
 8000a50:	2201      	movs	r2, #1
 8000a52:	60da      	str	r2, [r3, #12]
 8000a54:	e000      	b.n	8000a58 <flash_wait_ready+0x54>
        return;
 8000a56:	bf00      	nop
  }
}
 8000a58:	3710      	adds	r7, #16
 8000a5a:	46bd      	mov	sp, r7
 8000a5c:	bd80      	pop	{r7, pc}
 8000a5e:	bf00      	nop
 8000a60:	40023c00 	.word	0x40023c00

08000a64 <flash_erase_sector>:

void flash_erase_sector(uint32_t Sector)
{
 8000a64:	b580      	push	{r7, lr}
 8000a66:	b084      	sub	sp, #16
 8000a68:	af00      	add	r7, sp, #0
 8000a6a:	6078      	str	r0, [r7, #4]
  uint32_t tmp_psize = 0U;
 8000a6c:	2300      	movs	r3, #0
 8000a6e:	60fb      	str	r3, [r7, #12]

  uint8_t VoltageRange = FLASH_VOLTAGE_RANGE_3;
 8000a70:	2302      	movs	r3, #2
 8000a72:	72fb      	strb	r3, [r7, #11]

  if (VoltageRange == FLASH_VOLTAGE_RANGE_1)
 8000a74:	7afb      	ldrb	r3, [r7, #11]
 8000a76:	2b00      	cmp	r3, #0
 8000a78:	d102      	bne.n	8000a80 <flash_erase_sector+0x1c>
  {
    tmp_psize = FLASH_PSIZE_BYTE;
 8000a7a:	2300      	movs	r3, #0
 8000a7c:	60fb      	str	r3, [r7, #12]
 8000a7e:	e010      	b.n	8000aa2 <flash_erase_sector+0x3e>
  }
  else if (VoltageRange == FLASH_VOLTAGE_RANGE_2)
 8000a80:	7afb      	ldrb	r3, [r7, #11]
 8000a82:	2b01      	cmp	r3, #1
 8000a84:	d103      	bne.n	8000a8e <flash_erase_sector+0x2a>
  {
    tmp_psize = FLASH_PSIZE_HALF_WORD;
 8000a86:	f44f 7380 	mov.w	r3, #256	@ 0x100
 8000a8a:	60fb      	str	r3, [r7, #12]
 8000a8c:	e009      	b.n	8000aa2 <flash_erase_sector+0x3e>
  }
  else if (VoltageRange == FLASH_VOLTAGE_RANGE_3)
 8000a8e:	7afb      	ldrb	r3, [r7, #11]
 8000a90:	2b02      	cmp	r3, #2
 8000a92:	d103      	bne.n	8000a9c <flash_erase_sector+0x38>
  {
    tmp_psize = FLASH_PSIZE_WORD;
 8000a94:	f44f 7300 	mov.w	r3, #512	@ 0x200
 8000a98:	60fb      	str	r3, [r7, #12]
 8000a9a:	e002      	b.n	8000aa2 <flash_erase_sector+0x3e>
  }
  else
  {
    tmp_psize = FLASH_PSIZE_DOUBLE_WORD;
 8000a9c:	f44f 7340 	mov.w	r3, #768	@ 0x300
 8000aa0:	60fb      	str	r3, [r7, #12]
  }

  /* Need to add offset of 4 when sector higher than FLASH_SECTOR_11 */
  if (Sector > FLASH_SECTOR_11)
 8000aa2:	687b      	ldr	r3, [r7, #4]
 8000aa4:	2b0b      	cmp	r3, #11
 8000aa6:	d902      	bls.n	8000aae <flash_erase_sector+0x4a>
  {
    Sector += 4U;
 8000aa8:	687b      	ldr	r3, [r7, #4]
 8000aaa:	3304      	adds	r3, #4
 8000aac:	607b      	str	r3, [r7, #4]
  }
  /* If the previous operation is completed, proceed to erase the sector */
  CLEAR_BIT(FLASH->CR, FLASH_CR_PSIZE);
 8000aae:	4b17      	ldr	r3, [pc, #92]	@ (8000b0c <flash_erase_sector+0xa8>)
 8000ab0:	691b      	ldr	r3, [r3, #16]
 8000ab2:	4a16      	ldr	r2, [pc, #88]	@ (8000b0c <flash_erase_sector+0xa8>)
 8000ab4:	f423 7340 	bic.w	r3, r3, #768	@ 0x300
 8000ab8:	6113      	str	r3, [r2, #16]
  FLASH->CR |= tmp_psize;
 8000aba:	4b14      	ldr	r3, [pc, #80]	@ (8000b0c <flash_erase_sector+0xa8>)
 8000abc:	691a      	ldr	r2, [r3, #16]
 8000abe:	4913      	ldr	r1, [pc, #76]	@ (8000b0c <flash_erase_sector+0xa8>)
 8000ac0:	68fb      	ldr	r3, [r7, #12]
 8000ac2:	4313      	orrs	r3, r2
 8000ac4:	610b      	str	r3, [r1, #16]
  CLEAR_BIT(FLASH->CR, FLASH_CR_SNB);
 8000ac6:	4b11      	ldr	r3, [pc, #68]	@ (8000b0c <flash_erase_sector+0xa8>)
 8000ac8:	691b      	ldr	r3, [r3, #16]
 8000aca:	4a10      	ldr	r2, [pc, #64]	@ (8000b0c <flash_erase_sector+0xa8>)
 8000acc:	f023 0378 	bic.w	r3, r3, #120	@ 0x78
 8000ad0:	6113      	str	r3, [r2, #16]
  FLASH->CR |= FLASH_CR_SER | (Sector << FLASH_CR_SNB_Pos);
 8000ad2:	4b0e      	ldr	r3, [pc, #56]	@ (8000b0c <flash_erase_sector+0xa8>)
 8000ad4:	691a      	ldr	r2, [r3, #16]
 8000ad6:	687b      	ldr	r3, [r7, #4]
 8000ad8:	00db      	lsls	r3, r3, #3
 8000ada:	4313      	orrs	r3, r2
 8000adc:	4a0b      	ldr	r2, [pc, #44]	@ (8000b0c <flash_erase_sector+0xa8>)
 8000ade:	f043 0302 	orr.w	r3, r3, #2
 8000ae2:	6113      	str	r3, [r2, #16]
  FLASH->CR |= FLASH_CR_STRT;
 8000ae4:	4b09      	ldr	r3, [pc, #36]	@ (8000b0c <flash_erase_sector+0xa8>)
 8000ae6:	691b      	ldr	r3, [r3, #16]
 8000ae8:	4a08      	ldr	r2, [pc, #32]	@ (8000b0c <flash_erase_sector+0xa8>)
 8000aea:	f443 3380 	orr.w	r3, r3, #65536	@ 0x10000
 8000aee:	6113      	str	r3, [r2, #16]

  flash_wait_ready(2000);
 8000af0:	f44f 60fa 	mov.w	r0, #2000	@ 0x7d0
 8000af4:	f7ff ff86 	bl	8000a04 <flash_wait_ready>

  CLEAR_BIT(FLASH->CR, (FLASH_CR_SER | FLASH_CR_SNB));
 8000af8:	4b04      	ldr	r3, [pc, #16]	@ (8000b0c <flash_erase_sector+0xa8>)
 8000afa:	691b      	ldr	r3, [r3, #16]
 8000afc:	4a03      	ldr	r2, [pc, #12]	@ (8000b0c <flash_erase_sector+0xa8>)
 8000afe:	f023 037a 	bic.w	r3, r3, #122	@ 0x7a
 8000b02:	6113      	str	r3, [r2, #16]
}
 8000b04:	bf00      	nop
 8000b06:	3710      	adds	r7, #16
 8000b08:	46bd      	mov	sp, r7
 8000b0a:	bd80      	pop	{r7, pc}
 8000b0c:	40023c00 	.word	0x40023c00

08000b10 <flash_write_word>:

static void flash_write_word(uint32_t Address, uint32_t Data)
{
 8000b10:	b580      	push	{r7, lr}
 8000b12:	b082      	sub	sp, #8
 8000b14:	af00      	add	r7, sp, #0
 8000b16:	6078      	str	r0, [r7, #4]
 8000b18:	6039      	str	r1, [r7, #0]
  /* If the previous operation is completed, proceed to program the new data */
  CLEAR_BIT(FLASH->CR, FLASH_CR_PSIZE);
 8000b1a:	4b11      	ldr	r3, [pc, #68]	@ (8000b60 <flash_write_word+0x50>)
 8000b1c:	691b      	ldr	r3, [r3, #16]
 8000b1e:	4a10      	ldr	r2, [pc, #64]	@ (8000b60 <flash_write_word+0x50>)
 8000b20:	f423 7340 	bic.w	r3, r3, #768	@ 0x300
 8000b24:	6113      	str	r3, [r2, #16]
  FLASH->CR |= FLASH_PSIZE_WORD;
 8000b26:	4b0e      	ldr	r3, [pc, #56]	@ (8000b60 <flash_write_word+0x50>)
 8000b28:	691b      	ldr	r3, [r3, #16]
 8000b2a:	4a0d      	ldr	r2, [pc, #52]	@ (8000b60 <flash_write_word+0x50>)
 8000b2c:	f443 7300 	orr.w	r3, r3, #512	@ 0x200
 8000b30:	6113      	str	r3, [r2, #16]
  FLASH->CR |= FLASH_CR_PG;
 8000b32:	4b0b      	ldr	r3, [pc, #44]	@ (8000b60 <flash_write_word+0x50>)
 8000b34:	691b      	ldr	r3, [r3, #16]
 8000b36:	4a0a      	ldr	r2, [pc, #40]	@ (8000b60 <flash_write_word+0x50>)
 8000b38:	f043 0301 	orr.w	r3, r3, #1
 8000b3c:	6113      	str	r3, [r2, #16]

  *(__IO uint32_t*)Address = Data;
 8000b3e:	687b      	ldr	r3, [r7, #4]
 8000b40:	683a      	ldr	r2, [r7, #0]
 8000b42:	601a      	str	r2, [r3, #0]

  flash_wait_ready(10);
 8000b44:	200a      	movs	r0, #10
 8000b46:	f7ff ff5d 	bl	8000a04 <flash_wait_ready>

  FLASH->CR &= (~FLASH_CR_PG);
 8000b4a:	4b05      	ldr	r3, [pc, #20]	@ (8000b60 <flash_write_word+0x50>)
 8000b4c:	691b      	ldr	r3, [r3, #16]
 8000b4e:	4a04      	ldr	r2, [pc, #16]	@ (8000b60 <flash_write_word+0x50>)
 8000b50:	f023 0301 	bic.w	r3, r3, #1
 8000b54:	6113      	str	r3, [r2, #16]
}
 8000b56:	bf00      	nop
 8000b58:	3708      	adds	r7, #8
 8000b5a:	46bd      	mov	sp, r7
 8000b5c:	bd80      	pop	{r7, pc}
 8000b5e:	bf00      	nop
 8000b60:	40023c00 	.word	0x40023c00

08000b64 <flash_write_byte>:
//不能用
static void flash_write_byte(uint32_t Address, uint8_t Data)
{
 8000b64:	b580      	push	{r7, lr}
 8000b66:	b082      	sub	sp, #8
 8000b68:	af00      	add	r7, sp, #0
 8000b6a:	6078      	str	r0, [r7, #4]
 8000b6c:	460b      	mov	r3, r1
 8000b6e:	70fb      	strb	r3, [r7, #3]
  /* If the previous operation is completed, proceed to program the new data */
  CLEAR_BIT(FLASH->CR, FLASH_CR_PSIZE);
 8000b70:	4b0f      	ldr	r3, [pc, #60]	@ (8000bb0 <flash_write_byte+0x4c>)
 8000b72:	691b      	ldr	r3, [r3, #16]
 8000b74:	4a0e      	ldr	r2, [pc, #56]	@ (8000bb0 <flash_write_byte+0x4c>)
 8000b76:	f423 7340 	bic.w	r3, r3, #768	@ 0x300
 8000b7a:	6113      	str	r3, [r2, #16]
  FLASH->CR |= FLASH_PSIZE_BYTE;
 8000b7c:	4b0c      	ldr	r3, [pc, #48]	@ (8000bb0 <flash_write_byte+0x4c>)
 8000b7e:	4a0c      	ldr	r2, [pc, #48]	@ (8000bb0 <flash_write_byte+0x4c>)
 8000b80:	691b      	ldr	r3, [r3, #16]
 8000b82:	6113      	str	r3, [r2, #16]
  FLASH->CR |= FLASH_CR_PG;
 8000b84:	4b0a      	ldr	r3, [pc, #40]	@ (8000bb0 <flash_write_byte+0x4c>)
 8000b86:	691b      	ldr	r3, [r3, #16]
 8000b88:	4a09      	ldr	r2, [pc, #36]	@ (8000bb0 <flash_write_byte+0x4c>)
 8000b8a:	f043 0301 	orr.w	r3, r3, #1
 8000b8e:	6113      	str	r3, [r2, #16]

  *(__IO uint8_t*)Address = Data;
 8000b90:	687b      	ldr	r3, [r7, #4]
 8000b92:	78fa      	ldrb	r2, [r7, #3]
 8000b94:	701a      	strb	r2, [r3, #0]

  flash_wait_ready(10);
 8000b96:	200a      	movs	r0, #10
 8000b98:	f7ff ff34 	bl	8000a04 <flash_wait_ready>

  FLASH->CR &= (~FLASH_CR_PG);
 8000b9c:	4b04      	ldr	r3, [pc, #16]	@ (8000bb0 <flash_write_byte+0x4c>)
 8000b9e:	691b      	ldr	r3, [r3, #16]
 8000ba0:	4a03      	ldr	r2, [pc, #12]	@ (8000bb0 <flash_write_byte+0x4c>)
 8000ba2:	f023 0301 	bic.w	r3, r3, #1
 8000ba6:	6113      	str	r3, [r2, #16]
}
 8000ba8:	bf00      	nop
 8000baa:	3708      	adds	r7, #8
 8000bac:	46bd      	mov	sp, r7
 8000bae:	bd80      	pop	{r7, pc}
 8000bb0:	40023c00 	.word	0x40023c00

08000bb4 <flash_erase_page>:

// @brief Erases a flash sector. This sets all bits in the sector to 1.
// The sector's current index is reset to the minimum value (n_reserved).
// @returns 0 on success or a non-zero error code otherwise
int flash_erase_page(uint32_t address) {
 8000bb4:	b580      	push	{r7, lr}
 8000bb6:	b082      	sub	sp, #8
 8000bb8:	af00      	add	r7, sp, #0
 8000bba:	6078      	str	r0, [r7, #4]
//	wdog_reload();
    flash_unlock();
 8000bbc:	f7ff fefe 	bl	80009bc <flash_unlock>
    HAL_FLASH_ClearError();
 8000bc0:	f7ff fe52 	bl	8000868 <HAL_FLASH_ClearError>
    flash_erase_sector(_sector_frame_address(address));
 8000bc4:	6878      	ldr	r0, [r7, #4]
 8000bc6:	f7ff fe5b 	bl	8000880 <_sector_frame_address>
 8000bca:	4603      	mov	r3, r0
 8000bcc:	4618      	mov	r0, r3
 8000bce:	f7ff ff49 	bl	8000a64 <flash_erase_sector>
    flash_lock();
 8000bd2:	f7ff ff07 	bl	80009e4 <flash_lock>
//	wdog_reload();
    return 0;
 8000bd6:	2300      	movs	r3, #0
}
 8000bd8:	4618      	mov	r0, r3
 8000bda:	3708      	adds	r7, #8
 8000bdc:	46bd      	mov	sp, r7
 8000bde:	bd80      	pop	{r7, pc}

08000be0 <flash_erase_app>:
		size -= sectors_size[sector];;
	}
	return 0;
}

int flash_erase_app(uint8_t app_num) {
 8000be0:	b580      	push	{r7, lr}
 8000be2:	b082      	sub	sp, #8
 8000be4:	af00      	add	r7, sp, #0
 8000be6:	4603      	mov	r3, r0
 8000be8:	71fb      	strb	r3, [r7, #7]
	if(app_num == 1) {
 8000bea:	79fb      	ldrb	r3, [r7, #7]
 8000bec:	2b01      	cmp	r3, #1
 8000bee:	d110      	bne.n	8000c12 <flash_erase_app+0x32>
		app_status_set(1,false);
 8000bf0:	2100      	movs	r1, #0
 8000bf2:	2001      	movs	r0, #1
 8000bf4:	f000 f830 	bl	8000c58 <app_status_set>

		//total = 16+64+128+128=336k
		flash_erase_page(ADDR_FLASH_SECTOR_3);//16k
 8000bf8:	4810      	ldr	r0, [pc, #64]	@ (8000c3c <flash_erase_app+0x5c>)
 8000bfa:	f7ff ffdb 	bl	8000bb4 <flash_erase_page>
		flash_erase_page(ADDR_FLASH_SECTOR_4);//64k
 8000bfe:	4810      	ldr	r0, [pc, #64]	@ (8000c40 <flash_erase_app+0x60>)
 8000c00:	f7ff ffd8 	bl	8000bb4 <flash_erase_page>
		flash_erase_page(ADDR_FLASH_SECTOR_5);//128k
 8000c04:	480f      	ldr	r0, [pc, #60]	@ (8000c44 <flash_erase_app+0x64>)
 8000c06:	f7ff ffd5 	bl	8000bb4 <flash_erase_page>
		flash_erase_page(ADDR_FLASH_SECTOR_6);//128k
 8000c0a:	480f      	ldr	r0, [pc, #60]	@ (8000c48 <flash_erase_app+0x68>)
 8000c0c:	f7ff ffd2 	bl	8000bb4 <flash_erase_page>
 8000c10:	e00f      	b.n	8000c32 <flash_erase_app+0x52>
	}
	else if(app_num == 2) {
 8000c12:	79fb      	ldrb	r3, [r7, #7]
 8000c14:	2b02      	cmp	r3, #2
 8000c16:	d10c      	bne.n	8000c32 <flash_erase_app+0x52>
		app_status_set(2,false);
 8000c18:	2100      	movs	r1, #0
 8000c1a:	2002      	movs	r0, #2
 8000c1c:	f000 f81c 	bl	8000c58 <app_status_set>

		//total = 128+128+128=384k
		flash_erase_page(ADDR_FLASH_SECTOR_7);//128k
 8000c20:	480a      	ldr	r0, [pc, #40]	@ (8000c4c <flash_erase_app+0x6c>)
 8000c22:	f7ff ffc7 	bl	8000bb4 <flash_erase_page>
		flash_erase_page(ADDR_FLASH_SECTOR_8);//128k
 8000c26:	480a      	ldr	r0, [pc, #40]	@ (8000c50 <flash_erase_app+0x70>)
 8000c28:	f7ff ffc4 	bl	8000bb4 <flash_erase_page>
		flash_erase_page(ADDR_FLASH_SECTOR_9);//128k
 8000c2c:	4809      	ldr	r0, [pc, #36]	@ (8000c54 <flash_erase_app+0x74>)
 8000c2e:	f7ff ffc1 	bl	8000bb4 <flash_erase_page>
	}
	return 0;
 8000c32:	2300      	movs	r3, #0
}
 8000c34:	4618      	mov	r0, r3
 8000c36:	3708      	adds	r7, #8
 8000c38:	46bd      	mov	sp, r7
 8000c3a:	bd80      	pop	{r7, pc}
 8000c3c:	0800c000 	.word	0x0800c000
 8000c40:	08010000 	.word	0x08010000
 8000c44:	08020000 	.word	0x08020000
 8000c48:	08040000 	.word	0x08040000
 8000c4c:	08060000 	.word	0x08060000
 8000c50:	08080000 	.word	0x08080000
 8000c54:	080a0000 	.word	0x080a0000

08000c58 <app_status_set>:

void app_status_set(uint8_t app_num,bool status) {
 8000c58:	b580      	push	{r7, lr}
 8000c5a:	b084      	sub	sp, #16
 8000c5c:	af00      	add	r7, sp, #0
 8000c5e:	4603      	mov	r3, r0
 8000c60:	460a      	mov	r2, r1
 8000c62:	71fb      	strb	r3, [r7, #7]
 8000c64:	4613      	mov	r3, r2
 8000c66:	71bb      	strb	r3, [r7, #6]
  uint8_t app_ok_flag[2];
  if(app_num == 1) {
 8000c68:	79fb      	ldrb	r3, [r7, #7]
 8000c6a:	2b01      	cmp	r3, #1
 8000c6c:	d110      	bne.n	8000c90 <app_status_set+0x38>
    app_ok_flag[0] = status;
 8000c6e:	79bb      	ldrb	r3, [r7, #6]
 8000c70:	733b      	strb	r3, [r7, #12]
    app_ok_flag[1] = *(volatile uint8_t*)(CONFIG_IAP_INFO_ADDR+1);
 8000c72:	4b13      	ldr	r3, [pc, #76]	@ (8000cc0 <app_status_set+0x68>)
 8000c74:	781b      	ldrb	r3, [r3, #0]
 8000c76:	b2db      	uxtb	r3, r3
 8000c78:	737b      	strb	r3, [r7, #13]
    flash_erase_page(CONFIG_IAP_INFO_ADDR);
 8000c7a:	4812      	ldr	r0, [pc, #72]	@ (8000cc4 <app_status_set+0x6c>)
 8000c7c:	f7ff ff9a 	bl	8000bb4 <flash_erase_page>
    flash_write_page(CONFIG_IAP_INFO_ADDR, app_ok_flag, 2, false);
 8000c80:	f107 010c 	add.w	r1, r7, #12
 8000c84:	2300      	movs	r3, #0
 8000c86:	2202      	movs	r2, #2
 8000c88:	480e      	ldr	r0, [pc, #56]	@ (8000cc4 <app_status_set+0x6c>)
 8000c8a:	f000 f81d 	bl	8000cc8 <flash_write_page>
    app_ok_flag[0] = *(volatile uint8_t*)(CONFIG_IAP_INFO_ADDR);
    app_ok_flag[1] = status;
    flash_erase_page(CONFIG_IAP_INFO_ADDR);
    flash_write_page(CONFIG_IAP_INFO_ADDR, app_ok_flag, 2, false);
  }
}
 8000c8e:	e012      	b.n	8000cb6 <app_status_set+0x5e>
  else if(app_num == 2) {
 8000c90:	79fb      	ldrb	r3, [r7, #7]
 8000c92:	2b02      	cmp	r3, #2
 8000c94:	d10f      	bne.n	8000cb6 <app_status_set+0x5e>
    app_ok_flag[0] = *(volatile uint8_t*)(CONFIG_IAP_INFO_ADDR);
 8000c96:	4b0b      	ldr	r3, [pc, #44]	@ (8000cc4 <app_status_set+0x6c>)
 8000c98:	781b      	ldrb	r3, [r3, #0]
 8000c9a:	b2db      	uxtb	r3, r3
 8000c9c:	733b      	strb	r3, [r7, #12]
    app_ok_flag[1] = status;
 8000c9e:	79bb      	ldrb	r3, [r7, #6]
 8000ca0:	737b      	strb	r3, [r7, #13]
    flash_erase_page(CONFIG_IAP_INFO_ADDR);
 8000ca2:	4808      	ldr	r0, [pc, #32]	@ (8000cc4 <app_status_set+0x6c>)
 8000ca4:	f7ff ff86 	bl	8000bb4 <flash_erase_page>
    flash_write_page(CONFIG_IAP_INFO_ADDR, app_ok_flag, 2, false);
 8000ca8:	f107 010c 	add.w	r1, r7, #12
 8000cac:	2300      	movs	r3, #0
 8000cae:	2202      	movs	r2, #2
 8000cb0:	4804      	ldr	r0, [pc, #16]	@ (8000cc4 <app_status_set+0x6c>)
 8000cb2:	f000 f809 	bl	8000cc8 <flash_write_page>
}
 8000cb6:	bf00      	nop
 8000cb8:	3710      	adds	r7, #16
 8000cba:	46bd      	mov	sp, r7
 8000cbc:	bd80      	pop	{r7, pc}
 8000cbe:	bf00      	nop
 8000cc0:	08008001 	.word	0x08008001
 8000cc4:	08008000 	.word	0x08008000

08000cc8 <flash_write_page>:

int flash_write_page(uint32_t target_addr, uint8_t *data, uint32_t length, bool erase) {
 8000cc8:	b580      	push	{r7, lr}
 8000cca:	b086      	sub	sp, #24
 8000ccc:	af00      	add	r7, sp, #0
 8000cce:	60f8      	str	r0, [r7, #12]
 8000cd0:	60b9      	str	r1, [r7, #8]
 8000cd2:	607a      	str	r2, [r7, #4]
 8000cd4:	70fb      	strb	r3, [r7, #3]
	uint32_t offset = target_addr & 0x3;
 8000cd6:	68fb      	ldr	r3, [r7, #12]
 8000cd8:	f003 0303 	and.w	r3, r3, #3
 8000cdc:	617b      	str	r3, [r7, #20]
    target_addr -= offset;
 8000cde:	68fa      	ldr	r2, [r7, #12]
 8000ce0:	697b      	ldr	r3, [r7, #20]
 8000ce2:	1ad3      	subs	r3, r2, r3
 8000ce4:	60fb      	str	r3, [r7, #12]
    if (erase && flash_erase_page(target_addr) != 0) {
 8000ce6:	78fb      	ldrb	r3, [r7, #3]
 8000ce8:	2b00      	cmp	r3, #0
 8000cea:	d008      	beq.n	8000cfe <flash_write_page+0x36>
 8000cec:	68f8      	ldr	r0, [r7, #12]
 8000cee:	f7ff ff61 	bl	8000bb4 <flash_erase_page>
 8000cf2:	4603      	mov	r3, r0
 8000cf4:	2b00      	cmp	r3, #0
 8000cf6:	d002      	beq.n	8000cfe <flash_write_page+0x36>
        return -1;
 8000cf8:	f04f 33ff 	mov.w	r3, #4294967295
 8000cfc:	e04d      	b.n	8000d9a <flash_write_page+0xd2>
    }
//	wdog_reload();
    flash_unlock();
 8000cfe:	f7ff fe5d 	bl	80009bc <flash_unlock>
    HAL_FLASH_ClearError();
 8000d02:	f7ff fdb1 	bl	8000868 <HAL_FLASH_ClearError>
    // handle unaligned start
    for (; (offset & 0x3) && length; ++data, ++offset, --length) {
 8000d06:	e011      	b.n	8000d2c <flash_write_page+0x64>
        flash_write_byte(target_addr + offset, *data);
 8000d08:	68fa      	ldr	r2, [r7, #12]
 8000d0a:	697b      	ldr	r3, [r7, #20]
 8000d0c:	441a      	add	r2, r3
 8000d0e:	68bb      	ldr	r3, [r7, #8]
 8000d10:	781b      	ldrb	r3, [r3, #0]
 8000d12:	4619      	mov	r1, r3
 8000d14:	4610      	mov	r0, r2
 8000d16:	f7ff ff25 	bl	8000b64 <flash_write_byte>
    for (; (offset & 0x3) && length; ++data, ++offset, --length) {
 8000d1a:	68bb      	ldr	r3, [r7, #8]
 8000d1c:	3301      	adds	r3, #1
 8000d1e:	60bb      	str	r3, [r7, #8]
 8000d20:	697b      	ldr	r3, [r7, #20]
 8000d22:	3301      	adds	r3, #1
 8000d24:	617b      	str	r3, [r7, #20]
 8000d26:	687b      	ldr	r3, [r7, #4]
 8000d28:	3b01      	subs	r3, #1
 8000d2a:	607b      	str	r3, [r7, #4]
 8000d2c:	697b      	ldr	r3, [r7, #20]
 8000d2e:	f003 0303 	and.w	r3, r3, #3
 8000d32:	2b00      	cmp	r3, #0
 8000d34:	d015      	beq.n	8000d62 <flash_write_page+0x9a>
 8000d36:	687b      	ldr	r3, [r7, #4]
 8000d38:	2b00      	cmp	r3, #0
 8000d3a:	d1e5      	bne.n	8000d08 <flash_write_page+0x40>
    }
    // write 32-bit values (64-bit doesn't work)
    for (; length >= 4; data += 4, offset += 4, length -=4) {
 8000d3c:	e011      	b.n	8000d62 <flash_write_page+0x9a>
        flash_write_word(target_addr + offset, *(uint32_t *)data);
 8000d3e:	68fa      	ldr	r2, [r7, #12]
 8000d40:	697b      	ldr	r3, [r7, #20]
 8000d42:	441a      	add	r2, r3
 8000d44:	68bb      	ldr	r3, [r7, #8]
 8000d46:	681b      	ldr	r3, [r3, #0]
 8000d48:	4619      	mov	r1, r3
 8000d4a:	4610      	mov	r0, r2
 8000d4c:	f7ff fee0 	bl	8000b10 <flash_write_word>
    for (; length >= 4; data += 4, offset += 4, length -=4) {
 8000d50:	68bb      	ldr	r3, [r7, #8]
 8000d52:	3304      	adds	r3, #4
 8000d54:	60bb      	str	r3, [r7, #8]
 8000d56:	697b      	ldr	r3, [r7, #20]
 8000d58:	3304      	adds	r3, #4
 8000d5a:	617b      	str	r3, [r7, #20]
 8000d5c:	687b      	ldr	r3, [r7, #4]
 8000d5e:	3b04      	subs	r3, #4
 8000d60:	607b      	str	r3, [r7, #4]
 8000d62:	687b      	ldr	r3, [r7, #4]
 8000d64:	2b03      	cmp	r3, #3
 8000d66:	d8ea      	bhi.n	8000d3e <flash_write_page+0x76>
    }

    // handle unaligned end
    for (; length; ++data, ++offset, --length) {
 8000d68:	e011      	b.n	8000d8e <flash_write_page+0xc6>
        flash_write_byte(target_addr + offset, *data);
 8000d6a:	68fa      	ldr	r2, [r7, #12]
 8000d6c:	697b      	ldr	r3, [r7, #20]
 8000d6e:	441a      	add	r2, r3
 8000d70:	68bb      	ldr	r3, [r7, #8]
 8000d72:	781b      	ldrb	r3, [r3, #0]
 8000d74:	4619      	mov	r1, r3
 8000d76:	4610      	mov	r0, r2
 8000d78:	f7ff fef4 	bl	8000b64 <flash_write_byte>
    for (; length; ++data, ++offset, --length) {
 8000d7c:	68bb      	ldr	r3, [r7, #8]
 8000d7e:	3301      	adds	r3, #1
 8000d80:	60bb      	str	r3, [r7, #8]
 8000d82:	697b      	ldr	r3, [r7, #20]
 8000d84:	3301      	adds	r3, #1
 8000d86:	617b      	str	r3, [r7, #20]
 8000d88:	687b      	ldr	r3, [r7, #4]
 8000d8a:	3b01      	subs	r3, #1
 8000d8c:	607b      	str	r3, [r7, #4]
 8000d8e:	687b      	ldr	r3, [r7, #4]
 8000d90:	2b00      	cmp	r3, #0
 8000d92:	d1ea      	bne.n	8000d6a <flash_write_page+0xa2>
    }

    flash_lock();
 8000d94:	f7ff fe26 	bl	80009e4 <flash_lock>
    return 0;
 8000d98:	2300      	movs	r3, #0
}
 8000d9a:	4618      	mov	r0, r3
 8000d9c:	3718      	adds	r7, #24
 8000d9e:	46bd      	mov	sp, r7
 8000da0:	bd80      	pop	{r7, pc}

08000da2 <app2_copy_to_app1>:
  for (uint32_t i = 0; i < APP2_ADDRESS - APP1_ADDRESS; i++) {
    data[0] = *(volatile uint8_t*)(APP1_ADDRESS + i);
    flash_write_page(APP2_ADDRESS + i, data, 1, false);
  }
}
void app2_copy_to_app1(void) {
 8000da2:	b580      	push	{r7, lr}
 8000da4:	b082      	sub	sp, #8
 8000da6:	af00      	add	r7, sp, #0
  uint8_t data[1];
  //1、擦除APP1的flash和完整性标志位
  flash_erase_app(1);
 8000da8:	2001      	movs	r0, #1
 8000daa:	f7ff ff19 	bl	8000be0 <flash_erase_app>
  //2、从APP2_ADDRESS读出APP2_ADDRESS - APP1_ADDRESS个数据，复制写入到APP1_ADDRESS
  for (uint32_t i = 0; i < APP2_ADDRESS - APP1_ADDRESS; i++) {
 8000dae:	2300      	movs	r3, #0
 8000db0:	607b      	str	r3, [r7, #4]
 8000db2:	e014      	b.n	8000dde <app2_copy_to_app1+0x3c>
    data[0] = *(volatile uint8_t*)(APP2_ADDRESS + i);
 8000db4:	687b      	ldr	r3, [r7, #4]
 8000db6:	f103 6300 	add.w	r3, r3, #134217728	@ 0x8000000
 8000dba:	f503 23c0 	add.w	r3, r3, #393216	@ 0x60000
 8000dbe:	781b      	ldrb	r3, [r3, #0]
 8000dc0:	b2db      	uxtb	r3, r3
 8000dc2:	703b      	strb	r3, [r7, #0]
    flash_write_page(APP1_ADDRESS + i, data, 1, false);
 8000dc4:	687b      	ldr	r3, [r7, #4]
 8000dc6:	f103 6000 	add.w	r0, r3, #134217728	@ 0x8000000
 8000dca:	f500 4040 	add.w	r0, r0, #49152	@ 0xc000
 8000dce:	4639      	mov	r1, r7
 8000dd0:	2300      	movs	r3, #0
 8000dd2:	2201      	movs	r2, #1
 8000dd4:	f7ff ff78 	bl	8000cc8 <flash_write_page>
  for (uint32_t i = 0; i < APP2_ADDRESS - APP1_ADDRESS; i++) {
 8000dd8:	687b      	ldr	r3, [r7, #4]
 8000dda:	3301      	adds	r3, #1
 8000ddc:	607b      	str	r3, [r7, #4]
 8000dde:	687b      	ldr	r3, [r7, #4]
 8000de0:	f5b3 2fa8 	cmp.w	r3, #344064	@ 0x54000
 8000de4:	d3e6      	bcc.n	8000db4 <app2_copy_to_app1+0x12>
  }
}
 8000de6:	bf00      	nop
 8000de8:	bf00      	nop
 8000dea:	3708      	adds	r7, #8
 8000dec:	46bd      	mov	sp, r7
 8000dee:	bd80      	pop	{r7, pc}

08000df0 <jump_to_app>:
    }
}
#endif

void jump_to_app(uint32_t app_addr)
{
 8000df0:	b580      	push	{r7, lr}
 8000df2:	b084      	sub	sp, #16
 8000df4:	af00      	add	r7, sp, #0
 8000df6:	6078      	str	r0, [r7, #4]
  \details Disables IRQ interrupts by setting special-purpose register PRIMASK.
           Can only be executed in Privileged modes.
 */
__STATIC_FORCEINLINE void __disable_irq(void)
{
  __ASM volatile ("cpsid i" : : : "memory");
 8000df8:	b672      	cpsid	i
}
 8000dfa:	bf00      	nop
	__disable_irq();
    // 3. 清除所有中断挂起位（非常重要！）
    for (int i = 0; i < 8; i++) {
 8000dfc:	2300      	movs	r3, #0
 8000dfe:	60fb      	str	r3, [r7, #12]
 8000e00:	e010      	b.n	8000e24 <jump_to_app+0x34>
        NVIC->ICPR[i] = 0xFFFFFFFF;  // 清除挂起
 8000e02:	4a15      	ldr	r2, [pc, #84]	@ (8000e58 <jump_to_app+0x68>)
 8000e04:	68fb      	ldr	r3, [r7, #12]
 8000e06:	3360      	adds	r3, #96	@ 0x60
 8000e08:	f04f 31ff 	mov.w	r1, #4294967295
 8000e0c:	f842 1023 	str.w	r1, [r2, r3, lsl #2]
        NVIC->ICER[i] = 0xFFFFFFFF;  // 禁用中断
 8000e10:	4a11      	ldr	r2, [pc, #68]	@ (8000e58 <jump_to_app+0x68>)
 8000e12:	68fb      	ldr	r3, [r7, #12]
 8000e14:	3320      	adds	r3, #32
 8000e16:	f04f 31ff 	mov.w	r1, #4294967295
 8000e1a:	f842 1023 	str.w	r1, [r2, r3, lsl #2]
    for (int i = 0; i < 8; i++) {
 8000e1e:	68fb      	ldr	r3, [r7, #12]
 8000e20:	3301      	adds	r3, #1
 8000e22:	60fb      	str	r3, [r7, #12]
 8000e24:	68fb      	ldr	r3, [r7, #12]
 8000e26:	2b07      	cmp	r3, #7
 8000e28:	ddeb      	ble.n	8000e02 <jump_to_app+0x12>
    }

	SysTick->CTRL = 0;
 8000e2a:	4b0c      	ldr	r3, [pc, #48]	@ (8000e5c <jump_to_app+0x6c>)
 8000e2c:	2200      	movs	r2, #0
 8000e2e:	601a      	str	r2, [r3, #0]

	HAL_CAN_DeInit(&hcan1);
 8000e30:	480b      	ldr	r0, [pc, #44]	@ (8000e60 <jump_to_app+0x70>)
 8000e32:	f002 fa90 	bl	8003356 <HAL_CAN_DeInit>
	HAL_DeInit();
 8000e36:	f002 f90d 	bl	8003054 <HAL_DeInit>

	__set_MSP(REG32(app_addr));
 8000e3a:	687b      	ldr	r3, [r7, #4]
 8000e3c:	681b      	ldr	r3, [r3, #0]
 8000e3e:	60bb      	str	r3, [r7, #8]
  \details Assigns the given value to the Main Stack Pointer (MSP).
  \param [in]    topOfMainStack  Main Stack Pointer value to set
 */
__STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack)
{
  __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : );
 8000e40:	68bb      	ldr	r3, [r7, #8]
 8000e42:	f383 8808 	msr	MSP, r3
}
 8000e46:	bf00      	nop
//	SCB->VTOR = app_addr;

	((void (*)(void))(REG32(app_addr + 4)))();
 8000e48:	687b      	ldr	r3, [r7, #4]
 8000e4a:	3304      	adds	r3, #4
 8000e4c:	681b      	ldr	r3, [r3, #0]
 8000e4e:	4798      	blx	r3
}
 8000e50:	bf00      	nop
 8000e52:	3710      	adds	r7, #16
 8000e54:	46bd      	mov	sp, r7
 8000e56:	bd80      	pop	{r7, pc}
 8000e58:	e000e100 	.word	0xe000e100
 8000e5c:	e000e010 	.word	0xe000e010
 8000e60:	20000064 	.word	0x20000064

08000e64 <MX_GPIO_Init>:
        * Output
        * EVENT_OUT
        * EXTI
*/
void MX_GPIO_Init(void)
{
 8000e64:	b580      	push	{r7, lr}
 8000e66:	b08a      	sub	sp, #40	@ 0x28
 8000e68:	af00      	add	r7, sp, #0

  GPIO_InitTypeDef GPIO_InitStruct = {0};
 8000e6a:	f107 0314 	add.w	r3, r7, #20
 8000e6e:	2200      	movs	r2, #0
 8000e70:	601a      	str	r2, [r3, #0]
 8000e72:	605a      	str	r2, [r3, #4]
 8000e74:	609a      	str	r2, [r3, #8]
 8000e76:	60da      	str	r2, [r3, #12]
 8000e78:	611a      	str	r2, [r3, #16]

  /* GPIO Ports Clock Enable */
  __HAL_RCC_GPIOH_CLK_ENABLE();
 8000e7a:	2300      	movs	r3, #0
 8000e7c:	613b      	str	r3, [r7, #16]
 8000e7e:	4b39      	ldr	r3, [pc, #228]	@ (8000f64 <MX_GPIO_Init+0x100>)
 8000e80:	6b1b      	ldr	r3, [r3, #48]	@ 0x30
 8000e82:	4a38      	ldr	r2, [pc, #224]	@ (8000f64 <MX_GPIO_Init+0x100>)
 8000e84:	f043 0380 	orr.w	r3, r3, #128	@ 0x80
 8000e88:	6313      	str	r3, [r2, #48]	@ 0x30
 8000e8a:	4b36      	ldr	r3, [pc, #216]	@ (8000f64 <MX_GPIO_Init+0x100>)
 8000e8c:	6b1b      	ldr	r3, [r3, #48]	@ 0x30
 8000e8e:	f003 0380 	and.w	r3, r3, #128	@ 0x80
 8000e92:	613b      	str	r3, [r7, #16]
 8000e94:	693b      	ldr	r3, [r7, #16]
  __HAL_RCC_GPIOA_CLK_ENABLE();
 8000e96:	2300      	movs	r3, #0
 8000e98:	60fb      	str	r3, [r7, #12]
 8000e9a:	4b32      	ldr	r3, [pc, #200]	@ (8000f64 <MX_GPIO_Init+0x100>)
 8000e9c:	6b1b      	ldr	r3, [r3, #48]	@ 0x30
 8000e9e:	4a31      	ldr	r2, [pc, #196]	@ (8000f64 <MX_GPIO_Init+0x100>)
 8000ea0:	f043 0301 	orr.w	r3, r3, #1
 8000ea4:	6313      	str	r3, [r2, #48]	@ 0x30
 8000ea6:	4b2f      	ldr	r3, [pc, #188]	@ (8000f64 <MX_GPIO_Init+0x100>)
 8000ea8:	6b1b      	ldr	r3, [r3, #48]	@ 0x30
 8000eaa:	f003 0301 	and.w	r3, r3, #1
 8000eae:	60fb      	str	r3, [r7, #12]
 8000eb0:	68fb      	ldr	r3, [r7, #12]
  __HAL_RCC_GPIOB_CLK_ENABLE();
 8000eb2:	2300      	movs	r3, #0
 8000eb4:	60bb      	str	r3, [r7, #8]
 8000eb6:	4b2b      	ldr	r3, [pc, #172]	@ (8000f64 <MX_GPIO_Init+0x100>)
 8000eb8:	6b1b      	ldr	r3, [r3, #48]	@ 0x30
 8000eba:	4a2a      	ldr	r2, [pc, #168]	@ (8000f64 <MX_GPIO_Init+0x100>)
 8000ebc:	f043 0302 	orr.w	r3, r3, #2
 8000ec0:	6313      	str	r3, [r2, #48]	@ 0x30
 8000ec2:	4b28      	ldr	r3, [pc, #160]	@ (8000f64 <MX_GPIO_Init+0x100>)
 8000ec4:	6b1b      	ldr	r3, [r3, #48]	@ 0x30
 8000ec6:	f003 0302 	and.w	r3, r3, #2
 8000eca:	60bb      	str	r3, [r7, #8]
 8000ecc:	68bb      	ldr	r3, [r7, #8]
  __HAL_RCC_GPIOC_CLK_ENABLE();
 8000ece:	2300      	movs	r3, #0
 8000ed0:	607b      	str	r3, [r7, #4]
 8000ed2:	4b24      	ldr	r3, [pc, #144]	@ (8000f64 <MX_GPIO_Init+0x100>)
 8000ed4:	6b1b      	ldr	r3, [r3, #48]	@ 0x30
 8000ed6:	4a23      	ldr	r2, [pc, #140]	@ (8000f64 <MX_GPIO_Init+0x100>)
 8000ed8:	f043 0304 	orr.w	r3, r3, #4
 8000edc:	6313      	str	r3, [r2, #48]	@ 0x30
 8000ede:	4b21      	ldr	r3, [pc, #132]	@ (8000f64 <MX_GPIO_Init+0x100>)
 8000ee0:	6b1b      	ldr	r3, [r3, #48]	@ 0x30
 8000ee2:	f003 0304 	and.w	r3, r3, #4
 8000ee6:	607b      	str	r3, [r7, #4]
 8000ee8:	687b      	ldr	r3, [r7, #4]

  /*Configure GPIO pin Output Level */

  /*Configure GPIO pin : PC4  抱闸输出 */
  GPIO_InitStruct.Pin = GPIO_PIN_4;
 8000eea:	2310      	movs	r3, #16
 8000eec:	617b      	str	r3, [r7, #20]
  GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
 8000eee:	2301      	movs	r3, #1
 8000ef0:	61bb      	str	r3, [r7, #24]
  GPIO_InitStruct.Pull = GPIO_NOPULL;
 8000ef2:	2300      	movs	r3, #0
 8000ef4:	61fb      	str	r3, [r7, #28]
  GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
 8000ef6:	2300      	movs	r3, #0
 8000ef8:	623b      	str	r3, [r7, #32]
  HAL_GPIO_Init(GPIOC, &GPIO_InitStruct);
 8000efa:	f107 0314 	add.w	r3, r7, #20
 8000efe:	4619      	mov	r1, r3
 8000f00:	4819      	ldr	r0, [pc, #100]	@ (8000f68 <MX_GPIO_Init+0x104>)
 8000f02:	f003 f9ab 	bl	800425c <HAL_GPIO_Init>

  /*Configure GPIO pin : PB3  抱闸输出*/
  GPIO_InitStruct.Pin = GPIO_PIN_3;
 8000f06:	2308      	movs	r3, #8
 8000f08:	617b      	str	r3, [r7, #20]
  GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
 8000f0a:	2301      	movs	r3, #1
 8000f0c:	61bb      	str	r3, [r7, #24]
  GPIO_InitStruct.Pull = GPIO_NOPULL;
 8000f0e:	2300      	movs	r3, #0
 8000f10:	61fb      	str	r3, [r7, #28]
  GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
 8000f12:	2300      	movs	r3, #0
 8000f14:	623b      	str	r3, [r7, #32]
  HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
 8000f16:	f107 0314 	add.w	r3, r7, #20
 8000f1a:	4619      	mov	r1, r3
 8000f1c:	4813      	ldr	r0, [pc, #76]	@ (8000f6c <MX_GPIO_Init+0x108>)
 8000f1e:	f003 f99d 	bl	800425c <HAL_GPIO_Init>

  /*Configure GPIO pin : PA2  抱闸状态读取 */
  GPIO_InitStruct.Pin = GPIO_PIN_2;
 8000f22:	2304      	movs	r3, #4
 8000f24:	617b      	str	r3, [r7, #20]
  GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
 8000f26:	2300      	movs	r3, #0
 8000f28:	61bb      	str	r3, [r7, #24]
  GPIO_InitStruct.Pull = GPIO_NOPULL;
 8000f2a:	2300      	movs	r3, #0
 8000f2c:	61fb      	str	r3, [r7, #28]
  GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
 8000f2e:	2300      	movs	r3, #0
 8000f30:	623b      	str	r3, [r7, #32]
  HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
 8000f32:	f107 0314 	add.w	r3, r7, #20
 8000f36:	4619      	mov	r1, r3
 8000f38:	480d      	ldr	r0, [pc, #52]	@ (8000f70 <MX_GPIO_Init+0x10c>)
 8000f3a:	f003 f98f 	bl	800425c <HAL_GPIO_Init>

  /*Configure GPIO pin : PA3  抱闸状态读取*/
  GPIO_InitStruct.Pin = GPIO_PIN_3;
 8000f3e:	2308      	movs	r3, #8
 8000f40:	617b      	str	r3, [r7, #20]
  GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
 8000f42:	2300      	movs	r3, #0
 8000f44:	61bb      	str	r3, [r7, #24]
  GPIO_InitStruct.Pull = GPIO_NOPULL;
 8000f46:	2300      	movs	r3, #0
 8000f48:	61fb      	str	r3, [r7, #28]
  GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
 8000f4a:	2300      	movs	r3, #0
 8000f4c:	623b      	str	r3, [r7, #32]
  HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
 8000f4e:	f107 0314 	add.w	r3, r7, #20
 8000f52:	4619      	mov	r1, r3
 8000f54:	4806      	ldr	r0, [pc, #24]	@ (8000f70 <MX_GPIO_Init+0x10c>)
 8000f56:	f003 f981 	bl	800425c <HAL_GPIO_Init>
}
 8000f5a:	bf00      	nop
 8000f5c:	3728      	adds	r7, #40	@ 0x28
 8000f5e:	46bd      	mov	sp, r7
 8000f60:	bd80      	pop	{r7, pc}
 8000f62:	bf00      	nop
 8000f64:	40023800 	.word	0x40023800
 8000f68:	40020800 	.word	0x40020800
 8000f6c:	40020400 	.word	0x40020400
 8000f70:	40020000 	.word	0x40020000

08000f74 <get_app_version>:
    .software_version = 0x0100,  // 示例：V1.01
};

// 获取版本信息的函数
uint32_t get_app_version(uint8_t soft)
{
 8000f74:	b480      	push	{r7}
 8000f76:	b085      	sub	sp, #20
 8000f78:	af00      	add	r7, sp, #0
 8000f7a:	4603      	mov	r3, r0
 8000f7c:	71fb      	strb	r3, [r7, #7]
	uint32_t app1_version = *(volatile uint32_t*)0x0800C188;
 8000f7e:	4b11      	ldr	r3, [pc, #68]	@ (8000fc4 <get_app_version+0x50>)
 8000f80:	681b      	ldr	r3, [r3, #0]
 8000f82:	60fb      	str	r3, [r7, #12]
	uint32_t app2_version = *(volatile uint32_t*)0x08060188;
 8000f84:	4b10      	ldr	r3, [pc, #64]	@ (8000fc8 <get_app_version+0x54>)
 8000f86:	681b      	ldr	r3, [r3, #0]
 8000f88:	60bb      	str	r3, [r7, #8]

	if(app1_version == 0xFFFFFFFF)
 8000f8a:	68fb      	ldr	r3, [r7, #12]
 8000f8c:	f1b3 3fff 	cmp.w	r3, #4294967295
 8000f90:	d101      	bne.n	8000f96 <get_app_version+0x22>
	{
		app1_version = 0;
 8000f92:	2300      	movs	r3, #0
 8000f94:	60fb      	str	r3, [r7, #12]
	}
	if(app2_version == 0xFFFFFFFF)
 8000f96:	68bb      	ldr	r3, [r7, #8]
 8000f98:	f1b3 3fff 	cmp.w	r3, #4294967295
 8000f9c:	d101      	bne.n	8000fa2 <get_app_version+0x2e>
	{
		app2_version = 0;
 8000f9e:	2300      	movs	r3, #0
 8000fa0:	60bb      	str	r3, [r7, #8]
	}

	if(soft == 1)//app1
 8000fa2:	79fb      	ldrb	r3, [r7, #7]
 8000fa4:	2b01      	cmp	r3, #1
 8000fa6:	d101      	bne.n	8000fac <get_app_version+0x38>
	{
        return app1_version;
 8000fa8:	68fb      	ldr	r3, [r7, #12]
 8000faa:	e005      	b.n	8000fb8 <get_app_version+0x44>
	}
	else if(soft == 2)//app2
 8000fac:	79fb      	ldrb	r3, [r7, #7]
 8000fae:	2b02      	cmp	r3, #2
 8000fb0:	d101      	bne.n	8000fb6 <get_app_version+0x42>
	{
        return app2_version;
 8000fb2:	68bb      	ldr	r3, [r7, #8]
 8000fb4:	e000      	b.n	8000fb8 <get_app_version+0x44>
	}
	else
	{
		return 0;
 8000fb6:	2300      	movs	r3, #0
	}
}
 8000fb8:	4618      	mov	r0, r3
 8000fba:	3714      	adds	r7, #20
 8000fbc:	46bd      	mov	sp, r7
 8000fbe:	f85d 7b04 	ldr.w	r7, [sp], #4
 8000fc2:	4770      	bx	lr
 8000fc4:	0800c188 	.word	0x0800c188
 8000fc8:	08060188 	.word	0x08060188

08000fcc <main>:
/**
  * @brief  The application entry point.
  * @retval int
  */
int main(void)
{
 8000fcc:	b580      	push	{r7, lr}
 8000fce:	b082      	sub	sp, #8
 8000fd0:	af00      	add	r7, sp, #0
  /* USER CODE END 1 */

  /* MCU Configuration--------------------------------------------------------*/

  /* Reset of all peripherals, Initializes the Flash interface and the Systick. */
  HAL_Init();
 8000fd2:	f002 f81d 	bl	8003010 <HAL_Init>
  /* USER CODE BEGIN Init */

  /* USER CODE END Init */

  /* Configure the system clock */
  SystemClock_Config();
 8000fd6:	f000 f84b 	bl	8001070 <SystemClock_Config>
  /* USER CODE BEGIN SysInit */

  /* USER CODE END SysInit */

  /* Initialize all configured peripherals */
  MX_GPIO_Init();
 8000fda:	f7ff ff43 	bl	8000e64 <MX_GPIO_Init>
  MX_CAN1_Init();
 8000fde:	f7ff fa8b 	bl	80004f8 <MX_CAN1_Init>
  MX_TIM2_Init();
 8000fe2:	f000 f933 	bl	800124c <MX_TIM2_Init>
  /* USER CODE BEGIN 2 */
  HAL_TIM_Base_Start_IT(&htim2); // 启动定时器中断
 8000fe6:	481c      	ldr	r0, [pc, #112]	@ (8001058 <main+0x8c>)
 8000fe8:	f004 f884 	bl	80050f4 <HAL_TIM_Base_Start_IT>
  CAN_Filter_config();
 8000fec:	f7ff fb4e 	bl	800068c <CAN_Filter_config>
  i15765_init();
 8000ff0:	f000 fb32 	bl	8001658 <i15765_init>
  i15765app_init();
 8000ff4:	f001 f9aa 	bl	800234c <i15765app_init>
//	  app1_copy_to_app2();
//	  app_status_set(2,true);
//  }
#endif

  uint32_t app1_version = get_app_version(1);
 8000ff8:	2001      	movs	r0, #1
 8000ffa:	f7ff ffbb 	bl	8000f74 <get_app_version>
 8000ffe:	6078      	str	r0, [r7, #4]
  uint32_t app2_version = get_app_version(2);
 8001000:	2002      	movs	r0, #2
 8001002:	f7ff ffb7 	bl	8000f74 <get_app_version>
 8001006:	6038      	str	r0, [r7, #0]

  if(1 == *(volatile uint8_t*)(CONFIG_IAP_INFO_ADDR+1))//APP_B is ok
 8001008:	4b14      	ldr	r3, [pc, #80]	@ (800105c <main+0x90>)
 800100a:	781b      	ldrb	r3, [r3, #0]
 800100c:	b2db      	uxtb	r3, r3
 800100e:	2b01      	cmp	r3, #1
 8001010:	d109      	bne.n	8001026 <main+0x5a>
  {
	  if(app1_version < app2_version)
 8001012:	687a      	ldr	r2, [r7, #4]
 8001014:	683b      	ldr	r3, [r7, #0]
 8001016:	429a      	cmp	r2, r3
 8001018:	d205      	bcs.n	8001026 <main+0x5a>
	  {
		app2_copy_to_app1();
 800101a:	f7ff fec2 	bl	8000da2 <app2_copy_to_app1>
		//flash_erase_app(1);
		app_status_set(1,true);
 800101e:	2101      	movs	r1, #1
 8001020:	2001      	movs	r0, #1
 8001022:	f7ff fe19 	bl	8000c58 <app_status_set>
  while (1)
  {
    /* USER CODE END WHILE */

    /* USER CODE BEGIN 3 */
	  check_SID_run();
 8001026:	f001 fa43 	bl	80024b0 <check_SID_run>

	  //if((system_time_ms == WAIT_OTA_TIME_MS)&&(1))//复位后判断是否从APP跳转过来，不是的话直接跳到APP
	  if(system_time_ms == WAIT_OTA_TIME_MS)
 800102a:	4b0d      	ldr	r3, [pc, #52]	@ (8001060 <main+0x94>)
 800102c:	681b      	ldr	r3, [r3, #0]
 800102e:	f240 52dc 	movw	r2, #1500	@ 0x5dc
 8001032:	4293      	cmp	r3, r2
 8001034:	d1f7      	bne.n	8001026 <main+0x5a>
	  {
		  //APP_A is ok
		  if(1 == *(volatile uint8_t*)CONFIG_IAP_INFO_ADDR)
 8001036:	4b0b      	ldr	r3, [pc, #44]	@ (8001064 <main+0x98>)
 8001038:	781b      	ldrb	r3, [r3, #0]
 800103a:	b2db      	uxtb	r3, r3
 800103c:	2b01      	cmp	r3, #1
 800103e:	d107      	bne.n	8001050 <main+0x84>
		  //if(0)
		  {
			  system_time_ms = WAIT_OTA_TIME_MS;
 8001040:	4b07      	ldr	r3, [pc, #28]	@ (8001060 <main+0x94>)
 8001042:	f240 52dc 	movw	r2, #1500	@ 0x5dc
 8001046:	601a      	str	r2, [r3, #0]
			  jump_to_app(APP1_ADDRESS);
 8001048:	4807      	ldr	r0, [pc, #28]	@ (8001068 <main+0x9c>)
 800104a:	f7ff fed1 	bl	8000df0 <jump_to_app>
 800104e:	e7ea      	b.n	8001026 <main+0x5a>
		  }
		  else
		  {
			  app_error_flag = 1;
 8001050:	4b06      	ldr	r3, [pc, #24]	@ (800106c <main+0xa0>)
 8001052:	2201      	movs	r2, #1
 8001054:	701a      	strb	r2, [r3, #0]
	  check_SID_run();
 8001056:	e7e6      	b.n	8001026 <main+0x5a>
 8001058:	2000008c 	.word	0x2000008c
 800105c:	08008001 	.word	0x08008001
 8001060:	200000e0 	.word	0x200000e0
 8001064:	08008000 	.word	0x08008000
 8001068:	0800c000 	.word	0x0800c000
 800106c:	200000e4 	.word	0x200000e4

08001070 <SystemClock_Config>:
/**
  * @brief System Clock Configuration
  * @retval None
  */
void SystemClock_Config(void)
{
 8001070:	b580      	push	{r7, lr}
 8001072:	b094      	sub	sp, #80	@ 0x50
 8001074:	af00      	add	r7, sp, #0
  RCC_OscInitTypeDef RCC_OscInitStruct = {0};
 8001076:	f107 0320 	add.w	r3, r7, #32
 800107a:	2230      	movs	r2, #48	@ 0x30
 800107c:	2100      	movs	r1, #0
 800107e:	4618      	mov	r0, r3
 8001080:	f004 fc58 	bl	8005934 <memset>
  RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
 8001084:	f107 030c 	add.w	r3, r7, #12
 8001088:	2200      	movs	r2, #0
 800108a:	601a      	str	r2, [r3, #0]
 800108c:	605a      	str	r2, [r3, #4]
 800108e:	609a      	str	r2, [r3, #8]
 8001090:	60da      	str	r2, [r3, #12]
 8001092:	611a      	str	r2, [r3, #16]

  /** Configure the main internal regulator output voltage
  */
  __HAL_RCC_PWR_CLK_ENABLE();
 8001094:	2300      	movs	r3, #0
 8001096:	60bb      	str	r3, [r7, #8]
 8001098:	4b28      	ldr	r3, [pc, #160]	@ (800113c <SystemClock_Config+0xcc>)
 800109a:	6c1b      	ldr	r3, [r3, #64]	@ 0x40
 800109c:	4a27      	ldr	r2, [pc, #156]	@ (800113c <SystemClock_Config+0xcc>)
 800109e:	f043 5380 	orr.w	r3, r3, #268435456	@ 0x10000000
 80010a2:	6413      	str	r3, [r2, #64]	@ 0x40
 80010a4:	4b25      	ldr	r3, [pc, #148]	@ (800113c <SystemClock_Config+0xcc>)
 80010a6:	6c1b      	ldr	r3, [r3, #64]	@ 0x40
 80010a8:	f003 5380 	and.w	r3, r3, #268435456	@ 0x10000000
 80010ac:	60bb      	str	r3, [r7, #8]
 80010ae:	68bb      	ldr	r3, [r7, #8]
  __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
 80010b0:	2300      	movs	r3, #0
 80010b2:	607b      	str	r3, [r7, #4]
 80010b4:	4b22      	ldr	r3, [pc, #136]	@ (8001140 <SystemClock_Config+0xd0>)
 80010b6:	681b      	ldr	r3, [r3, #0]
 80010b8:	4a21      	ldr	r2, [pc, #132]	@ (8001140 <SystemClock_Config+0xd0>)
 80010ba:	f443 4380 	orr.w	r3, r3, #16384	@ 0x4000
 80010be:	6013      	str	r3, [r2, #0]
 80010c0:	4b1f      	ldr	r3, [pc, #124]	@ (8001140 <SystemClock_Config+0xd0>)
 80010c2:	681b      	ldr	r3, [r3, #0]
 80010c4:	f403 4380 	and.w	r3, r3, #16384	@ 0x4000
 80010c8:	607b      	str	r3, [r7, #4]
 80010ca:	687b      	ldr	r3, [r7, #4]

  /** Initializes the RCC Oscillators according to the specified parameters
  * in the RCC_OscInitTypeDef structure.
  */
  RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
 80010cc:	2301      	movs	r3, #1
 80010ce:	623b      	str	r3, [r7, #32]
  RCC_OscInitStruct.HSEState = RCC_HSE_ON;
 80010d0:	f44f 3380 	mov.w	r3, #65536	@ 0x10000
 80010d4:	627b      	str	r3, [r7, #36]	@ 0x24
  RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
 80010d6:	2302      	movs	r3, #2
 80010d8:	63bb      	str	r3, [r7, #56]	@ 0x38
  RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
 80010da:	f44f 0380 	mov.w	r3, #4194304	@ 0x400000
 80010de:	63fb      	str	r3, [r7, #60]	@ 0x3c
  RCC_OscInitStruct.PLL.PLLM = 4;
 80010e0:	2304      	movs	r3, #4
 80010e2:	643b      	str	r3, [r7, #64]	@ 0x40
  RCC_OscInitStruct.PLL.PLLN = 168;
 80010e4:	23a8      	movs	r3, #168	@ 0xa8
 80010e6:	647b      	str	r3, [r7, #68]	@ 0x44
  RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2;
 80010e8:	2302      	movs	r3, #2
 80010ea:	64bb      	str	r3, [r7, #72]	@ 0x48
  RCC_OscInitStruct.PLL.PLLQ = 4;
 80010ec:	2304      	movs	r3, #4
 80010ee:	64fb      	str	r3, [r7, #76]	@ 0x4c
  if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
 80010f0:	f107 0320 	add.w	r3, r7, #32
 80010f4:	4618      	mov	r0, r3
 80010f6:	f003 fb49 	bl	800478c <HAL_RCC_OscConfig>
 80010fa:	4603      	mov	r3, r0
 80010fc:	2b00      	cmp	r3, #0
 80010fe:	d001      	beq.n	8001104 <SystemClock_Config+0x94>
  {
    Error_Handler();
 8001100:	f000 f820 	bl	8001144 <Error_Handler>
  }

  /** Initializes the CPU, AHB and APB buses clocks
  */
  RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
 8001104:	230f      	movs	r3, #15
 8001106:	60fb      	str	r3, [r7, #12]
                              |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2;
  RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
 8001108:	2302      	movs	r3, #2
 800110a:	613b      	str	r3, [r7, #16]
  RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
 800110c:	2300      	movs	r3, #0
 800110e:	617b      	str	r3, [r7, #20]
  RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV4;
 8001110:	f44f 53a0 	mov.w	r3, #5120	@ 0x1400
 8001114:	61bb      	str	r3, [r7, #24]
  RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV2;
 8001116:	f44f 5380 	mov.w	r3, #4096	@ 0x1000
 800111a:	61fb      	str	r3, [r7, #28]

  if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_5) != HAL_OK)
 800111c:	f107 030c 	add.w	r3, r7, #12
 8001120:	2105      	movs	r1, #5
 8001122:	4618      	mov	r0, r3
 8001124:	f003 fdaa 	bl	8004c7c <HAL_RCC_ClockConfig>
 8001128:	4603      	mov	r3, r0
 800112a:	2b00      	cmp	r3, #0
 800112c:	d001      	beq.n	8001132 <SystemClock_Config+0xc2>
  {
    Error_Handler();
 800112e:	f000 f809 	bl	8001144 <Error_Handler>
  }
}
 8001132:	bf00      	nop
 8001134:	3750      	adds	r7, #80	@ 0x50
 8001136:	46bd      	mov	sp, r7
 8001138:	bd80      	pop	{r7, pc}
 800113a:	bf00      	nop
 800113c:	40023800 	.word	0x40023800
 8001140:	40007000 	.word	0x40007000

08001144 <Error_Handler>:
/**
  * @brief  This function is executed in case of error occurrence.
  * @retval None
  */
void Error_Handler(void)
{
 8001144:	b480      	push	{r7}
 8001146:	af00      	add	r7, sp, #0
  __ASM volatile ("cpsid i" : : : "memory");
 8001148:	b672      	cpsid	i
}
 800114a:	bf00      	nop
  /* USER CODE BEGIN Error_Handler_Debug */
  /* User can add his own implementation to report the HAL error return state */
  __disable_irq();
  while (1)
 800114c:	bf00      	nop
 800114e:	e7fd      	b.n	800114c <Error_Handler+0x8>

08001150 <HAL_MspInit>:
/* USER CODE END 0 */
/**
  * Initializes the Global MSP.
  */
void HAL_MspInit(void)
{
 8001150:	b480      	push	{r7}
 8001152:	b083      	sub	sp, #12
 8001154:	af00      	add	r7, sp, #0

  /* USER CODE BEGIN MspInit 0 */

  /* USER CODE END MspInit 0 */

  __HAL_RCC_SYSCFG_CLK_ENABLE();
 8001156:	2300      	movs	r3, #0
 8001158:	607b      	str	r3, [r7, #4]
 800115a:	4b10      	ldr	r3, [pc, #64]	@ (800119c <HAL_MspInit+0x4c>)
 800115c:	6c5b      	ldr	r3, [r3, #68]	@ 0x44
 800115e:	4a0f      	ldr	r2, [pc, #60]	@ (800119c <HAL_MspInit+0x4c>)
 8001160:	f443 4380 	orr.w	r3, r3, #16384	@ 0x4000
 8001164:	6453      	str	r3, [r2, #68]	@ 0x44
 8001166:	4b0d      	ldr	r3, [pc, #52]	@ (800119c <HAL_MspInit+0x4c>)
 8001168:	6c5b      	ldr	r3, [r3, #68]	@ 0x44
 800116a:	f403 4380 	and.w	r3, r3, #16384	@ 0x4000
 800116e:	607b      	str	r3, [r7, #4]
 8001170:	687b      	ldr	r3, [r7, #4]
  __HAL_RCC_PWR_CLK_ENABLE();
 8001172:	2300      	movs	r3, #0
 8001174:	603b      	str	r3, [r7, #0]
 8001176:	4b09      	ldr	r3, [pc, #36]	@ (800119c <HAL_MspInit+0x4c>)
 8001178:	6c1b      	ldr	r3, [r3, #64]	@ 0x40
 800117a:	4a08      	ldr	r2, [pc, #32]	@ (800119c <HAL_MspInit+0x4c>)
 800117c:	f043 5380 	orr.w	r3, r3, #268435456	@ 0x10000000
 8001180:	6413      	str	r3, [r2, #64]	@ 0x40
 8001182:	4b06      	ldr	r3, [pc, #24]	@ (800119c <HAL_MspInit+0x4c>)
 8001184:	6c1b      	ldr	r3, [r3, #64]	@ 0x40
 8001186:	f003 5380 	and.w	r3, r3, #268435456	@ 0x10000000
 800118a:	603b      	str	r3, [r7, #0]
 800118c:	683b      	ldr	r3, [r7, #0]
  /* System interrupt init*/

  /* USER CODE BEGIN MspInit 1 */

  /* USER CODE END MspInit 1 */
}
 800118e:	bf00      	nop
 8001190:	370c      	adds	r7, #12
 8001192:	46bd      	mov	sp, r7
 8001194:	f85d 7b04 	ldr.w	r7, [sp], #4
 8001198:	4770      	bx	lr
 800119a:	bf00      	nop
 800119c:	40023800 	.word	0x40023800

080011a0 <NMI_Handler>:
/******************************************************************************/
/**
  * @brief This function handles Non maskable interrupt.
  */
void NMI_Handler(void)
{
 80011a0:	b480      	push	{r7}
 80011a2:	af00      	add	r7, sp, #0
  /* USER CODE BEGIN NonMaskableInt_IRQn 0 */

  /* USER CODE END NonMaskableInt_IRQn 0 */
  /* USER CODE BEGIN NonMaskableInt_IRQn 1 */
   while (1)
 80011a4:	bf00      	nop
 80011a6:	e7fd      	b.n	80011a4 <NMI_Handler+0x4>

080011a8 <HardFault_Handler>:

/**
  * @brief This function handles Hard fault interrupt.
  */
void HardFault_Handler(void)
{
 80011a8:	b480      	push	{r7}
 80011aa:	af00      	add	r7, sp, #0
  /* USER CODE BEGIN HardFault_IRQn 0 */

  /* USER CODE END HardFault_IRQn 0 */
  while (1)
 80011ac:	bf00      	nop
 80011ae:	e7fd      	b.n	80011ac <HardFault_Handler+0x4>

080011b0 <MemManage_Handler>:

/**
  * @brief This function handles Memory management fault.
  */
void MemManage_Handler(void)
{
 80011b0:	b480      	push	{r7}
 80011b2:	af00      	add	r7, sp, #0
  /* USER CODE BEGIN MemoryManagement_IRQn 0 */

  /* USER CODE END MemoryManagement_IRQn 0 */
  while (1)
 80011b4:	bf00      	nop
 80011b6:	e7fd      	b.n	80011b4 <MemManage_Handler+0x4>

080011b8 <BusFault_Handler>:

/**
  * @brief This function handles Pre-fetch fault, memory access fault.
  */
void BusFault_Handler(void)
{
 80011b8:	b480      	push	{r7}
 80011ba:	af00      	add	r7, sp, #0
  /* USER CODE BEGIN BusFault_IRQn 0 */

  /* USER CODE END BusFault_IRQn 0 */
  while (1)
 80011bc:	bf00      	nop
 80011be:	e7fd      	b.n	80011bc <BusFault_Handler+0x4>

080011c0 <UsageFault_Handler>:

/**
  * @brief This function handles Undefined instruction or illegal state.
  */
void UsageFault_Handler(void)
{
 80011c0:	b480      	push	{r7}
 80011c2:	af00      	add	r7, sp, #0
  /* USER CODE BEGIN UsageFault_IRQn 0 */

  /* USER CODE END UsageFault_IRQn 0 */
  while (1)
 80011c4:	bf00      	nop
 80011c6:	e7fd      	b.n	80011c4 <UsageFault_Handler+0x4>

080011c8 <SVC_Handler>:

/**
  * @brief This function handles System service call via SWI instruction.
  */
void SVC_Handler(void)
{
 80011c8:	b480      	push	{r7}
 80011ca:	af00      	add	r7, sp, #0

  /* USER CODE END SVCall_IRQn 0 */
  /* USER CODE BEGIN SVCall_IRQn 1 */

  /* USER CODE END SVCall_IRQn 1 */
}
 80011cc:	bf00      	nop
 80011ce:	46bd      	mov	sp, r7
 80011d0:	f85d 7b04 	ldr.w	r7, [sp], #4
 80011d4:	4770      	bx	lr

080011d6 <DebugMon_Handler>:

/**
  * @brief This function handles Debug monitor.
  */
void DebugMon_Handler(void)
{
 80011d6:	b480      	push	{r7}
 80011d8:	af00      	add	r7, sp, #0

  /* USER CODE END DebugMonitor_IRQn 0 */
  /* USER CODE BEGIN DebugMonitor_IRQn 1 */

  /* USER CODE END DebugMonitor_IRQn 1 */
}
 80011da:	bf00      	nop
 80011dc:	46bd      	mov	sp, r7
 80011de:	f85d 7b04 	ldr.w	r7, [sp], #4
 80011e2:	4770      	bx	lr

080011e4 <PendSV_Handler>:

/**
  * @brief This function handles Pendable request for system service.
  */
void PendSV_Handler(void)
{
 80011e4:	b480      	push	{r7}
 80011e6:	af00      	add	r7, sp, #0

  /* USER CODE END PendSV_IRQn 0 */
  /* USER CODE BEGIN PendSV_IRQn 1 */

  /* USER CODE END PendSV_IRQn 1 */
}
 80011e8:	bf00      	nop
 80011ea:	46bd      	mov	sp, r7
 80011ec:	f85d 7b04 	ldr.w	r7, [sp], #4
 80011f0:	4770      	bx	lr

080011f2 <SysTick_Handler>:

/**
  * @brief This function handles System tick timer.
  */
void SysTick_Handler(void)
{
 80011f2:	b580      	push	{r7, lr}
 80011f4:	af00      	add	r7, sp, #0
  /* USER CODE BEGIN SysTick_IRQn 0 */

  /* USER CODE END SysTick_IRQn 0 */
  HAL_IncTick();
 80011f6:	f001 ff93 	bl	8003120 <HAL_IncTick>
  /* USER CODE BEGIN SysTick_IRQn 1 */

  /* USER CODE END SysTick_IRQn 1 */
}
 80011fa:	bf00      	nop
 80011fc:	bd80      	pop	{r7, pc}
	...

08001200 <CAN1_RX0_IRQHandler>:

/**
  * @brief This function handles CAN1 RX0 interrupts.
  */
void CAN1_RX0_IRQHandler(void)
{
 8001200:	b580      	push	{r7, lr}
 8001202:	af00      	add	r7, sp, #0
  /* USER CODE BEGIN CAN1_RX0_IRQn 0 */

  /* USER CODE END CAN1_RX0_IRQn 0 */
  HAL_CAN_IRQHandler(&hcan1);
 8001204:	4802      	ldr	r0, [pc, #8]	@ (8001210 <CAN1_RX0_IRQHandler+0x10>)
 8001206:	f002 fcb5 	bl	8003b74 <HAL_CAN_IRQHandler>
  /* USER CODE BEGIN CAN1_RX0_IRQn 1 */

  /* USER CODE END CAN1_RX0_IRQn 1 */
}
 800120a:	bf00      	nop
 800120c:	bd80      	pop	{r7, pc}
 800120e:	bf00      	nop
 8001210:	20000064 	.word	0x20000064

08001214 <TIM2_IRQHandler>:

/**
  * @brief This function handles TIM2 global interrupt.
  */
void TIM2_IRQHandler(void)
{
 8001214:	b580      	push	{r7, lr}
 8001216:	af00      	add	r7, sp, #0
  /* USER CODE BEGIN TIM2_IRQn 0 */

  /* USER CODE END TIM2_IRQn 0 */
  HAL_TIM_IRQHandler(&htim2);
 8001218:	4802      	ldr	r0, [pc, #8]	@ (8001224 <TIM2_IRQHandler+0x10>)
 800121a:	f003 ffdb 	bl	80051d4 <HAL_TIM_IRQHandler>
  /* USER CODE BEGIN TIM2_IRQn 1 */

  /* USER CODE END TIM2_IRQn 1 */
}
 800121e:	bf00      	nop
 8001220:	bd80      	pop	{r7, pc}
 8001222:	bf00      	nop
 8001224:	2000008c 	.word	0x2000008c

08001228 <SystemInit>:
  *         configuration.
  * @param  None
  * @retval None
  */
void SystemInit(void)
{
 8001228:	b480      	push	{r7}
 800122a:	af00      	add	r7, sp, #0
  /* FPU settings ------------------------------------------------------------*/
  #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
    SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2));  /* set CP10 and CP11 Full Access */
 800122c:	4b06      	ldr	r3, [pc, #24]	@ (8001248 <SystemInit+0x20>)
 800122e:	f8d3 3088 	ldr.w	r3, [r3, #136]	@ 0x88
 8001232:	4a05      	ldr	r2, [pc, #20]	@ (8001248 <SystemInit+0x20>)
 8001234:	f443 0370 	orr.w	r3, r3, #15728640	@ 0xf00000
 8001238:	f8c2 3088 	str.w	r3, [r2, #136]	@ 0x88

  /* Configure the Vector Table location -------------------------------------*/
#if defined(USER_VECT_TAB_ADDRESS)
  SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
#endif /* USER_VECT_TAB_ADDRESS */
}
 800123c:	bf00      	nop
 800123e:	46bd      	mov	sp, r7
 8001240:	f85d 7b04 	ldr.w	r7, [sp], #4
 8001244:	4770      	bx	lr
 8001246:	bf00      	nop
 8001248:	e000ed00 	.word	0xe000ed00

0800124c <MX_TIM2_Init>:

TIM_HandleTypeDef htim2;

/* TIM2 init function */
void MX_TIM2_Init(void)
{
 800124c:	b580      	push	{r7, lr}
 800124e:	b086      	sub	sp, #24
 8001250:	af00      	add	r7, sp, #0

  /* USER CODE BEGIN TIM2_Init 0 */

  /* USER CODE END TIM2_Init 0 */

  TIM_ClockConfigTypeDef sClockSourceConfig = {0};
 8001252:	f107 0308 	add.w	r3, r7, #8
 8001256:	2200      	movs	r2, #0
 8001258:	601a      	str	r2, [r3, #0]
 800125a:	605a      	str	r2, [r3, #4]
 800125c:	609a      	str	r2, [r3, #8]
 800125e:	60da      	str	r2, [r3, #12]
  TIM_MasterConfigTypeDef sMasterConfig = {0};
 8001260:	463b      	mov	r3, r7
 8001262:	2200      	movs	r2, #0
 8001264:	601a      	str	r2, [r3, #0]
 8001266:	605a      	str	r2, [r3, #4]

  /* USER CODE BEGIN TIM2_Init 1 */

  /* USER CODE END TIM2_Init 1 */
  htim2.Instance = TIM2;
 8001268:	4b1d      	ldr	r3, [pc, #116]	@ (80012e0 <MX_TIM2_Init+0x94>)
 800126a:	f04f 4280 	mov.w	r2, #1073741824	@ 0x40000000
 800126e:	601a      	str	r2, [r3, #0]
  htim2.Init.Prescaler = 84-1;
 8001270:	4b1b      	ldr	r3, [pc, #108]	@ (80012e0 <MX_TIM2_Init+0x94>)
 8001272:	2253      	movs	r2, #83	@ 0x53
 8001274:	605a      	str	r2, [r3, #4]
  htim2.Init.CounterMode = TIM_COUNTERMODE_UP;
 8001276:	4b1a      	ldr	r3, [pc, #104]	@ (80012e0 <MX_TIM2_Init+0x94>)
 8001278:	2200      	movs	r2, #0
 800127a:	609a      	str	r2, [r3, #8]
  htim2.Init.Period = 1000;
 800127c:	4b18      	ldr	r3, [pc, #96]	@ (80012e0 <MX_TIM2_Init+0x94>)
 800127e:	f44f 727a 	mov.w	r2, #1000	@ 0x3e8
 8001282:	60da      	str	r2, [r3, #12]
  htim2.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1;
 8001284:	4b16      	ldr	r3, [pc, #88]	@ (80012e0 <MX_TIM2_Init+0x94>)
 8001286:	2200      	movs	r2, #0
 8001288:	611a      	str	r2, [r3, #16]
  htim2.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE;
 800128a:	4b15      	ldr	r3, [pc, #84]	@ (80012e0 <MX_TIM2_Init+0x94>)
 800128c:	2200      	movs	r2, #0
 800128e:	619a      	str	r2, [r3, #24]
  if (HAL_TIM_Base_Init(&htim2) != HAL_OK)
 8001290:	4813      	ldr	r0, [pc, #76]	@ (80012e0 <MX_TIM2_Init+0x94>)
 8001292:	f003 fedf 	bl	8005054 <HAL_TIM_Base_Init>
 8001296:	4603      	mov	r3, r0
 8001298:	2b00      	cmp	r3, #0
 800129a:	d001      	beq.n	80012a0 <MX_TIM2_Init+0x54>
  {
    Error_Handler();
 800129c:	f7ff ff52 	bl	8001144 <Error_Handler>
  }
  sClockSourceConfig.ClockSource = TIM_CLOCKSOURCE_INTERNAL;
 80012a0:	f44f 5380 	mov.w	r3, #4096	@ 0x1000
 80012a4:	60bb      	str	r3, [r7, #8]
  if (HAL_TIM_ConfigClockSource(&htim2, &sClockSourceConfig) != HAL_OK)
 80012a6:	f107 0308 	add.w	r3, r7, #8
 80012aa:	4619      	mov	r1, r3
 80012ac:	480c      	ldr	r0, [pc, #48]	@ (80012e0 <MX_TIM2_Init+0x94>)
 80012ae:	f004 f881 	bl	80053b4 <HAL_TIM_ConfigClockSource>
 80012b2:	4603      	mov	r3, r0
 80012b4:	2b00      	cmp	r3, #0
 80012b6:	d001      	beq.n	80012bc <MX_TIM2_Init+0x70>
  {
    Error_Handler();
 80012b8:	f7ff ff44 	bl	8001144 <Error_Handler>
  }
  sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET;
 80012bc:	2300      	movs	r3, #0
 80012be:	603b      	str	r3, [r7, #0]
  sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE;
 80012c0:	2300      	movs	r3, #0
 80012c2:	607b      	str	r3, [r7, #4]
  if (HAL_TIMEx_MasterConfigSynchronization(&htim2, &sMasterConfig) != HAL_OK)
 80012c4:	463b      	mov	r3, r7
 80012c6:	4619      	mov	r1, r3
 80012c8:	4805      	ldr	r0, [pc, #20]	@ (80012e0 <MX_TIM2_Init+0x94>)
 80012ca:	f004 faa3 	bl	8005814 <HAL_TIMEx_MasterConfigSynchronization>
 80012ce:	4603      	mov	r3, r0
 80012d0:	2b00      	cmp	r3, #0
 80012d2:	d001      	beq.n	80012d8 <MX_TIM2_Init+0x8c>
  {
    Error_Handler();
 80012d4:	f7ff ff36 	bl	8001144 <Error_Handler>
  }
  /* USER CODE BEGIN TIM2_Init 2 */

  /* USER CODE END TIM2_Init 2 */

}
 80012d8:	bf00      	nop
 80012da:	3718      	adds	r7, #24
 80012dc:	46bd      	mov	sp, r7
 80012de:	bd80      	pop	{r7, pc}
 80012e0:	2000008c 	.word	0x2000008c

080012e4 <HAL_TIM_Base_MspInit>:

void HAL_TIM_Base_MspInit(TIM_HandleTypeDef* tim_baseHandle)
{
 80012e4:	b580      	push	{r7, lr}
 80012e6:	b084      	sub	sp, #16
 80012e8:	af00      	add	r7, sp, #0
 80012ea:	6078      	str	r0, [r7, #4]

  if(tim_baseHandle->Instance==TIM2)
 80012ec:	687b      	ldr	r3, [r7, #4]
 80012ee:	681b      	ldr	r3, [r3, #0]
 80012f0:	f1b3 4f80 	cmp.w	r3, #1073741824	@ 0x40000000
 80012f4:	d115      	bne.n	8001322 <HAL_TIM_Base_MspInit+0x3e>
  {
  /* USER CODE BEGIN TIM2_MspInit 0 */

  /* USER CODE END TIM2_MspInit 0 */
    /* TIM2 clock enable */
    __HAL_RCC_TIM2_CLK_ENABLE();
 80012f6:	2300      	movs	r3, #0
 80012f8:	60fb      	str	r3, [r7, #12]
 80012fa:	4b0c      	ldr	r3, [pc, #48]	@ (800132c <HAL_TIM_Base_MspInit+0x48>)
 80012fc:	6c1b      	ldr	r3, [r3, #64]	@ 0x40
 80012fe:	4a0b      	ldr	r2, [pc, #44]	@ (800132c <HAL_TIM_Base_MspInit+0x48>)
 8001300:	f043 0301 	orr.w	r3, r3, #1
 8001304:	6413      	str	r3, [r2, #64]	@ 0x40
 8001306:	4b09      	ldr	r3, [pc, #36]	@ (800132c <HAL_TIM_Base_MspInit+0x48>)
 8001308:	6c1b      	ldr	r3, [r3, #64]	@ 0x40
 800130a:	f003 0301 	and.w	r3, r3, #1
 800130e:	60fb      	str	r3, [r7, #12]
 8001310:	68fb      	ldr	r3, [r7, #12]

    /* TIM2 interrupt Init */
    HAL_NVIC_SetPriority(TIM2_IRQn, 0, 0);
 8001312:	2200      	movs	r2, #0
 8001314:	2100      	movs	r1, #0
 8001316:	201c      	movs	r0, #28
 8001318:	f002 ff5b 	bl	80041d2 <HAL_NVIC_SetPriority>
    HAL_NVIC_EnableIRQ(TIM2_IRQn);
 800131c:	201c      	movs	r0, #28
 800131e:	f002 ff74 	bl	800420a <HAL_NVIC_EnableIRQ>
  /* USER CODE BEGIN TIM2_MspInit 1 */

  /* USER CODE END TIM2_MspInit 1 */
  }
}
 8001322:	bf00      	nop
 8001324:	3710      	adds	r7, #16
 8001326:	46bd      	mov	sp, r7
 8001328:	bd80      	pop	{r7, pc}
 800132a:	bf00      	nop
 800132c:	40023800 	.word	0x40023800

08001330 <HAL_TIM_PeriodElapsedCallback>:
uint8_t ota_start_flag = 0;
uint32_t system_time_ms = 0;           // 系统运行时间，用于判断上电等待接收升级指令
uint8_t app_error_flag = 0;
uint32_t app_error_counter = 0;
void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim)
{
 8001330:	b580      	push	{r7, lr}
 8001332:	b086      	sub	sp, #24
 8001334:	af02      	add	r7, sp, #8
 8001336:	6078      	str	r0, [r7, #4]
	if (htim->Instance == TIM2)
 8001338:	687b      	ldr	r3, [r7, #4]
 800133a:	681b      	ldr	r3, [r3, #0]
 800133c:	f1b3 4f80 	cmp.w	r3, #1073741824	@ 0x40000000
 8001340:	d151      	bne.n	80013e6 <HAL_TIM_PeriodElapsedCallback+0xb6>
	{
		i15765_update();
 8001342:	f000 fffb 	bl	800233c <i15765_update>

		if(ota_start_flag == 0)
 8001346:	4b2a      	ldr	r3, [pc, #168]	@ (80013f0 <HAL_TIM_PeriodElapsedCallback+0xc0>)
 8001348:	781b      	ldrb	r3, [r3, #0]
 800134a:	2b00      	cmp	r3, #0
 800134c:	d10f      	bne.n	800136e <HAL_TIM_PeriodElapsedCallback+0x3e>
		{
			system_time_ms++;       // 系统时间加1ms
 800134e:	4b29      	ldr	r3, [pc, #164]	@ (80013f4 <HAL_TIM_PeriodElapsedCallback+0xc4>)
 8001350:	681b      	ldr	r3, [r3, #0]
 8001352:	3301      	adds	r3, #1
 8001354:	4a27      	ldr	r2, [pc, #156]	@ (80013f4 <HAL_TIM_PeriodElapsedCallback+0xc4>)
 8001356:	6013      	str	r3, [r2, #0]
			if(system_time_ms >= WAIT_OTA_TIME_MS)
 8001358:	4b26      	ldr	r3, [pc, #152]	@ (80013f4 <HAL_TIM_PeriodElapsedCallback+0xc4>)
 800135a:	681b      	ldr	r3, [r3, #0]
 800135c:	f240 52db 	movw	r2, #1499	@ 0x5db
 8001360:	4293      	cmp	r3, r2
 8001362:	d907      	bls.n	8001374 <HAL_TIM_PeriodElapsedCallback+0x44>
			{
				system_time_ms = WAIT_OTA_TIME_MS;
 8001364:	4b23      	ldr	r3, [pc, #140]	@ (80013f4 <HAL_TIM_PeriodElapsedCallback+0xc4>)
 8001366:	f240 52dc 	movw	r2, #1500	@ 0x5dc
 800136a:	601a      	str	r2, [r3, #0]
 800136c:	e002      	b.n	8001374 <HAL_TIM_PeriodElapsedCallback+0x44>
			}
		}
		else
		{
			system_time_ms = 0;
 800136e:	4b21      	ldr	r3, [pc, #132]	@ (80013f4 <HAL_TIM_PeriodElapsedCallback+0xc4>)
 8001370:	2200      	movs	r2, #0
 8001372:	601a      	str	r2, [r3, #0]
		}

		if(app_error_flag == 1)
 8001374:	4b20      	ldr	r3, [pc, #128]	@ (80013f8 <HAL_TIM_PeriodElapsedCallback+0xc8>)
 8001376:	781b      	ldrb	r3, [r3, #0]
 8001378:	2b01      	cmp	r3, #1
 800137a:	d134      	bne.n	80013e6 <HAL_TIM_PeriodElapsedCallback+0xb6>
		{
			app_error_counter++;
 800137c:	4b1f      	ldr	r3, [pc, #124]	@ (80013fc <HAL_TIM_PeriodElapsedCallback+0xcc>)
 800137e:	681b      	ldr	r3, [r3, #0]
 8001380:	3301      	adds	r3, #1
 8001382:	4a1e      	ldr	r2, [pc, #120]	@ (80013fc <HAL_TIM_PeriodElapsedCallback+0xcc>)
 8001384:	6013      	str	r3, [r2, #0]
			if(app_error_counter >= 1000)
 8001386:	4b1d      	ldr	r3, [pc, #116]	@ (80013fc <HAL_TIM_PeriodElapsedCallback+0xcc>)
 8001388:	681b      	ldr	r3, [r3, #0]
 800138a:	f5b3 7f7a 	cmp.w	r3, #1000	@ 0x3e8
 800138e:	d32a      	bcc.n	80013e6 <HAL_TIM_PeriodElapsedCallback+0xb6>
			{
				app_error_counter = 0;
 8001390:	4b1a      	ldr	r3, [pc, #104]	@ (80013fc <HAL_TIM_PeriodElapsedCallback+0xcc>)
 8001392:	2200      	movs	r2, #0
 8001394:	601a      	str	r2, [r3, #0]
				uint16_t hardware_version = *(volatile uint32_t*)0x08000188;
 8001396:	4b1a      	ldr	r3, [pc, #104]	@ (8001400 <HAL_TIM_PeriodElapsedCallback+0xd0>)
 8001398:	681b      	ldr	r3, [r3, #0]
 800139a:	81fb      	strh	r3, [r7, #14]
				TxBuf[0] = 0x04;
 800139c:	4b19      	ldr	r3, [pc, #100]	@ (8001404 <HAL_TIM_PeriodElapsedCallback+0xd4>)
 800139e:	2204      	movs	r2, #4
 80013a0:	701a      	strb	r2, [r3, #0]
				TxBuf[1] = 0x50;
 80013a2:	4b18      	ldr	r3, [pc, #96]	@ (8001404 <HAL_TIM_PeriodElapsedCallback+0xd4>)
 80013a4:	2250      	movs	r2, #80	@ 0x50
 80013a6:	705a      	strb	r2, [r3, #1]
				TxBuf[2] = 0x02;
 80013a8:	4b16      	ldr	r3, [pc, #88]	@ (8001404 <HAL_TIM_PeriodElapsedCallback+0xd4>)
 80013aa:	2202      	movs	r2, #2
 80013ac:	709a      	strb	r2, [r3, #2]
				TxBuf[3] = hardware_version >> 8;
 80013ae:	89fb      	ldrh	r3, [r7, #14]
 80013b0:	0a1b      	lsrs	r3, r3, #8
 80013b2:	b29b      	uxth	r3, r3
 80013b4:	b2da      	uxtb	r2, r3
 80013b6:	4b13      	ldr	r3, [pc, #76]	@ (8001404 <HAL_TIM_PeriodElapsedCallback+0xd4>)
 80013b8:	70da      	strb	r2, [r3, #3]
				TxBuf[4] = hardware_version & 0xFF;;
 80013ba:	89fb      	ldrh	r3, [r7, #14]
 80013bc:	b2da      	uxtb	r2, r3
 80013be:	4b11      	ldr	r3, [pc, #68]	@ (8001404 <HAL_TIM_PeriodElapsedCallback+0xd4>)
 80013c0:	711a      	strb	r2, [r3, #4]
				TxBuf[5] = 0x55;
 80013c2:	4b10      	ldr	r3, [pc, #64]	@ (8001404 <HAL_TIM_PeriodElapsedCallback+0xd4>)
 80013c4:	2255      	movs	r2, #85	@ 0x55
 80013c6:	715a      	strb	r2, [r3, #5]
				TxBuf[6] = 0x55;
 80013c8:	4b0e      	ldr	r3, [pc, #56]	@ (8001404 <HAL_TIM_PeriodElapsedCallback+0xd4>)
 80013ca:	2255      	movs	r2, #85	@ 0x55
 80013cc:	719a      	strb	r2, [r3, #6]
				TxBuf[7] = 0x55;
 80013ce:	4b0d      	ldr	r3, [pc, #52]	@ (8001404 <HAL_TIM_PeriodElapsedCallback+0xd4>)
 80013d0:	2255      	movs	r2, #85	@ 0x55
 80013d2:	71da      	strb	r2, [r3, #7]
				CAN_SendData(1, 2, 0x709, TxBuf,8);
 80013d4:	2308      	movs	r3, #8
 80013d6:	9300      	str	r3, [sp, #0]
 80013d8:	4b0a      	ldr	r3, [pc, #40]	@ (8001404 <HAL_TIM_PeriodElapsedCallback+0xd4>)
 80013da:	f240 7209 	movw	r2, #1801	@ 0x709
 80013de:	2102      	movs	r1, #2
 80013e0:	2001      	movs	r0, #1
 80013e2:	f7ff f981 	bl	80006e8 <CAN_SendData>
			}
		}
	}
}
 80013e6:	bf00      	nop
 80013e8:	3710      	adds	r7, #16
 80013ea:	46bd      	mov	sp, r7
 80013ec:	bd80      	pop	{r7, pc}
 80013ee:	bf00      	nop
 80013f0:	200000dc 	.word	0x200000dc
 80013f4:	200000e0 	.word	0x200000e0
 80013f8:	200000e4 	.word	0x200000e4
 80013fc:	200000e8 	.word	0x200000e8
 8001400:	08000188 	.word	0x08000188
 8001404:	200000d4 	.word	0x200000d4

08001408 <Reset_Handler>:

    .section  .text.Reset_Handler
  .weak  Reset_Handler
  .type  Reset_Handler, %function
Reset_Handler:  
  ldr   sp, =_estack     /* set stack pointer */
 8001408:	f8df d034 	ldr.w	sp, [pc, #52]	@ 8001440 <LoopFillZerobss+0xe>
  
/* Call the clock system initialization function.*/
  bl  SystemInit  
 800140c:	f7ff ff0c 	bl	8001228 <SystemInit>

/* Copy the data segment initializers from flash to SRAM */  
  ldr r0, =_sdata
 8001410:	480c      	ldr	r0, [pc, #48]	@ (8001444 <LoopFillZerobss+0x12>)
  ldr r1, =_edata
 8001412:	490d      	ldr	r1, [pc, #52]	@ (8001448 <LoopFillZerobss+0x16>)
  ldr r2, =_sidata
 8001414:	4a0d      	ldr	r2, [pc, #52]	@ (800144c <LoopFillZerobss+0x1a>)
  movs r3, #0
 8001416:	2300      	movs	r3, #0
  b LoopCopyDataInit
 8001418:	e002      	b.n	8001420 <LoopCopyDataInit>

0800141a <CopyDataInit>:

CopyDataInit:
  ldr r4, [r2, r3]
 800141a:	58d4      	ldr	r4, [r2, r3]
  str r4, [r0, r3]
 800141c:	50c4      	str	r4, [r0, r3]
  adds r3, r3, #4
 800141e:	3304      	adds	r3, #4

08001420 <LoopCopyDataInit>:

LoopCopyDataInit:
  adds r4, r0, r3
 8001420:	18c4      	adds	r4, r0, r3
  cmp r4, r1
 8001422:	428c      	cmp	r4, r1
  bcc CopyDataInit
 8001424:	d3f9      	bcc.n	800141a <CopyDataInit>
  
/* Zero fill the bss segment. */
  ldr r2, =_sbss
 8001426:	4a0a      	ldr	r2, [pc, #40]	@ (8001450 <LoopFillZerobss+0x1e>)
  ldr r4, =_ebss
 8001428:	4c0a      	ldr	r4, [pc, #40]	@ (8001454 <LoopFillZerobss+0x22>)
  movs r3, #0
 800142a:	2300      	movs	r3, #0
  b LoopFillZerobss
 800142c:	e001      	b.n	8001432 <LoopFillZerobss>

0800142e <FillZerobss>:

FillZerobss:
  str  r3, [r2]
 800142e:	6013      	str	r3, [r2, #0]
  adds r2, r2, #4
 8001430:	3204      	adds	r2, #4

08001432 <LoopFillZerobss>:

LoopFillZerobss:
  cmp r2, r4
 8001432:	42a2      	cmp	r2, r4
  bcc FillZerobss
 8001434:	d3fb      	bcc.n	800142e <FillZerobss>
 
/* Call static constructors */
    bl __libc_init_array
 8001436:	f004 fa85 	bl	8005944 <__libc_init_array>
/* Call the application's entry point.*/
  bl  main
 800143a:	f7ff fdc7 	bl	8000fcc <main>
  bx  lr    
 800143e:	4770      	bx	lr
  ldr   sp, =_estack     /* set stack pointer */
 8001440:	20020000 	.word	0x20020000
  ldr r0, =_sdata
 8001444:	20000000 	.word	0x20000000
  ldr r1, =_edata
 8001448:	20000014 	.word	0x20000014
  ldr r2, =_sidata
 800144c:	08005e00 	.word	0x08005e00
  ldr r2, =_sbss
 8001450:	20000014 	.word	0x20000014
  ldr r4, =_ebss
 8001454:	20001ec0 	.word	0x20001ec0

08001458 <ADC_IRQHandler>:
 * @retval None       
*/
    .section  .text.Default_Handler,"ax",%progbits
Default_Handler:
Infinite_Loop:
  b  Infinite_Loop
 8001458:	e7fe      	b.n	8001458 <ADC_IRQHandler>
	...

0800145c <crc32>:
   0xCDD70693,0x54DE5729,0x23D967BF,0xB3667A2E,0xC4614AB8,0x5D681B02,0x2A6F2B94,
   0xB40BBE37,0xC30C8EA1,0x5A05DF1B,0x2D02EF8D
  };

unsigned int crc32(unsigned int crc32val, unsigned char *s, unsigned int len)
{
 800145c:	b480      	push	{r7}
 800145e:	b087      	sub	sp, #28
 8001460:	af00      	add	r7, sp, #0
 8001462:	60f8      	str	r0, [r7, #12]
 8001464:	60b9      	str	r1, [r7, #8]
 8001466:	607a      	str	r2, [r7, #4]
	unsigned i;

    for (i = 0; i < len; i++)
 8001468:	2300      	movs	r3, #0
 800146a:	617b      	str	r3, [r7, #20]
 800146c:	e011      	b.n	8001492 <crc32+0x36>
    {
        crc32val = crc32_tab[(crc32val ^ s[i]) & 0xff] ^ (crc32val >> 8);
 800146e:	68ba      	ldr	r2, [r7, #8]
 8001470:	697b      	ldr	r3, [r7, #20]
 8001472:	4413      	add	r3, r2
 8001474:	781b      	ldrb	r3, [r3, #0]
 8001476:	461a      	mov	r2, r3
 8001478:	68fb      	ldr	r3, [r7, #12]
 800147a:	4053      	eors	r3, r2
 800147c:	b2db      	uxtb	r3, r3
 800147e:	4a0a      	ldr	r2, [pc, #40]	@ (80014a8 <crc32+0x4c>)
 8001480:	f852 2023 	ldr.w	r2, [r2, r3, lsl #2]
 8001484:	68fb      	ldr	r3, [r7, #12]
 8001486:	0a1b      	lsrs	r3, r3, #8
 8001488:	4053      	eors	r3, r2
 800148a:	60fb      	str	r3, [r7, #12]
    for (i = 0; i < len; i++)
 800148c:	697b      	ldr	r3, [r7, #20]
 800148e:	3301      	adds	r3, #1
 8001490:	617b      	str	r3, [r7, #20]
 8001492:	697a      	ldr	r2, [r7, #20]
 8001494:	687b      	ldr	r3, [r7, #4]
 8001496:	429a      	cmp	r2, r3
 8001498:	d3e9      	bcc.n	800146e <crc32+0x12>
    }

    return crc32val;
 800149a:	68fb      	ldr	r3, [r7, #12]
}
 800149c:	4618      	mov	r0, r3
 800149e:	371c      	adds	r7, #28
 80014a0:	46bd      	mov	sp, r7
 80014a2:	f85d 7b04 	ldr.w	r7, [sp], #4
 80014a6:	4770      	bx	lr
 80014a8:	080059d0 	.word	0x080059d0

080014ac <can_rx>:
** Called by application layer to receive a CAN message.
** RETURN 0: for success
**        1: for failure
*/
uint8_t can_rx(uint8_t p, can_t *frame)
{
 80014ac:	b490      	push	{r4, r7}
 80014ae:	b084      	sub	sp, #16
 80014b0:	af00      	add	r7, sp, #0
 80014b2:	4603      	mov	r3, r0
 80014b4:	6039      	str	r1, [r7, #0]
 80014b6:	71fb      	strb	r3, [r7, #7]
	uint8_t ret = 1;
 80014b8:	2301      	movs	r3, #1
 80014ba:	73fb      	strb	r3, [r7, #15]

	/* since the below global memory is shared with the rx isr, disable isrs */
//	CAN_LOCK();

	/* if there is something in the buffer, return it */
	if(can_buf_rx_cnt[p])
 80014bc:	79fb      	ldrb	r3, [r7, #7]
 80014be:	4a1b      	ldr	r2, [pc, #108]	@ (800152c <can_rx+0x80>)
 80014c0:	5cd3      	ldrb	r3, [r2, r3]
 80014c2:	b2db      	uxtb	r3, r3
 80014c4:	2b00      	cmp	r3, #0
 80014c6:	d02a      	beq.n	800151e <can_rx+0x72>
	{

		/* update buffer size */
		can_buf_rx_cnt[p]--;
 80014c8:	79fb      	ldrb	r3, [r7, #7]
 80014ca:	4a18      	ldr	r2, [pc, #96]	@ (800152c <can_rx+0x80>)
 80014cc:	5cd2      	ldrb	r2, [r2, r3]
 80014ce:	b2d2      	uxtb	r2, r2
 80014d0:	3a01      	subs	r2, #1
 80014d2:	b2d1      	uxtb	r1, r2
 80014d4:	4a15      	ldr	r2, [pc, #84]	@ (800152c <can_rx+0x80>)
 80014d6:	54d1      	strb	r1, [r2, r3]

		/* copy over the new can frame from current buffer location */
		*frame = can_buf_rx[p][can_buf_rx_tail[p]];
 80014d8:	79fa      	ldrb	r2, [r7, #7]
 80014da:	79fb      	ldrb	r3, [r7, #7]
 80014dc:	4914      	ldr	r1, [pc, #80]	@ (8001530 <can_rx+0x84>)
 80014de:	5ccb      	ldrb	r3, [r1, r3]
 80014e0:	461c      	mov	r4, r3
 80014e2:	6838      	ldr	r0, [r7, #0]
 80014e4:	4913      	ldr	r1, [pc, #76]	@ (8001534 <can_rx+0x88>)
 80014e6:	4613      	mov	r3, r2
 80014e8:	009b      	lsls	r3, r3, #2
 80014ea:	4413      	add	r3, r2
 80014ec:	005b      	lsls	r3, r3, #1
 80014ee:	4423      	add	r3, r4
 80014f0:	011b      	lsls	r3, r3, #4
 80014f2:	440b      	add	r3, r1
 80014f4:	4604      	mov	r4, r0
 80014f6:	cb0f      	ldmia	r3, {r0, r1, r2, r3}
 80014f8:	e884 000f 	stmia.w	r4, {r0, r1, r2, r3}

		/* move on to next index in buffer */
		if(++can_buf_rx_tail[p] >= CAN_BUF_RX_SIZE)
 80014fc:	79fb      	ldrb	r3, [r7, #7]
 80014fe:	4a0c      	ldr	r2, [pc, #48]	@ (8001530 <can_rx+0x84>)
 8001500:	5cd2      	ldrb	r2, [r2, r3]
 8001502:	3201      	adds	r2, #1
 8001504:	b2d1      	uxtb	r1, r2
 8001506:	4a0a      	ldr	r2, [pc, #40]	@ (8001530 <can_rx+0x84>)
 8001508:	54d1      	strb	r1, [r2, r3]
 800150a:	4a09      	ldr	r2, [pc, #36]	@ (8001530 <can_rx+0x84>)
 800150c:	5cd3      	ldrb	r3, [r2, r3]
 800150e:	2b09      	cmp	r3, #9
 8001510:	d903      	bls.n	800151a <can_rx+0x6e>
			can_buf_rx_tail[p] = 0;
 8001512:	79fb      	ldrb	r3, [r7, #7]
 8001514:	4a06      	ldr	r2, [pc, #24]	@ (8001530 <can_rx+0x84>)
 8001516:	2100      	movs	r1, #0
 8001518:	54d1      	strb	r1, [r2, r3]

		ret = 0;
 800151a:	2300      	movs	r3, #0
 800151c:	73fb      	strb	r3, [r7, #15]
	}

//	CAN_UNLOCK();

	return ret;
 800151e:	7bfb      	ldrb	r3, [r7, #15]
}
 8001520:	4618      	mov	r0, r3
 8001522:	3710      	adds	r7, #16
 8001524:	46bd      	mov	sp, r7
 8001526:	bc90      	pop	{r4, r7}
 8001528:	4770      	bx	lr
 800152a:	bf00      	nop
 800152c:	20000230 	.word	0x20000230
 8001530:	20000234 	.word	0x20000234
 8001534:	200000ec 	.word	0x200000ec

08001538 <can_rx_isr_i>:
/*
** Internal receive interrupt.
*/

void can_rx_isr_i(uint8_t p,uint32_t msgId,uint8_t * data, uint8_t len)
{
 8001538:	b480      	push	{r7}
 800153a:	b08b      	sub	sp, #44	@ 0x2c
 800153c:	af00      	add	r7, sp, #0
 800153e:	60b9      	str	r1, [r7, #8]
 8001540:	607a      	str	r2, [r7, #4]
 8001542:	461a      	mov	r2, r3
 8001544:	4603      	mov	r3, r0
 8001546:	73fb      	strb	r3, [r7, #15]
 8001548:	4613      	mov	r3, r2
 800154a:	73bb      	strb	r3, [r7, #14]
	can_t *frame;
	can_t tmp_frame;

	/* is there room in the buffer and is it extended? */
	if(can_buf_rx_cnt[p] < CAN_BUF_RX_SIZE)
 800154c:	7bfb      	ldrb	r3, [r7, #15]
 800154e:	4a2f      	ldr	r2, [pc, #188]	@ (800160c <can_rx_isr_i+0xd4>)
 8001550:	5cd3      	ldrb	r3, [r2, r3]
 8001552:	b2db      	uxtb	r3, r3
 8001554:	2b09      	cmp	r3, #9
 8001556:	d826      	bhi.n	80015a6 <can_rx_isr_i+0x6e>
	{

		/* mark we have one more in the buffer */
		can_buf_rx_cnt[p]++;
 8001558:	7bfb      	ldrb	r3, [r7, #15]
 800155a:	4a2c      	ldr	r2, [pc, #176]	@ (800160c <can_rx_isr_i+0xd4>)
 800155c:	5cd2      	ldrb	r2, [r2, r3]
 800155e:	b2d2      	uxtb	r2, r2
 8001560:	3201      	adds	r2, #1
 8001562:	b2d1      	uxtb	r1, r2
 8001564:	4a29      	ldr	r2, [pc, #164]	@ (800160c <can_rx_isr_i+0xd4>)
 8001566:	54d1      	strb	r1, [r2, r3]

		/* get pointer to the next open index */
		frame = (can_t *)&can_buf_rx[p][ can_buf_rx_head[p] ];
 8001568:	7bfa      	ldrb	r2, [r7, #15]
 800156a:	7bfb      	ldrb	r3, [r7, #15]
 800156c:	4928      	ldr	r1, [pc, #160]	@ (8001610 <can_rx_isr_i+0xd8>)
 800156e:	5ccb      	ldrb	r3, [r1, r3]
 8001570:	b2db      	uxtb	r3, r3
 8001572:	4619      	mov	r1, r3
 8001574:	4613      	mov	r3, r2
 8001576:	009b      	lsls	r3, r3, #2
 8001578:	4413      	add	r3, r2
 800157a:	005b      	lsls	r3, r3, #1
 800157c:	440b      	add	r3, r1
 800157e:	011b      	lsls	r3, r3, #4
 8001580:	4a24      	ldr	r2, [pc, #144]	@ (8001614 <can_rx_isr_i+0xdc>)
 8001582:	4413      	add	r3, r2
 8001584:	627b      	str	r3, [r7, #36]	@ 0x24

		/* move on to next index in buffer */
		if(++can_buf_rx_head[p] >= CAN_BUF_RX_SIZE)
 8001586:	7bfb      	ldrb	r3, [r7, #15]
 8001588:	4a21      	ldr	r2, [pc, #132]	@ (8001610 <can_rx_isr_i+0xd8>)
 800158a:	5cd2      	ldrb	r2, [r2, r3]
 800158c:	b2d2      	uxtb	r2, r2
 800158e:	3201      	adds	r2, #1
 8001590:	b2d2      	uxtb	r2, r2
 8001592:	491f      	ldr	r1, [pc, #124]	@ (8001610 <can_rx_isr_i+0xd8>)
 8001594:	4610      	mov	r0, r2
 8001596:	54c8      	strb	r0, [r1, r3]
 8001598:	2a09      	cmp	r2, #9
 800159a:	d907      	bls.n	80015ac <can_rx_isr_i+0x74>
			can_buf_rx_head[p] = 0;
 800159c:	7bfb      	ldrb	r3, [r7, #15]
 800159e:	4a1c      	ldr	r2, [pc, #112]	@ (8001610 <can_rx_isr_i+0xd8>)
 80015a0:	2100      	movs	r1, #0
 80015a2:	54d1      	strb	r1, [r2, r3]
 80015a4:	e002      	b.n	80015ac <can_rx_isr_i+0x74>

	}
	else
	{
		/* point to empty location because our rx buffer is full (always do a read) */
		frame = (can_t *)&tmp_frame;
 80015a6:	f107 0314 	add.w	r3, r7, #20
 80015aa:	627b      	str	r3, [r7, #36]	@ 0x24
	}

	//qiaoxu  Get ID �� data lenth  and  data
	//ID
	frame->id = msgId;
 80015ac:	6a7b      	ldr	r3, [r7, #36]	@ 0x24
 80015ae:	68ba      	ldr	r2, [r7, #8]
 80015b0:	601a      	str	r2, [r3, #0]

	/* get dlc */
	frame->buf_len = len;
 80015b2:	6a7b      	ldr	r3, [r7, #36]	@ 0x24
 80015b4:	7bba      	ldrb	r2, [r7, #14]
 80015b6:	731a      	strb	r2, [r3, #12]
		*   @return The function will return:
		*           - 0: When RX message box hasn't received new data
		*           - 1: When RX data are stored in the data buffer
		*           - 3: When RX data are stored in the data buffer and a message was lost
	*/
	if(frame->buf_len > 0)
 80015b8:	6a7b      	ldr	r3, [r7, #36]	@ 0x24
 80015ba:	7b1b      	ldrb	r3, [r3, #12]
 80015bc:	2b00      	cmp	r3, #0
 80015be:	d01f      	beq.n	8001600 <can_rx_isr_i+0xc8>
	{
		frame->buf[0] = data[0];
 80015c0:	687b      	ldr	r3, [r7, #4]
 80015c2:	781a      	ldrb	r2, [r3, #0]
 80015c4:	6a7b      	ldr	r3, [r7, #36]	@ 0x24
 80015c6:	711a      	strb	r2, [r3, #4]
		frame->buf[1] = data[1];
 80015c8:	687b      	ldr	r3, [r7, #4]
 80015ca:	785a      	ldrb	r2, [r3, #1]
 80015cc:	6a7b      	ldr	r3, [r7, #36]	@ 0x24
 80015ce:	715a      	strb	r2, [r3, #5]
		frame->buf[2] = data[2];
 80015d0:	687b      	ldr	r3, [r7, #4]
 80015d2:	789a      	ldrb	r2, [r3, #2]
 80015d4:	6a7b      	ldr	r3, [r7, #36]	@ 0x24
 80015d6:	719a      	strb	r2, [r3, #6]
		frame->buf[3] = data[3];
 80015d8:	687b      	ldr	r3, [r7, #4]
 80015da:	78da      	ldrb	r2, [r3, #3]
 80015dc:	6a7b      	ldr	r3, [r7, #36]	@ 0x24
 80015de:	71da      	strb	r2, [r3, #7]

		frame->buf[4] = data[4];
 80015e0:	687b      	ldr	r3, [r7, #4]
 80015e2:	791a      	ldrb	r2, [r3, #4]
 80015e4:	6a7b      	ldr	r3, [r7, #36]	@ 0x24
 80015e6:	721a      	strb	r2, [r3, #8]
		frame->buf[5] = data[5];
 80015e8:	687b      	ldr	r3, [r7, #4]
 80015ea:	795a      	ldrb	r2, [r3, #5]
 80015ec:	6a7b      	ldr	r3, [r7, #36]	@ 0x24
 80015ee:	725a      	strb	r2, [r3, #9]
		frame->buf[6] = data[6];
 80015f0:	687b      	ldr	r3, [r7, #4]
 80015f2:	799a      	ldrb	r2, [r3, #6]
 80015f4:	6a7b      	ldr	r3, [r7, #36]	@ 0x24
 80015f6:	729a      	strb	r2, [r3, #10]
		frame->buf[7] = data[7];
 80015f8:	687b      	ldr	r3, [r7, #4]
 80015fa:	79da      	ldrb	r2, [r3, #7]
 80015fc:	6a7b      	ldr	r3, [r7, #36]	@ 0x24
 80015fe:	72da      	strb	r2, [r3, #11]
	}

}
 8001600:	bf00      	nop
 8001602:	372c      	adds	r7, #44	@ 0x2c
 8001604:	46bd      	mov	sp, r7
 8001606:	f85d 7b04 	ldr.w	r7, [sp], #4
 800160a:	4770      	bx	lr
 800160c:	20000230 	.word	0x20000230
 8001610:	2000022c 	.word	0x2000022c
 8001614:	200000ec 	.word	0x200000ec

08001618 <i15765_ai_cmp>:
**
** RETURN: 1: if the ai's match
**         0: otherwise
*/
uint8_t i15765_ai_cmp(i15765_t *msg1, i15765_t *msg2)
{
 8001618:	b480      	push	{r7}
 800161a:	b083      	sub	sp, #12
 800161c:	af00      	add	r7, sp, #0
 800161e:	6078      	str	r0, [r7, #4]
 8001620:	6039      	str	r1, [r7, #0]
	if((msg1->sa != msg2->sa)
 8001622:	687b      	ldr	r3, [r7, #4]
 8001624:	781a      	ldrb	r2, [r3, #0]
 8001626:	683b      	ldr	r3, [r7, #0]
 8001628:	781b      	ldrb	r3, [r3, #0]
 800162a:	429a      	cmp	r2, r3
 800162c:	d10b      	bne.n	8001646 <i15765_ai_cmp+0x2e>
	        || (msg1->ta != msg2->ta)
 800162e:	687b      	ldr	r3, [r7, #4]
 8001630:	785a      	ldrb	r2, [r3, #1]
 8001632:	683b      	ldr	r3, [r7, #0]
 8001634:	785b      	ldrb	r3, [r3, #1]
 8001636:	429a      	cmp	r2, r3
 8001638:	d105      	bne.n	8001646 <i15765_ai_cmp+0x2e>
	        || (msg1->tat != msg2->tat))
 800163a:	687b      	ldr	r3, [r7, #4]
 800163c:	78da      	ldrb	r2, [r3, #3]
 800163e:	683b      	ldr	r3, [r7, #0]
 8001640:	78db      	ldrb	r3, [r3, #3]
 8001642:	429a      	cmp	r2, r3
 8001644:	d001      	beq.n	800164a <i15765_ai_cmp+0x32>
		return 0;
 8001646:	2300      	movs	r3, #0
 8001648:	e000      	b.n	800164c <i15765_ai_cmp+0x34>

	return 1;
 800164a:	2301      	movs	r3, #1
}
 800164c:	4618      	mov	r0, r3
 800164e:	370c      	adds	r7, #12
 8001650:	46bd      	mov	sp, r7
 8001652:	f85d 7b04 	ldr.w	r7, [sp], #4
 8001656:	4770      	bx	lr

08001658 <i15765_init>:
/*
** Initialize the receive and transmit buffers.
*/
void i15765_init(void)
{
 8001658:	b480      	push	{r7}
 800165a:	b083      	sub	sp, #12
 800165c:	af00      	add	r7, sp, #0

	uint8_t i;

	/* clear the rx buffers */
	for(i = 0; i < I15765CFG_MF_RX_BUF_NUM; i++)
 800165e:	2300      	movs	r3, #0
 8001660:	71fb      	strb	r3, [r7, #7]
 8001662:	e00c      	b.n	800167e <i15765_init+0x26>
		i15765_mfrb[i].state = STATE_IDLE;
 8001664:	79fb      	ldrb	r3, [r7, #7]
 8001666:	4a19      	ldr	r2, [pc, #100]	@ (80016cc <i15765_init+0x74>)
 8001668:	f640 0118 	movw	r1, #2072	@ 0x818
 800166c:	fb01 f303 	mul.w	r3, r1, r3
 8001670:	4413      	add	r3, r2
 8001672:	3314      	adds	r3, #20
 8001674:	2200      	movs	r2, #0
 8001676:	701a      	strb	r2, [r3, #0]
	for(i = 0; i < I15765CFG_MF_RX_BUF_NUM; i++)
 8001678:	79fb      	ldrb	r3, [r7, #7]
 800167a:	3301      	adds	r3, #1
 800167c:	71fb      	strb	r3, [r7, #7]
 800167e:	79fb      	ldrb	r3, [r7, #7]
 8001680:	2b00      	cmp	r3, #0
 8001682:	d0ef      	beq.n	8001664 <i15765_init+0xc>

	/* clear the tx buffers */
	for(i = 0; i < I15765CFG_MF_TX_BUF_NUM; i++)
 8001684:	2300      	movs	r3, #0
 8001686:	71fb      	strb	r3, [r7, #7]
 8001688:	e016      	b.n	80016b8 <i15765_init+0x60>
	{

		i15765_mftb[i].state = STATE_IDLE;
 800168a:	79fb      	ldrb	r3, [r7, #7]
 800168c:	4a10      	ldr	r2, [pc, #64]	@ (80016d0 <i15765_init+0x78>)
 800168e:	f240 4124 	movw	r1, #1060	@ 0x424
 8001692:	fb01 f303 	mul.w	r3, r1, r3
 8001696:	4413      	add	r3, r2
 8001698:	3318      	adds	r3, #24
 800169a:	2200      	movs	r2, #0
 800169c:	701a      	strb	r2, [r3, #0]
		i15765_mftb[i].status = 0;//&i15765_tmp;
 800169e:	79fb      	ldrb	r3, [r7, #7]
 80016a0:	4a0b      	ldr	r2, [pc, #44]	@ (80016d0 <i15765_init+0x78>)
 80016a2:	f240 4124 	movw	r1, #1060	@ 0x424
 80016a6:	fb01 f303 	mul.w	r3, r1, r3
 80016aa:	4413      	add	r3, r2
 80016ac:	331c      	adds	r3, #28
 80016ae:	2200      	movs	r2, #0
 80016b0:	601a      	str	r2, [r3, #0]
	for(i = 0; i < I15765CFG_MF_TX_BUF_NUM; i++)
 80016b2:	79fb      	ldrb	r3, [r7, #7]
 80016b4:	3301      	adds	r3, #1
 80016b6:	71fb      	strb	r3, [r7, #7]
 80016b8:	79fb      	ldrb	r3, [r7, #7]
 80016ba:	2b00      	cmp	r3, #0
 80016bc:	d0e5      	beq.n	800168a <i15765_init+0x32>
	}

//	i15765app_init();
}
 80016be:	bf00      	nop
 80016c0:	bf00      	nop
 80016c2:	370c      	adds	r7, #12
 80016c4:	46bd      	mov	sp, r7
 80016c6:	f85d 7b04 	ldr.w	r7, [sp], #4
 80016ca:	4770      	bx	lr
 80016cc:	20000238 	.word	0x20000238
 80016d0:	20000a50 	.word	0x20000a50

080016d4 <i15765_mfrb_get>:
**
** RETURN: 0: success, index found
**         1: failure, buf is full
*/
uint8_t i15765_mfrb_get(i15765_mfr_t **mfrb)
{
 80016d4:	b480      	push	{r7}
 80016d6:	b085      	sub	sp, #20
 80016d8:	af00      	add	r7, sp, #0
 80016da:	6078      	str	r0, [r7, #4]

	uint8_t i;

	/* find first available index */
	for(i = 0; i < I15765CFG_MF_RX_BUF_NUM; i++)
 80016dc:	2300      	movs	r3, #0
 80016de:	73fb      	strb	r3, [r7, #15]
 80016e0:	e018      	b.n	8001714 <i15765_mfrb_get+0x40>
	{

		if(i15765_mfrb[i].state == STATE_IDLE)
 80016e2:	7bfb      	ldrb	r3, [r7, #15]
 80016e4:	4a10      	ldr	r2, [pc, #64]	@ (8001728 <i15765_mfrb_get+0x54>)
 80016e6:	f640 0118 	movw	r1, #2072	@ 0x818
 80016ea:	fb01 f303 	mul.w	r3, r1, r3
 80016ee:	4413      	add	r3, r2
 80016f0:	3314      	adds	r3, #20
 80016f2:	781b      	ldrb	r3, [r3, #0]
 80016f4:	2b00      	cmp	r3, #0
 80016f6:	d10a      	bne.n	800170e <i15765_mfrb_get+0x3a>
		{

			*mfrb = &i15765_mfrb[i];
 80016f8:	7bfb      	ldrb	r3, [r7, #15]
 80016fa:	f640 0218 	movw	r2, #2072	@ 0x818
 80016fe:	fb02 f303 	mul.w	r3, r2, r3
 8001702:	4a09      	ldr	r2, [pc, #36]	@ (8001728 <i15765_mfrb_get+0x54>)
 8001704:	441a      	add	r2, r3
 8001706:	687b      	ldr	r3, [r7, #4]
 8001708:	601a      	str	r2, [r3, #0]
			return 0;
 800170a:	2300      	movs	r3, #0
 800170c:	e006      	b.n	800171c <i15765_mfrb_get+0x48>
	for(i = 0; i < I15765CFG_MF_RX_BUF_NUM; i++)
 800170e:	7bfb      	ldrb	r3, [r7, #15]
 8001710:	3301      	adds	r3, #1
 8001712:	73fb      	strb	r3, [r7, #15]
 8001714:	7bfb      	ldrb	r3, [r7, #15]
 8001716:	2b00      	cmp	r3, #0
 8001718:	d0e3      	beq.n	80016e2 <i15765_mfrb_get+0xe>
		}
	}

	return 1;
 800171a:	2301      	movs	r3, #1
}
 800171c:	4618      	mov	r0, r3
 800171e:	3714      	adds	r7, #20
 8001720:	46bd      	mov	sp, r7
 8001722:	f85d 7b04 	ldr.w	r7, [sp], #4
 8001726:	4770      	bx	lr
 8001728:	20000238 	.word	0x20000238

0800172c <i15765_mftb_get>:
**
** RETURN: 0: success, index found
**         1: failure, buf is full
*/
uint8_t i15765_mftb_get(i15765_mft_t **mftb)
{
 800172c:	b480      	push	{r7}
 800172e:	b085      	sub	sp, #20
 8001730:	af00      	add	r7, sp, #0
 8001732:	6078      	str	r0, [r7, #4]

	uint8_t i;

	/* find first available index */
	for(i = 0; i < I15765CFG_MF_TX_BUF_NUM; i++)
 8001734:	2300      	movs	r3, #0
 8001736:	73fb      	strb	r3, [r7, #15]
 8001738:	e018      	b.n	800176c <i15765_mftb_get+0x40>
	{

		if(i15765_mftb[i].state == STATE_IDLE)
 800173a:	7bfb      	ldrb	r3, [r7, #15]
 800173c:	4a10      	ldr	r2, [pc, #64]	@ (8001780 <i15765_mftb_get+0x54>)
 800173e:	f240 4124 	movw	r1, #1060	@ 0x424
 8001742:	fb01 f303 	mul.w	r3, r1, r3
 8001746:	4413      	add	r3, r2
 8001748:	3318      	adds	r3, #24
 800174a:	781b      	ldrb	r3, [r3, #0]
 800174c:	2b00      	cmp	r3, #0
 800174e:	d10a      	bne.n	8001766 <i15765_mftb_get+0x3a>
		{

			*mftb = &i15765_mftb[i];
 8001750:	7bfb      	ldrb	r3, [r7, #15]
 8001752:	f240 4224 	movw	r2, #1060	@ 0x424
 8001756:	fb02 f303 	mul.w	r3, r2, r3
 800175a:	4a09      	ldr	r2, [pc, #36]	@ (8001780 <i15765_mftb_get+0x54>)
 800175c:	441a      	add	r2, r3
 800175e:	687b      	ldr	r3, [r7, #4]
 8001760:	601a      	str	r2, [r3, #0]
			return 0;
 8001762:	2300      	movs	r3, #0
 8001764:	e006      	b.n	8001774 <i15765_mftb_get+0x48>
	for(i = 0; i < I15765CFG_MF_TX_BUF_NUM; i++)
 8001766:	7bfb      	ldrb	r3, [r7, #15]
 8001768:	3301      	adds	r3, #1
 800176a:	73fb      	strb	r3, [r7, #15]
 800176c:	7bfb      	ldrb	r3, [r7, #15]
 800176e:	2b00      	cmp	r3, #0
 8001770:	d0e3      	beq.n	800173a <i15765_mftb_get+0xe>
		}
	}

	return 1;
 8001772:	2301      	movs	r3, #1
}
 8001774:	4618      	mov	r0, r3
 8001776:	3714      	adds	r7, #20
 8001778:	46bd      	mov	sp, r7
 800177a:	f85d 7b04 	ldr.w	r7, [sp], #4
 800177e:	4770      	bx	lr
 8001780:	20000a50 	.word	0x20000a50

08001784 <i15765_mfrb_del>:

/*
** Delete all receive mf buffers with matching AE info
*/
void i15765_mfrb_del(i15765_t *msg)
{
 8001784:	b580      	push	{r7, lr}
 8001786:	b084      	sub	sp, #16
 8001788:	af00      	add	r7, sp, #0
 800178a:	6078      	str	r0, [r7, #4]
	uint8_t i;

	for(i = 0; i < I15765CFG_MF_RX_BUF_NUM; i++)
 800178c:	2300      	movs	r3, #0
 800178e:	73fb      	strb	r3, [r7, #15]
 8001790:	e01b      	b.n	80017ca <i15765_mfrb_del+0x46>
	{
		if(i15765_ai_cmp(&i15765_mfrb[i].msg, msg))
 8001792:	7bfb      	ldrb	r3, [r7, #15]
 8001794:	f640 0218 	movw	r2, #2072	@ 0x818
 8001798:	fb02 f303 	mul.w	r3, r2, r3
 800179c:	4a0e      	ldr	r2, [pc, #56]	@ (80017d8 <i15765_mfrb_del+0x54>)
 800179e:	4413      	add	r3, r2
 80017a0:	3304      	adds	r3, #4
 80017a2:	6879      	ldr	r1, [r7, #4]
 80017a4:	4618      	mov	r0, r3
 80017a6:	f7ff ff37 	bl	8001618 <i15765_ai_cmp>
 80017aa:	4603      	mov	r3, r0
 80017ac:	2b00      	cmp	r3, #0
 80017ae:	d009      	beq.n	80017c4 <i15765_mfrb_del+0x40>
		{
			i15765_mfrb[i].state = STATE_IDLE;
 80017b0:	7bfb      	ldrb	r3, [r7, #15]
 80017b2:	4a09      	ldr	r2, [pc, #36]	@ (80017d8 <i15765_mfrb_del+0x54>)
 80017b4:	f640 0118 	movw	r1, #2072	@ 0x818
 80017b8:	fb01 f303 	mul.w	r3, r1, r3
 80017bc:	4413      	add	r3, r2
 80017be:	3314      	adds	r3, #20
 80017c0:	2200      	movs	r2, #0
 80017c2:	701a      	strb	r2, [r3, #0]
	for(i = 0; i < I15765CFG_MF_RX_BUF_NUM; i++)
 80017c4:	7bfb      	ldrb	r3, [r7, #15]
 80017c6:	3301      	adds	r3, #1
 80017c8:	73fb      	strb	r3, [r7, #15]
 80017ca:	7bfb      	ldrb	r3, [r7, #15]
 80017cc:	2b00      	cmp	r3, #0
 80017ce:	d0e0      	beq.n	8001792 <i15765_mfrb_del+0xe>
		}
	}
	return;
 80017d0:	bf00      	nop
}
 80017d2:	3710      	adds	r7, #16
 80017d4:	46bd      	mov	sp, r7
 80017d6:	bd80      	pop	{r7, pc}
 80017d8:	20000238 	.word	0x20000238

080017dc <i15765_mftb_seek>:
**
** RETURN: 0 - match found
**         1 - no match
*/
uint8_t i15765_mftb_seek(i15765_t *msg, i15765_mft_t **ptr)
{
 80017dc:	b480      	push	{r7}
 80017de:	b085      	sub	sp, #20
 80017e0:	af00      	add	r7, sp, #0
 80017e2:	6078      	str	r0, [r7, #4]
 80017e4:	6039      	str	r1, [r7, #0]

	uint8_t i;

	for(i = 0; i < I15765CFG_MF_TX_BUF_NUM; i++)
 80017e6:	2300      	movs	r3, #0
 80017e8:	73fb      	strb	r3, [r7, #15]
 80017ea:	e018      	b.n	800181e <i15765_mftb_seek+0x42>
	{

		if(i15765_mftb[i].state != STATE_IDLE)
 80017ec:	7bfb      	ldrb	r3, [r7, #15]
 80017ee:	4a11      	ldr	r2, [pc, #68]	@ (8001834 <i15765_mftb_seek+0x58>)
 80017f0:	f240 4124 	movw	r1, #1060	@ 0x424
 80017f4:	fb01 f303 	mul.w	r3, r1, r3
 80017f8:	4413      	add	r3, r2
 80017fa:	3318      	adds	r3, #24
 80017fc:	781b      	ldrb	r3, [r3, #0]
 80017fe:	2b00      	cmp	r3, #0
 8001800:	d00a      	beq.n	8001818 <i15765_mftb_seek+0x3c>
		{
			*ptr = &i15765_mftb[i];
 8001802:	7bfb      	ldrb	r3, [r7, #15]
 8001804:	f240 4224 	movw	r2, #1060	@ 0x424
 8001808:	fb02 f303 	mul.w	r3, r2, r3
 800180c:	4a09      	ldr	r2, [pc, #36]	@ (8001834 <i15765_mftb_seek+0x58>)
 800180e:	441a      	add	r2, r3
 8001810:	683b      	ldr	r3, [r7, #0]
 8001812:	601a      	str	r2, [r3, #0]
			return 0;
 8001814:	2300      	movs	r3, #0
 8001816:	e006      	b.n	8001826 <i15765_mftb_seek+0x4a>
	for(i = 0; i < I15765CFG_MF_TX_BUF_NUM; i++)
 8001818:	7bfb      	ldrb	r3, [r7, #15]
 800181a:	3301      	adds	r3, #1
 800181c:	73fb      	strb	r3, [r7, #15]
 800181e:	7bfb      	ldrb	r3, [r7, #15]
 8001820:	2b00      	cmp	r3, #0
 8001822:	d0e3      	beq.n	80017ec <i15765_mftb_seek+0x10>
		}
	}

	return 1;
 8001824:	2301      	movs	r3, #1
}
 8001826:	4618      	mov	r0, r3
 8001828:	3714      	adds	r7, #20
 800182a:	46bd      	mov	sp, r7
 800182c:	f85d 7b04 	ldr.w	r7, [sp], #4
 8001830:	4770      	bx	lr
 8001832:	bf00      	nop
 8001834:	20000a50 	.word	0x20000a50

08001838 <i15765_mfrb_seek>:
**
** RETURN: 0 - match found
**         1 - no match
*/
uint8_t i15765_mfrb_seek(i15765_t *msg, i15765_mfr_t **ptr)
{
 8001838:	b480      	push	{r7}
 800183a:	b085      	sub	sp, #20
 800183c:	af00      	add	r7, sp, #0
 800183e:	6078      	str	r0, [r7, #4]
 8001840:	6039      	str	r1, [r7, #0]

	uint8_t i;

	for(i = 0; i < I15765CFG_MF_RX_BUF_NUM; i++)
 8001842:	2300      	movs	r3, #0
 8001844:	73fb      	strb	r3, [r7, #15]
 8001846:	e018      	b.n	800187a <i15765_mfrb_seek+0x42>
	{
		if(i15765_mfrb[i].state != STATE_IDLE)
 8001848:	7bfb      	ldrb	r3, [r7, #15]
 800184a:	4a11      	ldr	r2, [pc, #68]	@ (8001890 <i15765_mfrb_seek+0x58>)
 800184c:	f640 0118 	movw	r1, #2072	@ 0x818
 8001850:	fb01 f303 	mul.w	r3, r1, r3
 8001854:	4413      	add	r3, r2
 8001856:	3314      	adds	r3, #20
 8001858:	781b      	ldrb	r3, [r3, #0]
 800185a:	2b00      	cmp	r3, #0
 800185c:	d00a      	beq.n	8001874 <i15765_mfrb_seek+0x3c>
		{
			*ptr = &i15765_mfrb[i];
 800185e:	7bfb      	ldrb	r3, [r7, #15]
 8001860:	f640 0218 	movw	r2, #2072	@ 0x818
 8001864:	fb02 f303 	mul.w	r3, r2, r3
 8001868:	4a09      	ldr	r2, [pc, #36]	@ (8001890 <i15765_mfrb_seek+0x58>)
 800186a:	441a      	add	r2, r3
 800186c:	683b      	ldr	r3, [r7, #0]
 800186e:	601a      	str	r2, [r3, #0]
			return 0;
 8001870:	2300      	movs	r3, #0
 8001872:	e006      	b.n	8001882 <i15765_mfrb_seek+0x4a>
	for(i = 0; i < I15765CFG_MF_RX_BUF_NUM; i++)
 8001874:	7bfb      	ldrb	r3, [r7, #15]
 8001876:	3301      	adds	r3, #1
 8001878:	73fb      	strb	r3, [r7, #15]
 800187a:	7bfb      	ldrb	r3, [r7, #15]
 800187c:	2b00      	cmp	r3, #0
 800187e:	d0e3      	beq.n	8001848 <i15765_mfrb_seek+0x10>
		}
	}

	return 1;
 8001880:	2301      	movs	r3, #1
}
 8001882:	4618      	mov	r0, r3
 8001884:	3714      	adds	r7, #20
 8001886:	46bd      	mov	sp, r7
 8001888:	f85d 7b04 	ldr.w	r7, [sp], #4
 800188c:	4770      	bx	lr
 800188e:	bf00      	nop
 8001890:	20000238 	.word	0x20000238

08001894 <i15765_tx>:
** RETURN: 0 - success
**         1 - failure
**
*/
uint8_t i15765_tx(i15765_t *msg)
{
 8001894:	b590      	push	{r4, r7, lr}
 8001896:	b08b      	sub	sp, #44	@ 0x2c
 8001898:	af02      	add	r7, sp, #8
 800189a:	6078      	str	r0, [r7, #4]

	can_t can;
	uint8_t i = 0;
 800189c:	2300      	movs	r3, #0
 800189e:	77fb      	strb	r3, [r7, #31]

	// 11bit  ��׼֡  ֱ�Ӹ�ֵID��
	/* physical response */
	can.id = UDS_TX_ID;
 80018a0:	4b19      	ldr	r3, [pc, #100]	@ (8001908 <i15765_tx+0x74>)
 80018a2:	681b      	ldr	r3, [r3, #0]
 80018a4:	60fb      	str	r3, [r7, #12]
//	can.id = msg->ID;
	/* pack the data, garbage will be packed when we overflow so it is the
	   receiver's responsibility to only read as much as was valid */
	for(i = 0; i < 8; i++)
 80018a6:	2300      	movs	r3, #0
 80018a8:	77fb      	strb	r3, [r7, #31]
 80018aa:	e015      	b.n	80018d8 <i15765_tx+0x44>
		can.buf[i] = (i < msg->buf_len) ? msg->buf[i] : BUFFER_DATA_LAST;
 80018ac:	7ffb      	ldrb	r3, [r7, #31]
 80018ae:	b29a      	uxth	r2, r3
 80018b0:	687b      	ldr	r3, [r7, #4]
 80018b2:	891b      	ldrh	r3, [r3, #8]
 80018b4:	429a      	cmp	r2, r3
 80018b6:	d205      	bcs.n	80018c4 <i15765_tx+0x30>
 80018b8:	687b      	ldr	r3, [r7, #4]
 80018ba:	685a      	ldr	r2, [r3, #4]
 80018bc:	7ffb      	ldrb	r3, [r7, #31]
 80018be:	4413      	add	r3, r2
 80018c0:	781b      	ldrb	r3, [r3, #0]
 80018c2:	e001      	b.n	80018c8 <i15765_tx+0x34>
 80018c4:	4b11      	ldr	r3, [pc, #68]	@ (800190c <i15765_tx+0x78>)
 80018c6:	781b      	ldrb	r3, [r3, #0]
 80018c8:	7ffa      	ldrb	r2, [r7, #31]
 80018ca:	3220      	adds	r2, #32
 80018cc:	443a      	add	r2, r7
 80018ce:	f802 3c10 	strb.w	r3, [r2, #-16]
	for(i = 0; i < 8; i++)
 80018d2:	7ffb      	ldrb	r3, [r7, #31]
 80018d4:	3301      	adds	r3, #1
 80018d6:	77fb      	strb	r3, [r7, #31]
 80018d8:	7ffb      	ldrb	r3, [r7, #31]
 80018da:	2b07      	cmp	r3, #7
 80018dc:	d9e6      	bls.n	80018ac <i15765_tx+0x18>

	/* fix all packets to 8 bytes per 15765-4 */
	can.buf_len = 8;
 80018de:	2308      	movs	r3, #8
 80018e0:	763b      	strb	r3, [r7, #24]

	/* Send message */
//	return can_tx(0, &can);

	CAN_SendData(UDS_CAN_COM, UDS_TX_MAILBOX, can.id, can.buf, can.buf_len);
 80018e2:	4b0b      	ldr	r3, [pc, #44]	@ (8001910 <i15765_tx+0x7c>)
 80018e4:	7818      	ldrb	r0, [r3, #0]
 80018e6:	4b0b      	ldr	r3, [pc, #44]	@ (8001914 <i15765_tx+0x80>)
 80018e8:	6819      	ldr	r1, [r3, #0]
 80018ea:	68fa      	ldr	r2, [r7, #12]
 80018ec:	7e3b      	ldrb	r3, [r7, #24]
 80018ee:	461c      	mov	r4, r3
 80018f0:	f107 030c 	add.w	r3, r7, #12
 80018f4:	3304      	adds	r3, #4
 80018f6:	9400      	str	r4, [sp, #0]
 80018f8:	f7fe fef6 	bl	80006e8 <CAN_SendData>

	return 0;
 80018fc:	2300      	movs	r3, #0
}
 80018fe:	4618      	mov	r0, r3
 8001900:	3724      	adds	r7, #36	@ 0x24
 8001902:	46bd      	mov	sp, r7
 8001904:	bd90      	pop	{r4, r7, pc}
 8001906:	bf00      	nop
 8001908:	08005de8 	.word	0x08005de8
 800190c:	08005dec 	.word	0x08005dec
 8001910:	08005ddc 	.word	0x08005ddc
 8001914:	08005de0 	.word	0x08005de0

08001918 <i15765_tx_sf>:
** INPUT:  frame - pointer to the i15765 frame to be transmitted
** RETURN: 0 - success
**         1 - failure
*/
uint8_t i15765_tx_sf(i15765_t *msg)
{
 8001918:	b590      	push	{r4, r7, lr}
 800191a:	b08b      	sub	sp, #44	@ 0x2c
 800191c:	af00      	add	r7, sp, #0
 800191e:	6078      	str	r0, [r7, #4]
	uint8_t cnt;
	i15765_t sf;
	uint8_t buf[8];

	/* copy over the old message */
	sf = *msg;
 8001920:	687b      	ldr	r3, [r7, #4]
 8001922:	f107 0414 	add.w	r4, r7, #20
 8001926:	cb0f      	ldmia	r3, {r0, r1, r2, r3}
 8001928:	e884 000f 	stmia.w	r4, {r0, r1, r2, r3}

	/* start writing at the beginning */
	i = 0;
 800192c:	2300      	movs	r3, #0
 800192e:	f887 3027 	strb.w	r3, [r7, #39]	@ 0x27

	/* construct SF N_PDU and pack it into a CAN frame */
	buf[i++] = (I15765_PDU_SF << 4) | (uint8_t)msg->buf_len;
 8001932:	687b      	ldr	r3, [r7, #4]
 8001934:	891a      	ldrh	r2, [r3, #8]
 8001936:	f897 3027 	ldrb.w	r3, [r7, #39]	@ 0x27
 800193a:	1c59      	adds	r1, r3, #1
 800193c:	f887 1027 	strb.w	r1, [r7, #39]	@ 0x27
 8001940:	b2d2      	uxtb	r2, r2
 8001942:	3328      	adds	r3, #40	@ 0x28
 8001944:	443b      	add	r3, r7
 8001946:	f803 2c1c 	strb.w	r2, [r3, #-28]

	for(cnt = 0; cnt < msg->buf_len; cnt++)
 800194a:	2300      	movs	r3, #0
 800194c:	f887 3026 	strb.w	r3, [r7, #38]	@ 0x26
 8001950:	e013      	b.n	800197a <i15765_tx_sf+0x62>
		buf[i++] = msg->buf[cnt];
 8001952:	687b      	ldr	r3, [r7, #4]
 8001954:	685a      	ldr	r2, [r3, #4]
 8001956:	f897 3026 	ldrb.w	r3, [r7, #38]	@ 0x26
 800195a:	441a      	add	r2, r3
 800195c:	f897 3027 	ldrb.w	r3, [r7, #39]	@ 0x27
 8001960:	1c59      	adds	r1, r3, #1
 8001962:	f887 1027 	strb.w	r1, [r7, #39]	@ 0x27
 8001966:	7812      	ldrb	r2, [r2, #0]
 8001968:	3328      	adds	r3, #40	@ 0x28
 800196a:	443b      	add	r3, r7
 800196c:	f803 2c1c 	strb.w	r2, [r3, #-28]
	for(cnt = 0; cnt < msg->buf_len; cnt++)
 8001970:	f897 3026 	ldrb.w	r3, [r7, #38]	@ 0x26
 8001974:	3301      	adds	r3, #1
 8001976:	f887 3026 	strb.w	r3, [r7, #38]	@ 0x26
 800197a:	f897 3026 	ldrb.w	r3, [r7, #38]	@ 0x26
 800197e:	b29a      	uxth	r2, r3
 8001980:	687b      	ldr	r3, [r7, #4]
 8001982:	891b      	ldrh	r3, [r3, #8]
 8001984:	429a      	cmp	r2, r3
 8001986:	d3e4      	bcc.n	8001952 <i15765_tx_sf+0x3a>

	sf.buf = buf;
 8001988:	f107 030c 	add.w	r3, r7, #12
 800198c:	61bb      	str	r3, [r7, #24]
	sf.buf_len = i;
 800198e:	f897 3027 	ldrb.w	r3, [r7, #39]	@ 0x27
 8001992:	b29b      	uxth	r3, r3
 8001994:	83bb      	strh	r3, [r7, #28]

	/* attempt to buffer the CAN frame */
	return i15765_tx(&sf);
 8001996:	f107 0314 	add.w	r3, r7, #20
 800199a:	4618      	mov	r0, r3
 800199c:	f7ff ff7a 	bl	8001894 <i15765_tx>
 80019a0:	4603      	mov	r3, r0
}
 80019a2:	4618      	mov	r0, r3
 80019a4:	372c      	adds	r7, #44	@ 0x2c
 80019a6:	46bd      	mov	sp, r7
 80019a8:	bd90      	pop	{r4, r7, pc}
	...

080019ac <i15765_tx_ff>:
/*
** Transmit a first frame.
** INPUT: frame - pointer to the i15765 multiframe buffer
*/
void i15765_tx_ff(i15765_mft_t *mftb)
{
 80019ac:	b590      	push	{r4, r7, lr}
 80019ae:	b08b      	sub	sp, #44	@ 0x2c
 80019b0:	af00      	add	r7, sp, #0
 80019b2:	6078      	str	r0, [r7, #4]

	uint8_t i = 0;
 80019b4:	2300      	movs	r3, #0
 80019b6:	f887 3027 	strb.w	r3, [r7, #39]	@ 0x27
	uint8_t *ptr;
	uint8_t buf[8];
	i15765_t frame;

	/* copy over message */
	frame = mftb->msg;
 80019ba:	687b      	ldr	r3, [r7, #4]
 80019bc:	f107 0408 	add.w	r4, r7, #8
 80019c0:	3308      	adds	r3, #8
 80019c2:	cb0f      	ldmia	r3, {r0, r1, r2, r3}
 80019c4:	e884 000f 	stmia.w	r4, {r0, r1, r2, r3}
	frame.buf = buf;
 80019c8:	f107 0318 	add.w	r3, r7, #24
 80019cc:	60fb      	str	r3, [r7, #12]
	ptr = mftb->buf;
 80019ce:	687b      	ldr	r3, [r7, #4]
 80019d0:	3322      	adds	r3, #34	@ 0x22
 80019d2:	623b      	str	r3, [r7, #32]

	/* construct FF N_PDU and pack it into a CAN frame */
	frame.buf[i++] = (I15765_PDU_FF << 4) | (mftb->msg.buf_len >> 8);
 80019d4:	687b      	ldr	r3, [r7, #4]
 80019d6:	8a1b      	ldrh	r3, [r3, #16]
 80019d8:	0a1b      	lsrs	r3, r3, #8
 80019da:	b29b      	uxth	r3, r3
 80019dc:	b2da      	uxtb	r2, r3
 80019de:	68f9      	ldr	r1, [r7, #12]
 80019e0:	f897 3027 	ldrb.w	r3, [r7, #39]	@ 0x27
 80019e4:	1c58      	adds	r0, r3, #1
 80019e6:	f887 0027 	strb.w	r0, [r7, #39]	@ 0x27
 80019ea:	440b      	add	r3, r1
 80019ec:	f042 0210 	orr.w	r2, r2, #16
 80019f0:	b2d2      	uxtb	r2, r2
 80019f2:	701a      	strb	r2, [r3, #0]
	frame.buf[i++] = (uint8_t)mftb->msg.buf_len;
 80019f4:	687b      	ldr	r3, [r7, #4]
 80019f6:	8a19      	ldrh	r1, [r3, #16]
 80019f8:	68fa      	ldr	r2, [r7, #12]
 80019fa:	f897 3027 	ldrb.w	r3, [r7, #39]	@ 0x27
 80019fe:	1c58      	adds	r0, r3, #1
 8001a00:	f887 0027 	strb.w	r0, [r7, #39]	@ 0x27
 8001a04:	4413      	add	r3, r2
 8001a06:	b2ca      	uxtb	r2, r1
 8001a08:	701a      	strb	r2, [r3, #0]

	/* copy over the data */
	while(i < 8)
 8001a0a:	e00b      	b.n	8001a24 <i15765_tx_ff+0x78>
		frame.buf[i++] = *ptr++;
 8001a0c:	6a3b      	ldr	r3, [r7, #32]
 8001a0e:	1c5a      	adds	r2, r3, #1
 8001a10:	623a      	str	r2, [r7, #32]
 8001a12:	68f9      	ldr	r1, [r7, #12]
 8001a14:	f897 2027 	ldrb.w	r2, [r7, #39]	@ 0x27
 8001a18:	1c50      	adds	r0, r2, #1
 8001a1a:	f887 0027 	strb.w	r0, [r7, #39]	@ 0x27
 8001a1e:	440a      	add	r2, r1
 8001a20:	781b      	ldrb	r3, [r3, #0]
 8001a22:	7013      	strb	r3, [r2, #0]
	while(i < 8)
 8001a24:	f897 3027 	ldrb.w	r3, [r7, #39]	@ 0x27
 8001a28:	2b07      	cmp	r3, #7
 8001a2a:	d9ef      	bls.n	8001a0c <i15765_tx_ff+0x60>

	/* FF's are always 8 bytes long */
	frame.buf_len = 8;
 8001a2c:	2308      	movs	r3, #8
 8001a2e:	823b      	strh	r3, [r7, #16]

	/* transmit the CAN frame, testing to see if it was sent correctly */
	if(i15765_tx(&frame) == 0)
 8001a30:	f107 0308 	add.w	r3, r7, #8
 8001a34:	4618      	mov	r0, r3
 8001a36:	f7ff ff2d 	bl	8001894 <i15765_tx>
 8001a3a:	4603      	mov	r3, r0
 8001a3c:	2b00      	cmp	r3, #0
 8001a3e:	d10a      	bne.n	8001a56 <i15765_tx_ff+0xaa>
	{

		mftb->state = STATE_WT_FC;
 8001a40:	687b      	ldr	r3, [r7, #4]
 8001a42:	2204      	movs	r2, #4
 8001a44:	761a      	strb	r2, [r3, #24]
		mftb->timeout = TIMEOUT_FC_S;
 8001a46:	4b06      	ldr	r3, [pc, #24]	@ (8001a60 <i15765_tx_ff+0xb4>)
 8001a48:	881a      	ldrh	r2, [r3, #0]
 8001a4a:	687b      	ldr	r3, [r7, #4]
 8001a4c:	841a      	strh	r2, [r3, #32]
		mftb->msg.buf = ptr;
 8001a4e:	687b      	ldr	r3, [r7, #4]
 8001a50:	6a3a      	ldr	r2, [r7, #32]
 8001a52:	60da      	str	r2, [r3, #12]
	}

	return;
 8001a54:	bf00      	nop
 8001a56:	bf00      	nop
}
 8001a58:	372c      	adds	r7, #44	@ 0x2c
 8001a5a:	46bd      	mov	sp, r7
 8001a5c:	bd90      	pop	{r4, r7, pc}
 8001a5e:	bf00      	nop
 8001a60:	08005dd4 	.word	0x08005dd4

08001a64 <i15765_tx_cf>:
/*
** Transmit a consecutive frame.
** INPUT: mftb - pointer to the i15765 multiframe buffer
*/
void i15765_tx_cf(i15765_mft_t *mftb)
{
 8001a64:	b590      	push	{r4, r7, lr}
 8001a66:	b08d      	sub	sp, #52	@ 0x34
 8001a68:	af00      	add	r7, sp, #0
 8001a6a:	6078      	str	r0, [r7, #4]

	uint8_t min;
	uint8_t i = 0;
 8001a6c:	2300      	movs	r3, #0
 8001a6e:	f887 302f 	strb.w	r3, [r7, #47]	@ 0x2f
	uint16_t rem;
	uint8_t buf[8];
	i15765_t frame;

	/* copy over message */
	frame = mftb->msg;
 8001a72:	687b      	ldr	r3, [r7, #4]
 8001a74:	f107 040c 	add.w	r4, r7, #12
 8001a78:	3308      	adds	r3, #8
 8001a7a:	cb0f      	ldmia	r3, {r0, r1, r2, r3}
 8001a7c:	e884 000f 	stmia.w	r4, {r0, r1, r2, r3}
	frame.buf = buf;
 8001a80:	f107 031c 	add.w	r3, r7, #28
 8001a84:	613b      	str	r3, [r7, #16]
	ptr = mftb->msg.buf;
 8001a86:	687b      	ldr	r3, [r7, #4]
 8001a88:	68db      	ldr	r3, [r3, #12]
 8001a8a:	62bb      	str	r3, [r7, #40]	@ 0x28

	/* update separation time */
	if(mftb->st_cnt)
 8001a8c:	687b      	ldr	r3, [r7, #4]
 8001a8e:	889b      	ldrh	r3, [r3, #4]
 8001a90:	2b00      	cmp	r3, #0
 8001a92:	d006      	beq.n	8001aa2 <i15765_tx_cf+0x3e>
	{

		/* delay */
		mftb->st_cnt--;
 8001a94:	687b      	ldr	r3, [r7, #4]
 8001a96:	889b      	ldrh	r3, [r3, #4]
 8001a98:	3b01      	subs	r3, #1
 8001a9a:	b29a      	uxth	r2, r3
 8001a9c:	687b      	ldr	r3, [r7, #4]
 8001a9e:	809a      	strh	r2, [r3, #4]
		return;
 8001aa0:	e082      	b.n	8001ba8 <i15765_tx_cf+0x144>
	}
	else
	{

		/* transmit */
		mftb->st_cnt = mftb->st;
 8001aa2:	687b      	ldr	r3, [r7, #4]
 8001aa4:	885a      	ldrh	r2, [r3, #2]
 8001aa6:	687b      	ldr	r3, [r7, #4]
 8001aa8:	809a      	strh	r2, [r3, #4]
	}

	/* load PDU type */
	frame.buf[i++] = (I15765_PDU_CF << 4) | (mftb->sn++ & 0xf);
 8001aaa:	687b      	ldr	r3, [r7, #4]
 8001aac:	799b      	ldrb	r3, [r3, #6]
 8001aae:	1c5a      	adds	r2, r3, #1
 8001ab0:	b2d1      	uxtb	r1, r2
 8001ab2:	687a      	ldr	r2, [r7, #4]
 8001ab4:	7191      	strb	r1, [r2, #6]
 8001ab6:	b25b      	sxtb	r3, r3
 8001ab8:	f003 030f 	and.w	r3, r3, #15
 8001abc:	b25b      	sxtb	r3, r3
 8001abe:	f043 0320 	orr.w	r3, r3, #32
 8001ac2:	b259      	sxtb	r1, r3
 8001ac4:	693a      	ldr	r2, [r7, #16]
 8001ac6:	f897 302f 	ldrb.w	r3, [r7, #47]	@ 0x2f
 8001aca:	1c58      	adds	r0, r3, #1
 8001acc:	f887 002f 	strb.w	r0, [r7, #47]	@ 0x2f
 8001ad0:	4413      	add	r3, r2
 8001ad2:	b2ca      	uxtb	r2, r1
 8001ad4:	701a      	strb	r2, [r3, #0]

	/* how much data can we (or need we) copy over? */
	rem = mftb->msg.buf_len - (mftb->msg.buf - mftb->buf);
 8001ad6:	687b      	ldr	r3, [r7, #4]
 8001ad8:	8a1a      	ldrh	r2, [r3, #16]
 8001ada:	687b      	ldr	r3, [r7, #4]
 8001adc:	68d9      	ldr	r1, [r3, #12]
 8001ade:	687b      	ldr	r3, [r7, #4]
 8001ae0:	3322      	adds	r3, #34	@ 0x22
 8001ae2:	1acb      	subs	r3, r1, r3
 8001ae4:	b29b      	uxth	r3, r3
 8001ae6:	1ad3      	subs	r3, r2, r3
 8001ae8:	84fb      	strh	r3, [r7, #38]	@ 0x26
	min = (uint8_t)MIN(rem, 8 - i);
 8001aea:	8cfa      	ldrh	r2, [r7, #38]	@ 0x26
 8001aec:	f897 302f 	ldrb.w	r3, [r7, #47]	@ 0x2f
 8001af0:	f1c3 0308 	rsb	r3, r3, #8
 8001af4:	429a      	cmp	r2, r3
 8001af6:	da02      	bge.n	8001afe <i15765_tx_cf+0x9a>
 8001af8:	8cfb      	ldrh	r3, [r7, #38]	@ 0x26
 8001afa:	b2db      	uxtb	r3, r3
 8001afc:	e004      	b.n	8001b08 <i15765_tx_cf+0xa4>
 8001afe:	f897 302f 	ldrb.w	r3, [r7, #47]	@ 0x2f
 8001b02:	f1c3 0308 	rsb	r3, r3, #8
 8001b06:	b2db      	uxtb	r3, r3
 8001b08:	f887 3025 	strb.w	r3, [r7, #37]	@ 0x25

	/* add in the PDU field (and maybe AE) */
	min += i;
 8001b0c:	f897 2025 	ldrb.w	r2, [r7, #37]	@ 0x25
 8001b10:	f897 302f 	ldrb.w	r3, [r7, #47]	@ 0x2f
 8001b14:	4413      	add	r3, r2
 8001b16:	f887 3025 	strb.w	r3, [r7, #37]	@ 0x25

	/* copy  over the data */
	while(i < min)
 8001b1a:	e00b      	b.n	8001b34 <i15765_tx_cf+0xd0>
		frame.buf[i++] = *ptr++;
 8001b1c:	6abb      	ldr	r3, [r7, #40]	@ 0x28
 8001b1e:	1c5a      	adds	r2, r3, #1
 8001b20:	62ba      	str	r2, [r7, #40]	@ 0x28
 8001b22:	6939      	ldr	r1, [r7, #16]
 8001b24:	f897 202f 	ldrb.w	r2, [r7, #47]	@ 0x2f
 8001b28:	1c50      	adds	r0, r2, #1
 8001b2a:	f887 002f 	strb.w	r0, [r7, #47]	@ 0x2f
 8001b2e:	440a      	add	r2, r1
 8001b30:	781b      	ldrb	r3, [r3, #0]
 8001b32:	7013      	strb	r3, [r2, #0]
	while(i < min)
 8001b34:	f897 202f 	ldrb.w	r2, [r7, #47]	@ 0x2f
 8001b38:	f897 3025 	ldrb.w	r3, [r7, #37]	@ 0x25
 8001b3c:	429a      	cmp	r2, r3
 8001b3e:	d3ed      	bcc.n	8001b1c <i15765_tx_cf+0xb8>

	/* FF's are always 8 bytes long */
	frame.buf_len = min;
 8001b40:	f897 3025 	ldrb.w	r3, [r7, #37]	@ 0x25
 8001b44:	b29b      	uxth	r3, r3
 8001b46:	82bb      	strh	r3, [r7, #20]

	/* transmit the CAN frame, testing to see if it was sent correctly */
	if(i15765_tx(&frame) == 0)
 8001b48:	f107 030c 	add.w	r3, r7, #12
 8001b4c:	4618      	mov	r0, r3
 8001b4e:	f7ff fea1 	bl	8001894 <i15765_tx>
 8001b52:	4603      	mov	r3, r0
 8001b54:	2b00      	cmp	r3, #0
 8001b56:	d10f      	bne.n	8001b78 <i15765_tx_cf+0x114>
	{

		mftb->timeout = TIMEOUT_CF_S;
 8001b58:	4b15      	ldr	r3, [pc, #84]	@ (8001bb0 <i15765_tx_cf+0x14c>)
 8001b5a:	881a      	ldrh	r2, [r3, #0]
 8001b5c:	687b      	ldr	r3, [r7, #4]
 8001b5e:	841a      	strh	r2, [r3, #32]
		mftb->msg.buf = ptr;
 8001b60:	687b      	ldr	r3, [r7, #4]
 8001b62:	6aba      	ldr	r2, [r7, #40]	@ 0x28
 8001b64:	60da      	str	r2, [r3, #12]

		/* if bs is zero, then transmit away, else check how many we have left */
		mftb->bs_cnt--;
 8001b66:	687b      	ldr	r3, [r7, #4]
 8001b68:	785b      	ldrb	r3, [r3, #1]
 8001b6a:	3b01      	subs	r3, #1
 8001b6c:	b2da      	uxtb	r2, r3
 8001b6e:	687b      	ldr	r3, [r7, #4]
 8001b70:	705a      	strb	r2, [r3, #1]
		if(mftb->bs && (mftb->bs_cnt == 0))
 8001b72:	687b      	ldr	r3, [r7, #4]
 8001b74:	781b      	ldrb	r3, [r3, #0]
 8001b76:	2b00      	cmp	r3, #0
		{
			//			mftb->state = STATE_WT_FC;//qiaoxu  Ϊ���ó����ķ��ʹ���8֡
		}
	}

	rem = mftb->msg.buf_len - (mftb->msg.buf - mftb->buf);
 8001b78:	687b      	ldr	r3, [r7, #4]
 8001b7a:	8a1a      	ldrh	r2, [r3, #16]
 8001b7c:	687b      	ldr	r3, [r7, #4]
 8001b7e:	68d9      	ldr	r1, [r3, #12]
 8001b80:	687b      	ldr	r3, [r7, #4]
 8001b82:	3322      	adds	r3, #34	@ 0x22
 8001b84:	1acb      	subs	r3, r1, r3
 8001b86:	b29b      	uxth	r3, r3
 8001b88:	1ad3      	subs	r3, r2, r3
 8001b8a:	84fb      	strh	r3, [r7, #38]	@ 0x26
	if(rem == 0)
 8001b8c:	8cfb      	ldrh	r3, [r7, #38]	@ 0x26
 8001b8e:	2b00      	cmp	r3, #0
 8001b90:	d109      	bne.n	8001ba6 <i15765_tx_cf+0x142>
	{

		*mftb->status = I15765_SENT;
 8001b92:	687b      	ldr	r3, [r7, #4]
 8001b94:	69db      	ldr	r3, [r3, #28]
 8001b96:	2200      	movs	r2, #0
 8001b98:	701a      	strb	r2, [r3, #0]
		mftb->status = &i15765_tmp;
 8001b9a:	687b      	ldr	r3, [r7, #4]
 8001b9c:	4a05      	ldr	r2, [pc, #20]	@ (8001bb4 <i15765_tx_cf+0x150>)
 8001b9e:	61da      	str	r2, [r3, #28]
		mftb->state = STATE_IDLE;
 8001ba0:	687b      	ldr	r3, [r7, #4]
 8001ba2:	2200      	movs	r2, #0
 8001ba4:	761a      	strb	r2, [r3, #24]
	}

	return;
 8001ba6:	bf00      	nop
}
 8001ba8:	3734      	adds	r7, #52	@ 0x34
 8001baa:	46bd      	mov	sp, r7
 8001bac:	bd90      	pop	{r4, r7, pc}
 8001bae:	bf00      	nop
 8001bb0:	08005dd6 	.word	0x08005dd6
 8001bb4:	20000e74 	.word	0x20000e74

08001bb8 <i15765_tx_mf>:
** INPUT:  msg - pointer to the i15765 message to be transmitted
**         status - pointer to user RAM location for status feedback
**
*/
void i15765_tx_mf(i15765_t *msg, uint8_t *status)
{
 8001bb8:	b590      	push	{r4, r7, lr}
 8001bba:	b085      	sub	sp, #20
 8001bbc:	af00      	add	r7, sp, #0
 8001bbe:	6078      	str	r0, [r7, #4]
 8001bc0:	6039      	str	r1, [r7, #0]

	/* delete any mf buffers with matching address information */
//	i15765_mftb_del(msg);

	/* assume failure */
	*status = I15765_FAILED;
 8001bc2:	683b      	ldr	r3, [r7, #0]
 8001bc4:	2202      	movs	r2, #2
 8001bc6:	701a      	strb	r2, [r3, #0]

	/* find an available spot for this message */
	if(i15765_mftb_get(&mftb))
 8001bc8:	f107 0308 	add.w	r3, r7, #8
 8001bcc:	4618      	mov	r0, r3
 8001bce:	f7ff fdad 	bl	800172c <i15765_mftb_get>
 8001bd2:	4603      	mov	r3, r0
 8001bd4:	2b00      	cmp	r3, #0
 8001bd6:	d136      	bne.n	8001c46 <i15765_tx_mf+0x8e>
		return;

	/* there was room, so update status */
	*status = I15765_SENDING;
 8001bd8:	683b      	ldr	r3, [r7, #0]
 8001bda:	2201      	movs	r2, #1
 8001bdc:	701a      	strb	r2, [r3, #0]

	/* copy over the data */
	for(i = 0; i < msg->buf_len; i++)
 8001bde:	2300      	movs	r3, #0
 8001be0:	81fb      	strh	r3, [r7, #14]
 8001be2:	e00d      	b.n	8001c00 <i15765_tx_mf+0x48>
		mftb->buf[i] = msg->buf[i];
 8001be4:	687b      	ldr	r3, [r7, #4]
 8001be6:	685a      	ldr	r2, [r3, #4]
 8001be8:	89fb      	ldrh	r3, [r7, #14]
 8001bea:	18d1      	adds	r1, r2, r3
 8001bec:	68ba      	ldr	r2, [r7, #8]
 8001bee:	89fb      	ldrh	r3, [r7, #14]
 8001bf0:	7809      	ldrb	r1, [r1, #0]
 8001bf2:	4413      	add	r3, r2
 8001bf4:	460a      	mov	r2, r1
 8001bf6:	f883 2022 	strb.w	r2, [r3, #34]	@ 0x22
	for(i = 0; i < msg->buf_len; i++)
 8001bfa:	89fb      	ldrh	r3, [r7, #14]
 8001bfc:	3301      	adds	r3, #1
 8001bfe:	81fb      	strh	r3, [r7, #14]
 8001c00:	687b      	ldr	r3, [r7, #4]
 8001c02:	891b      	ldrh	r3, [r3, #8]
 8001c04:	89fa      	ldrh	r2, [r7, #14]
 8001c06:	429a      	cmp	r2, r3
 8001c08:	d3ec      	bcc.n	8001be4 <i15765_tx_mf+0x2c>

	/* copy over message */
	mftb->msg = *msg;
 8001c0a:	68bb      	ldr	r3, [r7, #8]
 8001c0c:	687a      	ldr	r2, [r7, #4]
 8001c0e:	f103 0408 	add.w	r4, r3, #8
 8001c12:	4613      	mov	r3, r2
 8001c14:	cb0f      	ldmia	r3, {r0, r1, r2, r3}
 8001c16:	e884 000f 	stmia.w	r4, {r0, r1, r2, r3}
	mftb->msg.buf = mftb->buf;
 8001c1a:	68ba      	ldr	r2, [r7, #8]
 8001c1c:	68bb      	ldr	r3, [r7, #8]
 8001c1e:	3222      	adds	r2, #34	@ 0x22
 8001c20:	60da      	str	r2, [r3, #12]

	/* set state to wait for a flow control PDU */
	mftb->state = STATE_TX_FF;
 8001c22:	68bb      	ldr	r3, [r7, #8]
 8001c24:	2201      	movs	r2, #1
 8001c26:	761a      	strb	r2, [r3, #24]
	mftb->sn = 1;
 8001c28:	68bb      	ldr	r3, [r7, #8]
 8001c2a:	2201      	movs	r2, #1
 8001c2c:	719a      	strb	r2, [r3, #6]

	mftb->status = status;
 8001c2e:	68bb      	ldr	r3, [r7, #8]
 8001c30:	683a      	ldr	r2, [r7, #0]
 8001c32:	61da      	str	r2, [r3, #28]

	/* transmit the CAN frame, testing to see if it was sent correctly */
	mftb->timeout = TIMEOUT_TX_S;
 8001c34:	68bb      	ldr	r3, [r7, #8]
 8001c36:	4a06      	ldr	r2, [pc, #24]	@ (8001c50 <i15765_tx_mf+0x98>)
 8001c38:	8812      	ldrh	r2, [r2, #0]
 8001c3a:	841a      	strh	r2, [r3, #32]
	i15765_tx_ff(mftb);
 8001c3c:	68bb      	ldr	r3, [r7, #8]
 8001c3e:	4618      	mov	r0, r3
 8001c40:	f7ff feb4 	bl	80019ac <i15765_tx_ff>
 8001c44:	e000      	b.n	8001c48 <i15765_tx_mf+0x90>
		return;
 8001c46:	bf00      	nop
}
 8001c48:	3714      	adds	r7, #20
 8001c4a:	46bd      	mov	sp, r7
 8001c4c:	bd90      	pop	{r4, r7, pc}
 8001c4e:	bf00      	nop
 8001c50:	08005dd0 	.word	0x08005dd0

08001c54 <i15765_tx_fc>:
** Transmit a flow control frame and updates the status of mfrb. Reception
** will be paused until the FC has been transmitted.
** INPUT: mfrb - pointer multiframe receive buffer
*/
void i15765_tx_fc(i15765_mfr_t *mfrb)
{
 8001c54:	b580      	push	{r7, lr}
 8001c56:	b08a      	sub	sp, #40	@ 0x28
 8001c58:	af00      	add	r7, sp, #0
 8001c5a:	6078      	str	r0, [r7, #4]
	uint8_t fs;
	i15765_t msg;
	uint8_t buf[8];

	/* get the FF_DL and check for potential buffer overflow */
	if(mfrb->msg.buf_len > I15765CFG_MF_RX_BUF_SIZE)
 8001c5c:	687b      	ldr	r3, [r7, #4]
 8001c5e:	899b      	ldrh	r3, [r3, #12]
 8001c60:	f5b3 6f00 	cmp.w	r3, #2048	@ 0x800
 8001c64:	d906      	bls.n	8001c74 <i15765_tx_fc+0x20>
	{

		fs = I15765_FS_OVFLW;
 8001c66:	2302      	movs	r3, #2
 8001c68:	f887 3027 	strb.w	r3, [r7, #39]	@ 0x27
		mfrb->state = STATE_TX_OVFLW;
 8001c6c:	687b      	ldr	r3, [r7, #4]
 8001c6e:	2207      	movs	r2, #7
 8001c70:	751a      	strb	r2, [r3, #20]
 8001c72:	e005      	b.n	8001c80 <i15765_tx_fc+0x2c>

	}
	else
	{

		fs = I15765_FS_CTS;		//
 8001c74:	2300      	movs	r3, #0
 8001c76:	f887 3027 	strb.w	r3, [r7, #39]	@ 0x27
//		fs = I15765_FS_WT;		//wait
		mfrb->state = STATE_TX_CTS;
 8001c7a:	687b      	ldr	r3, [r7, #4]
 8001c7c:	2206      	movs	r2, #6
 8001c7e:	751a      	strb	r2, [r3, #20]
	}

	/* pack the pci */
	msg.buf = buf;
 8001c80:	f107 030c 	add.w	r3, r7, #12
 8001c84:	61bb      	str	r3, [r7, #24]
	msg.buf[0] = (I15765_PDU_FC << 4) | fs;
 8001c86:	69bb      	ldr	r3, [r7, #24]
 8001c88:	f897 2027 	ldrb.w	r2, [r7, #39]	@ 0x27
 8001c8c:	f042 0230 	orr.w	r2, r2, #48	@ 0x30
 8001c90:	b2d2      	uxtb	r2, r2
 8001c92:	701a      	strb	r2, [r3, #0]
	msg.buf[1] = BS;	//qiaoxu modify
 8001c94:	69bb      	ldr	r3, [r7, #24]
 8001c96:	3301      	adds	r3, #1
 8001c98:	4a17      	ldr	r2, [pc, #92]	@ (8001cf8 <i15765_tx_fc+0xa4>)
 8001c9a:	7812      	ldrb	r2, [r2, #0]
 8001c9c:	701a      	strb	r2, [r3, #0]
	msg.buf[2] = STmin; //qiaoxu modify
 8001c9e:	69bb      	ldr	r3, [r7, #24]
 8001ca0:	3302      	adds	r3, #2
 8001ca2:	4a16      	ldr	r2, [pc, #88]	@ (8001cfc <i15765_tx_fc+0xa8>)
 8001ca4:	7812      	ldrb	r2, [r2, #0]
 8001ca6:	701a      	strb	r2, [r3, #0]
	msg.buf_len = 3;
 8001ca8:	2303      	movs	r3, #3
 8001caa:	83bb      	strh	r3, [r7, #28]

	msg.sa = i15765_sa;
 8001cac:	4b14      	ldr	r3, [pc, #80]	@ (8001d00 <i15765_tx_fc+0xac>)
 8001cae:	781b      	ldrb	r3, [r3, #0]
 8001cb0:	753b      	strb	r3, [r7, #20]
	msg.ta = mfrb->msg.sa;
 8001cb2:	687b      	ldr	r3, [r7, #4]
 8001cb4:	791b      	ldrb	r3, [r3, #4]
 8001cb6:	757b      	strb	r3, [r7, #21]
	msg.tat = mfrb->msg.tat;
 8001cb8:	687b      	ldr	r3, [r7, #4]
 8001cba:	79db      	ldrb	r3, [r3, #7]
 8001cbc:	75fb      	strb	r3, [r7, #23]

	/* set pri same as received FF */
	msg.pri = mfrb->msg.pri;
 8001cbe:	687b      	ldr	r3, [r7, #4]
 8001cc0:	799b      	ldrb	r3, [r3, #6]
 8001cc2:	75bb      	strb	r3, [r7, #22]

	/* send the message */
	if(i15765_tx(&msg) == 0)
 8001cc4:	f107 0314 	add.w	r3, r7, #20
 8001cc8:	4618      	mov	r0, r3
 8001cca:	f7ff fde3 	bl	8001894 <i15765_tx>
 8001cce:	4603      	mov	r3, r0
 8001cd0:	2b00      	cmp	r3, #0
 8001cd2:	d10c      	bne.n	8001cee <i15765_tx_fc+0x9a>
	{
		/* transmission successful */
		mfrb->timeout = TIMEOUT_CF_R;
 8001cd4:	4b0b      	ldr	r3, [pc, #44]	@ (8001d04 <i15765_tx_fc+0xb0>)
 8001cd6:	881a      	ldrh	r2, [r3, #0]
 8001cd8:	687b      	ldr	r3, [r7, #4]
 8001cda:	82da      	strh	r2, [r3, #22]
		mfrb->state = (mfrb->state == STATE_TX_CTS) ? STATE_WT_CF : STATE_IDLE;
 8001cdc:	687b      	ldr	r3, [r7, #4]
 8001cde:	7d1b      	ldrb	r3, [r3, #20]
 8001ce0:	2b06      	cmp	r3, #6
 8001ce2:	d101      	bne.n	8001ce8 <i15765_tx_fc+0x94>
 8001ce4:	2205      	movs	r2, #5
 8001ce6:	e000      	b.n	8001cea <i15765_tx_fc+0x96>
 8001ce8:	2200      	movs	r2, #0
 8001cea:	687b      	ldr	r3, [r7, #4]
 8001cec:	751a      	strb	r2, [r3, #20]
	}
}
 8001cee:	bf00      	nop
 8001cf0:	3728      	adds	r7, #40	@ 0x28
 8001cf2:	46bd      	mov	sp, r7
 8001cf4:	bd80      	pop	{r7, pc}
 8001cf6:	bf00      	nop
 8001cf8:	08005ded 	.word	0x08005ded
 8001cfc:	08005dee 	.word	0x08005dee
 8001d00:	20000008 	.word	0x20000008
 8001d04:	08005dd8 	.word	0x08005dd8

08001d08 <i15765_rx_sf>:
/*
** Handles a recieved single frame
** INPUT: msg - pointer to the received message
*/
void i15765_rx_sf(i15765_t *msg)
{
 8001d08:	b580      	push	{r7, lr}
 8001d0a:	b082      	sub	sp, #8
 8001d0c:	af00      	add	r7, sp, #0
 8001d0e:	6078      	str	r0, [r7, #4]

	/* ignore message if errors are present */
	if((msg->buf[0] == 0) || (msg->buf[0] > (msg->buf_len - 1)))
 8001d10:	687b      	ldr	r3, [r7, #4]
 8001d12:	685b      	ldr	r3, [r3, #4]
 8001d14:	781b      	ldrb	r3, [r3, #0]
 8001d16:	2b00      	cmp	r3, #0
 8001d18:	d015      	beq.n	8001d46 <i15765_rx_sf+0x3e>
 8001d1a:	687b      	ldr	r3, [r7, #4]
 8001d1c:	891b      	ldrh	r3, [r3, #8]
 8001d1e:	687a      	ldr	r2, [r7, #4]
 8001d20:	6852      	ldr	r2, [r2, #4]
 8001d22:	7812      	ldrb	r2, [r2, #0]
 8001d24:	4293      	cmp	r3, r2
 8001d26:	d90e      	bls.n	8001d46 <i15765_rx_sf+0x3e>
	{
		return;
	}

	/* message length */
	msg->buf_len = msg->buf[0];
 8001d28:	687b      	ldr	r3, [r7, #4]
 8001d2a:	685b      	ldr	r3, [r3, #4]
 8001d2c:	781b      	ldrb	r3, [r3, #0]
 8001d2e:	461a      	mov	r2, r3
 8001d30:	687b      	ldr	r3, [r7, #4]
 8001d32:	811a      	strh	r2, [r3, #8]

	/* skip PCI field */
	msg->buf++;
 8001d34:	687b      	ldr	r3, [r7, #4]
 8001d36:	685b      	ldr	r3, [r3, #4]
 8001d38:	1c5a      	adds	r2, r3, #1
 8001d3a:	687b      	ldr	r3, [r7, #4]
 8001d3c:	605a      	str	r2, [r3, #4]

	i15765app_process(msg);
 8001d3e:	6878      	ldr	r0, [r7, #4]
 8001d40:	f000 fb10 	bl	8002364 <i15765app_process>
 8001d44:	e000      	b.n	8001d48 <i15765_rx_sf+0x40>
		return;
 8001d46:	bf00      	nop
}
 8001d48:	3708      	adds	r7, #8
 8001d4a:	46bd      	mov	sp, r7
 8001d4c:	bd80      	pop	{r7, pc}
	...

08001d50 <i15765_rx_ff>:
/*
** Handles a recieved first frame.
** INPUT: msg - pointer to the received message segment
*/
void i15765_rx_ff(i15765_t *msg)
{
 8001d50:	b590      	push	{r4, r7, lr}
 8001d52:	b085      	sub	sp, #20
 8001d54:	af00      	add	r7, sp, #0
 8001d56:	6078      	str	r0, [r7, #4]
	uint16_t ff_dl;
	i15765_mfr_t *mfrb;

	//qiaoxu   ɾ��
	/* delete any mf buffers with matching address information */
	i15765_mfrb_del(msg);
 8001d58:	6878      	ldr	r0, [r7, #4]
 8001d5a:	f7ff fd13 	bl	8001784 <i15765_mfrb_del>

	/* find an available spot for this message */
	if(i15765_mfrb_get(&mfrb))
 8001d5e:	f107 0308 	add.w	r3, r7, #8
 8001d62:	4618      	mov	r0, r3
 8001d64:	f7ff fcb6 	bl	80016d4 <i15765_mfrb_get>
 8001d68:	4603      	mov	r3, r0
 8001d6a:	2b00      	cmp	r3, #0
 8001d6c:	d14e      	bne.n	8001e0c <i15765_rx_ff+0xbc>
		return;

	/* first frame data length */
	ff_dl = ((msg->buf[0] & 0xf) << 8) | msg->buf[1];
 8001d6e:	687b      	ldr	r3, [r7, #4]
 8001d70:	685b      	ldr	r3, [r3, #4]
 8001d72:	781b      	ldrb	r3, [r3, #0]
 8001d74:	b21b      	sxth	r3, r3
 8001d76:	021b      	lsls	r3, r3, #8
 8001d78:	b21b      	sxth	r3, r3
 8001d7a:	f403 6370 	and.w	r3, r3, #3840	@ 0xf00
 8001d7e:	b21a      	sxth	r2, r3
 8001d80:	687b      	ldr	r3, [r7, #4]
 8001d82:	685b      	ldr	r3, [r3, #4]
 8001d84:	3301      	adds	r3, #1
 8001d86:	781b      	ldrb	r3, [r3, #0]
 8001d88:	b21b      	sxth	r3, r3
 8001d8a:	4313      	orrs	r3, r2
 8001d8c:	b21b      	sxth	r3, r3
 8001d8e:	81bb      	strh	r3, [r7, #12]

	/* if the total size could fit in an SF PDU, ignore */
	if(ff_dl <= 7)
 8001d90:	89bb      	ldrh	r3, [r7, #12]
 8001d92:	2b07      	cmp	r3, #7
 8001d94:	d93c      	bls.n	8001e10 <i15765_rx_ff+0xc0>
		return;

	/* skip PCI field */
	msg->buf += 2;
 8001d96:	687b      	ldr	r3, [r7, #4]
 8001d98:	685b      	ldr	r3, [r3, #4]
 8001d9a:	1c9a      	adds	r2, r3, #2
 8001d9c:	687b      	ldr	r3, [r7, #4]
 8001d9e:	605a      	str	r2, [r3, #4]
	msg->buf_len -= 2;
 8001da0:	687b      	ldr	r3, [r7, #4]
 8001da2:	891b      	ldrh	r3, [r3, #8]
 8001da4:	3b02      	subs	r3, #2
 8001da6:	b29a      	uxth	r2, r3
 8001da8:	687b      	ldr	r3, [r7, #4]
 8001daa:	811a      	strh	r2, [r3, #8]

	/* buffer the necessary info */
	mfrb->sn = 0;
 8001dac:	68bb      	ldr	r3, [r7, #8]
 8001dae:	2200      	movs	r2, #0
 8001db0:	701a      	strb	r2, [r3, #0]
	mfrb->msg = *msg;
 8001db2:	68bb      	ldr	r3, [r7, #8]
 8001db4:	687a      	ldr	r2, [r7, #4]
 8001db6:	1d1c      	adds	r4, r3, #4
 8001db8:	4613      	mov	r3, r2
 8001dba:	cb0f      	ldmia	r3, {r0, r1, r2, r3}
 8001dbc:	e884 000f 	stmia.w	r4, {r0, r1, r2, r3}
	mfrb->msg.buf_len = ff_dl;
 8001dc0:	68bb      	ldr	r3, [r7, #8]
 8001dc2:	89ba      	ldrh	r2, [r7, #12]
 8001dc4:	819a      	strh	r2, [r3, #12]

	/* reset buf pointer and store data that was recieved with the FF */
	mfrb->msg.buf = mfrb->buf;
 8001dc6:	68ba      	ldr	r2, [r7, #8]
 8001dc8:	68bb      	ldr	r3, [r7, #8]
 8001dca:	3218      	adds	r2, #24
 8001dcc:	609a      	str	r2, [r3, #8]
	for(i = 0; i < msg->buf_len; i++)
 8001dce:	2300      	movs	r3, #0
 8001dd0:	73fb      	strb	r3, [r7, #15]
 8001dd2:	e00c      	b.n	8001dee <i15765_rx_ff+0x9e>
		*mfrb->msg.buf++ = msg->buf[i];
 8001dd4:	687b      	ldr	r3, [r7, #4]
 8001dd6:	685a      	ldr	r2, [r3, #4]
 8001dd8:	7bfb      	ldrb	r3, [r7, #15]
 8001dda:	18d1      	adds	r1, r2, r3
 8001ddc:	68ba      	ldr	r2, [r7, #8]
 8001dde:	6893      	ldr	r3, [r2, #8]
 8001de0:	1c58      	adds	r0, r3, #1
 8001de2:	6090      	str	r0, [r2, #8]
 8001de4:	780a      	ldrb	r2, [r1, #0]
 8001de6:	701a      	strb	r2, [r3, #0]
	for(i = 0; i < msg->buf_len; i++)
 8001de8:	7bfb      	ldrb	r3, [r7, #15]
 8001dea:	3301      	adds	r3, #1
 8001dec:	73fb      	strb	r3, [r7, #15]
 8001dee:	7bfb      	ldrb	r3, [r7, #15]
 8001df0:	b29a      	uxth	r2, r3
 8001df2:	687b      	ldr	r3, [r7, #4]
 8001df4:	891b      	ldrh	r3, [r3, #8]
 8001df6:	429a      	cmp	r2, r3
 8001df8:	d3ec      	bcc.n	8001dd4 <i15765_rx_ff+0x84>

	/* transmit a flow control frame (the status will be updated based on FS) */
	mfrb->timeout = TIMEOUT_TX_R;
 8001dfa:	68bb      	ldr	r3, [r7, #8]
 8001dfc:	4a06      	ldr	r2, [pc, #24]	@ (8001e18 <i15765_rx_ff+0xc8>)
 8001dfe:	8812      	ldrh	r2, [r2, #0]
 8001e00:	82da      	strh	r2, [r3, #22]
	i15765_tx_fc(mfrb);
 8001e02:	68bb      	ldr	r3, [r7, #8]
 8001e04:	4618      	mov	r0, r3
 8001e06:	f7ff ff25 	bl	8001c54 <i15765_tx_fc>
 8001e0a:	e002      	b.n	8001e12 <i15765_rx_ff+0xc2>
		return;
 8001e0c:	bf00      	nop
 8001e0e:	e000      	b.n	8001e12 <i15765_rx_ff+0xc2>
		return;
 8001e10:	bf00      	nop
}
 8001e12:	3714      	adds	r7, #20
 8001e14:	46bd      	mov	sp, r7
 8001e16:	bd90      	pop	{r4, r7, pc}
 8001e18:	08005dd2 	.word	0x08005dd2

08001e1c <i15765_rx_cf>:
/*
** Handles a recieved consecutive frame
** INPUT: msg - pointer to the received message
*/
void i15765_rx_cf(i15765_t *msg)
{
 8001e1c:	b580      	push	{r7, lr}
 8001e1e:	b086      	sub	sp, #24
 8001e20:	af00      	add	r7, sp, #0
 8001e22:	6078      	str	r0, [r7, #4]
	uint8_t min;
	uint16_t rem;
	i15765_mfr_t *mfrb;

	/* find the matching index */	//qiaoxu
	if(i15765_mfrb_seek(msg, &mfrb))
 8001e24:	f107 030c 	add.w	r3, r7, #12
 8001e28:	4619      	mov	r1, r3
 8001e2a:	6878      	ldr	r0, [r7, #4]
 8001e2c:	f7ff fd04 	bl	8001838 <i15765_mfrb_seek>
 8001e30:	4603      	mov	r3, r0
 8001e32:	2b00      	cmp	r3, #0
 8001e34:	d168      	bne.n	8001f08 <i15765_rx_cf+0xec>
		return;

	/* if the CF frame is not expected, ignore it */
	if(mfrb->state != STATE_WT_CF)
 8001e36:	68fb      	ldr	r3, [r7, #12]
 8001e38:	7d1b      	ldrb	r3, [r3, #20]
 8001e3a:	2b05      	cmp	r3, #5
 8001e3c:	d166      	bne.n	8001f0c <i15765_rx_cf+0xf0>
		return;

	/* increment the sequence number and compare */
	if((++mfrb->sn & 0xf) == (msg->buf[0] & 0xf))
 8001e3e:	68fb      	ldr	r3, [r7, #12]
 8001e40:	781a      	ldrb	r2, [r3, #0]
 8001e42:	3201      	adds	r2, #1
 8001e44:	b2d2      	uxtb	r2, r2
 8001e46:	701a      	strb	r2, [r3, #0]
 8001e48:	781a      	ldrb	r2, [r3, #0]
 8001e4a:	687b      	ldr	r3, [r7, #4]
 8001e4c:	685b      	ldr	r3, [r3, #4]
 8001e4e:	781b      	ldrb	r3, [r3, #0]
 8001e50:	4053      	eors	r3, r2
 8001e52:	b2db      	uxtb	r3, r3
 8001e54:	f003 030f 	and.w	r3, r3, #15
 8001e58:	2b00      	cmp	r3, #0
 8001e5a:	d151      	bne.n	8001f00 <i15765_rx_cf+0xe4>
	{
		/* skip PCI field */
		msg->buf++;
 8001e5c:	687b      	ldr	r3, [r7, #4]
 8001e5e:	685b      	ldr	r3, [r3, #4]
 8001e60:	1c5a      	adds	r2, r3, #1
 8001e62:	687b      	ldr	r3, [r7, #4]
 8001e64:	605a      	str	r2, [r3, #4]
		msg->buf_len--;
 8001e66:	687b      	ldr	r3, [r7, #4]
 8001e68:	891b      	ldrh	r3, [r3, #8]
 8001e6a:	3b01      	subs	r3, #1
 8001e6c:	b29a      	uxth	r2, r3
 8001e6e:	687b      	ldr	r3, [r7, #4]
 8001e70:	811a      	strh	r2, [r3, #8]

		/* if we are at the end of the message, stop early */
		rem = (mfrb->buf + mfrb->msg.buf_len) - mfrb->msg.buf;
 8001e72:	68fb      	ldr	r3, [r7, #12]
 8001e74:	3318      	adds	r3, #24
 8001e76:	68fa      	ldr	r2, [r7, #12]
 8001e78:	8992      	ldrh	r2, [r2, #12]
 8001e7a:	441a      	add	r2, r3
 8001e7c:	68fb      	ldr	r3, [r7, #12]
 8001e7e:	689b      	ldr	r3, [r3, #8]
 8001e80:	1ad3      	subs	r3, r2, r3
 8001e82:	82bb      	strh	r3, [r7, #20]

		min = (uint8_t) MIN(msg->buf_len, rem);
 8001e84:	687b      	ldr	r3, [r7, #4]
 8001e86:	891b      	ldrh	r3, [r3, #8]
 8001e88:	8aba      	ldrh	r2, [r7, #20]
 8001e8a:	429a      	cmp	r2, r3
 8001e8c:	d903      	bls.n	8001e96 <i15765_rx_cf+0x7a>
 8001e8e:	687b      	ldr	r3, [r7, #4]
 8001e90:	891b      	ldrh	r3, [r3, #8]
 8001e92:	b2db      	uxtb	r3, r3
 8001e94:	e001      	b.n	8001e9a <i15765_rx_cf+0x7e>
 8001e96:	8abb      	ldrh	r3, [r7, #20]
 8001e98:	b2db      	uxtb	r3, r3
 8001e9a:	74fb      	strb	r3, [r7, #19]

		/* add the data to the buffer */
		for(i = 0; i < min; i++)
 8001e9c:	2300      	movs	r3, #0
 8001e9e:	75fb      	strb	r3, [r7, #23]
 8001ea0:	e00c      	b.n	8001ebc <i15765_rx_cf+0xa0>
			*mfrb->msg.buf++ = msg->buf[i];
 8001ea2:	687b      	ldr	r3, [r7, #4]
 8001ea4:	685a      	ldr	r2, [r3, #4]
 8001ea6:	7dfb      	ldrb	r3, [r7, #23]
 8001ea8:	18d1      	adds	r1, r2, r3
 8001eaa:	68fa      	ldr	r2, [r7, #12]
 8001eac:	6893      	ldr	r3, [r2, #8]
 8001eae:	1c58      	adds	r0, r3, #1
 8001eb0:	6090      	str	r0, [r2, #8]
 8001eb2:	780a      	ldrb	r2, [r1, #0]
 8001eb4:	701a      	strb	r2, [r3, #0]
		for(i = 0; i < min; i++)
 8001eb6:	7dfb      	ldrb	r3, [r7, #23]
 8001eb8:	3301      	adds	r3, #1
 8001eba:	75fb      	strb	r3, [r7, #23]
 8001ebc:	7dfa      	ldrb	r2, [r7, #23]
 8001ebe:	7cfb      	ldrb	r3, [r7, #19]
 8001ec0:	429a      	cmp	r2, r3
 8001ec2:	d3ee      	bcc.n	8001ea2 <i15765_rx_cf+0x86>

		rem = (mfrb->buf + mfrb->msg.buf_len) - mfrb->msg.buf;
 8001ec4:	68fb      	ldr	r3, [r7, #12]
 8001ec6:	3318      	adds	r3, #24
 8001ec8:	68fa      	ldr	r2, [r7, #12]
 8001eca:	8992      	ldrh	r2, [r2, #12]
 8001ecc:	441a      	add	r2, r3
 8001ece:	68fb      	ldr	r3, [r7, #12]
 8001ed0:	689b      	ldr	r3, [r3, #8]
 8001ed2:	1ad3      	subs	r3, r2, r3
 8001ed4:	82bb      	strh	r3, [r7, #20]

		/* if we stopped early, the reception is complete */
		if(rem == 0)
 8001ed6:	8abb      	ldrh	r3, [r7, #20]
 8001ed8:	2b00      	cmp	r3, #0
 8001eda:	d10c      	bne.n	8001ef6 <i15765_rx_cf+0xda>
		{

			mfrb->msg.buf = mfrb->buf;
 8001edc:	68fa      	ldr	r2, [r7, #12]
 8001ede:	68fb      	ldr	r3, [r7, #12]
 8001ee0:	3218      	adds	r2, #24
 8001ee2:	609a      	str	r2, [r3, #8]
			i15765app_process(&mfrb->msg);
 8001ee4:	68fb      	ldr	r3, [r7, #12]
 8001ee6:	3304      	adds	r3, #4
 8001ee8:	4618      	mov	r0, r3
 8001eea:	f000 fa3b 	bl	8002364 <i15765app_process>
			mfrb->state = STATE_IDLE;
 8001eee:	68fb      	ldr	r3, [r7, #12]
 8001ef0:	2200      	movs	r2, #0
 8001ef2:	751a      	strb	r2, [r3, #20]
 8001ef4:	e00b      	b.n	8001f0e <i15765_rx_cf+0xf2>

		}
		else
		{
			mfrb->timeout = TIMEOUT_CF_R;
 8001ef6:	68fb      	ldr	r3, [r7, #12]
 8001ef8:	4a06      	ldr	r2, [pc, #24]	@ (8001f14 <i15765_rx_cf+0xf8>)
 8001efa:	8812      	ldrh	r2, [r2, #0]
 8001efc:	82da      	strh	r2, [r3, #22]
 8001efe:	e006      	b.n	8001f0e <i15765_rx_cf+0xf2>
		}
	}
	else
	{
		/* abort the reception */
		mfrb->state = STATE_IDLE;
 8001f00:	68fb      	ldr	r3, [r7, #12]
 8001f02:	2200      	movs	r2, #0
 8001f04:	751a      	strb	r2, [r3, #20]
 8001f06:	e002      	b.n	8001f0e <i15765_rx_cf+0xf2>
		return;
 8001f08:	bf00      	nop
 8001f0a:	e000      	b.n	8001f0e <i15765_rx_cf+0xf2>
		return;
 8001f0c:	bf00      	nop

	}
}
 8001f0e:	3718      	adds	r7, #24
 8001f10:	46bd      	mov	sp, r7
 8001f12:	bd80      	pop	{r7, pc}
 8001f14:	08005dd8 	.word	0x08005dd8

08001f18 <i15765_rx_fc>:
/*
** Handle a recieved flow control frame
** INPUT: msg - pointer to the received message
*/
void i15765_rx_fc(i15765_t *msg)
{
 8001f18:	b580      	push	{r7, lr}
 8001f1a:	b084      	sub	sp, #16
 8001f1c:	af00      	add	r7, sp, #0
 8001f1e:	6078      	str	r0, [r7, #4]

	i15765_mft_t *mftb;

	/* find matching multiframe transmit buffer */
	if(i15765_mftb_seek(msg, &mftb))//qiaoxu
 8001f20:	f107 030c 	add.w	r3, r7, #12
 8001f24:	4619      	mov	r1, r3
 8001f26:	6878      	ldr	r0, [r7, #4]
 8001f28:	f7ff fc58 	bl	80017dc <i15765_mftb_seek>
 8001f2c:	4603      	mov	r3, r0
 8001f2e:	2b00      	cmp	r3, #0
 8001f30:	d173      	bne.n	800201a <i15765_rx_fc+0x102>
		return;

	/* if the FC frame is not expected, ignore it */
	if(mftb->state != STATE_WT_FC)
 8001f32:	68fb      	ldr	r3, [r7, #12]
 8001f34:	7e1b      	ldrb	r3, [r3, #24]
 8001f36:	2b04      	cmp	r3, #4
 8001f38:	d171      	bne.n	800201e <i15765_rx_fc+0x106>
		return;

	//qiaoxu add
	if(msg->buf_len<3)
 8001f3a:	687b      	ldr	r3, [r7, #4]
 8001f3c:	891b      	ldrh	r3, [r3, #8]
 8001f3e:	2b02      	cmp	r3, #2
 8001f40:	d96f      	bls.n	8002022 <i15765_rx_fc+0x10a>
		return;
	}
	//////////////////////////////////////////////////////////////

	/* determine what type of FC this is and act appropriately */
	switch(msg->buf[0] & 0xf)
 8001f42:	687b      	ldr	r3, [r7, #4]
 8001f44:	685b      	ldr	r3, [r3, #4]
 8001f46:	781b      	ldrb	r3, [r3, #0]
 8001f48:	f003 030f 	and.w	r3, r3, #15
 8001f4c:	2b00      	cmp	r3, #0
 8001f4e:	d002      	beq.n	8001f56 <i15765_rx_fc+0x3e>
 8001f50:	2b01      	cmp	r3, #1
 8001f52:	d048      	beq.n	8001fe6 <i15765_rx_fc+0xce>
 8001f54:	e056      	b.n	8002004 <i15765_rx_fc+0xec>
	{

		/* continue to send */
	case 0:
		mftb->state = STATE_TX_CF;
 8001f56:	68fb      	ldr	r3, [r7, #12]
 8001f58:	2203      	movs	r2, #3
 8001f5a:	761a      	strb	r2, [r3, #24]
		mftb->bs = msg->buf[1];
 8001f5c:	687b      	ldr	r3, [r7, #4]
 8001f5e:	685a      	ldr	r2, [r3, #4]
 8001f60:	68fb      	ldr	r3, [r7, #12]
 8001f62:	7852      	ldrb	r2, [r2, #1]
 8001f64:	701a      	strb	r2, [r3, #0]
		mftb->bs_cnt = mftb->bs;
 8001f66:	68fa      	ldr	r2, [r7, #12]
 8001f68:	68fb      	ldr	r3, [r7, #12]
 8001f6a:	7812      	ldrb	r2, [r2, #0]
 8001f6c:	705a      	strb	r2, [r3, #1]

		if(msg->buf[2] <= 0x7f)
 8001f6e:	687b      	ldr	r3, [r7, #4]
 8001f70:	685b      	ldr	r3, [r3, #4]
 8001f72:	3302      	adds	r3, #2
 8001f74:	781b      	ldrb	r3, [r3, #0]
 8001f76:	b25b      	sxtb	r3, r3
 8001f78:	2b00      	cmp	r3, #0
 8001f7a:	db06      	blt.n	8001f8a <i15765_rx_fc+0x72>
			mftb->st = msg->buf[2];
 8001f7c:	687b      	ldr	r3, [r7, #4]
 8001f7e:	685b      	ldr	r3, [r3, #4]
 8001f80:	3302      	adds	r3, #2
 8001f82:	781a      	ldrb	r2, [r3, #0]
 8001f84:	68fb      	ldr	r3, [r7, #12]
 8001f86:	805a      	strh	r2, [r3, #2]
 8001f88:	e012      	b.n	8001fb0 <i15765_rx_fc+0x98>
		else if((msg->buf[2] >= 0xf1) && (msg->buf[2] <= 0xf9))
 8001f8a:	687b      	ldr	r3, [r7, #4]
 8001f8c:	685b      	ldr	r3, [r3, #4]
 8001f8e:	3302      	adds	r3, #2
 8001f90:	781b      	ldrb	r3, [r3, #0]
 8001f92:	2bf0      	cmp	r3, #240	@ 0xf0
 8001f94:	d909      	bls.n	8001faa <i15765_rx_fc+0x92>
 8001f96:	687b      	ldr	r3, [r7, #4]
 8001f98:	685b      	ldr	r3, [r3, #4]
 8001f9a:	3302      	adds	r3, #2
 8001f9c:	781b      	ldrb	r3, [r3, #0]
 8001f9e:	2bf9      	cmp	r3, #249	@ 0xf9
 8001fa0:	d803      	bhi.n	8001faa <i15765_rx_fc+0x92>
			mftb->st = 0x01;
 8001fa2:	68fb      	ldr	r3, [r7, #12]
 8001fa4:	2201      	movs	r2, #1
 8001fa6:	805a      	strh	r2, [r3, #2]
 8001fa8:	e002      	b.n	8001fb0 <i15765_rx_fc+0x98>
		else
			mftb->st = 0x7f;
 8001faa:	68fb      	ldr	r3, [r7, #12]
 8001fac:	227f      	movs	r2, #127	@ 0x7f
 8001fae:	805a      	strh	r2, [r3, #2]

		/* convert to units of 100 microseconds (1ms) */
		mftb->st *= ((uint16_t)1);
 8001fb0:	68fa      	ldr	r2, [r7, #12]
 8001fb2:	68fb      	ldr	r3, [r7, #12]
 8001fb4:	8852      	ldrh	r2, [r2, #2]
 8001fb6:	805a      	strh	r2, [r3, #2]

		/* convert to ticks */
		mftb->st /= ((uint8_t)I15765CFG_TICK_PERIOD);
 8001fb8:	68fb      	ldr	r3, [r7, #12]
 8001fba:	885b      	ldrh	r3, [r3, #2]
 8001fbc:	461a      	mov	r2, r3
 8001fbe:	4b1c      	ldr	r3, [pc, #112]	@ (8002030 <i15765_rx_fc+0x118>)
 8001fc0:	881b      	ldrh	r3, [r3, #0]
 8001fc2:	b2db      	uxtb	r3, r3
 8001fc4:	fb92 f2f3 	sdiv	r2, r2, r3
 8001fc8:	68fb      	ldr	r3, [r7, #12]
 8001fca:	b292      	uxth	r2, r2
 8001fcc:	805a      	strh	r2, [r3, #2]

		mftb->st_cnt = mftb->st;
 8001fce:	68fa      	ldr	r2, [r7, #12]
 8001fd0:	68fb      	ldr	r3, [r7, #12]
 8001fd2:	8852      	ldrh	r2, [r2, #2]
 8001fd4:	809a      	strh	r2, [r3, #4]
		mftb->timeout = TIMEOUT_CF_S;
 8001fd6:	68fb      	ldr	r3, [r7, #12]
 8001fd8:	4a16      	ldr	r2, [pc, #88]	@ (8002034 <i15765_rx_fc+0x11c>)
 8001fda:	8812      	ldrh	r2, [r2, #0]
 8001fdc:	841a      	strh	r2, [r3, #32]
		mftb->wt_cnt = 0;
 8001fde:	68fb      	ldr	r3, [r7, #12]
 8001fe0:	2200      	movs	r2, #0
 8001fe2:	71da      	strb	r2, [r3, #7]
		break;
 8001fe4:	e020      	b.n	8002028 <i15765_rx_fc+0x110>

		/* wait (NOTE - must be above "default" case) */
	case 1:
		mftb->state = STATE_WT_FC;
 8001fe6:	68fb      	ldr	r3, [r7, #12]
 8001fe8:	2204      	movs	r2, #4
 8001fea:	761a      	strb	r2, [r3, #24]
		mftb->timeout = TIMEOUT_FC_S;
 8001fec:	68fb      	ldr	r3, [r7, #12]
 8001fee:	4a12      	ldr	r2, [pc, #72]	@ (8002038 <i15765_rx_fc+0x120>)
 8001ff0:	8812      	ldrh	r2, [r2, #0]
 8001ff2:	841a      	strh	r2, [r3, #32]

		/* if too many waits, bail */
		if(++mftb->wt_cnt < 5)
 8001ff4:	68fb      	ldr	r3, [r7, #12]
 8001ff6:	79da      	ldrb	r2, [r3, #7]
 8001ff8:	3201      	adds	r2, #1
 8001ffa:	b2d2      	uxtb	r2, r2
 8001ffc:	71da      	strb	r2, [r3, #7]
 8001ffe:	79db      	ldrb	r3, [r3, #7]
 8002000:	2b04      	cmp	r3, #4
 8002002:	d910      	bls.n	8002026 <i15765_rx_fc+0x10e>
			break;

		/* all others */
	default:
		mftb->state = STATE_IDLE;
 8002004:	68fb      	ldr	r3, [r7, #12]
 8002006:	2200      	movs	r2, #0
 8002008:	761a      	strb	r2, [r3, #24]
		*mftb->status = I15765_FAILED;
 800200a:	68fb      	ldr	r3, [r7, #12]
 800200c:	69db      	ldr	r3, [r3, #28]
 800200e:	2202      	movs	r2, #2
 8002010:	701a      	strb	r2, [r3, #0]
		mftb->status = &i15765_tmp;
 8002012:	68fb      	ldr	r3, [r7, #12]
 8002014:	4a09      	ldr	r2, [pc, #36]	@ (800203c <i15765_rx_fc+0x124>)
 8002016:	61da      	str	r2, [r3, #28]
		break;
 8002018:	e006      	b.n	8002028 <i15765_rx_fc+0x110>
		return;
 800201a:	bf00      	nop
 800201c:	e004      	b.n	8002028 <i15765_rx_fc+0x110>
		return;
 800201e:	bf00      	nop
 8002020:	e002      	b.n	8002028 <i15765_rx_fc+0x110>
		return;
 8002022:	bf00      	nop
 8002024:	e000      	b.n	8002028 <i15765_rx_fc+0x110>
			break;
 8002026:	bf00      	nop
	}
}
 8002028:	3710      	adds	r7, #16
 800202a:	46bd      	mov	sp, r7
 800202c:	bd80      	pop	{r7, pc}
 800202e:	bf00      	nop
 8002030:	08005dda 	.word	0x08005dda
 8002034:	08005dd6 	.word	0x08005dd6
 8002038:	08005dd4 	.word	0x08005dd4
 800203c:	20000e74 	.word	0x20000e74

08002040 <i15765_rx_post>:
/*
** Translates the CAN frame into an i15765 message
** INPUT: can - pointer to the received CAN frame
*/
void i15765_rx_post(can_t *can)
{
 8002040:	b580      	push	{r7, lr}
 8002042:	b088      	sub	sp, #32
 8002044:	af00      	add	r7, sp, #0
 8002046:	6078      	str	r0, [r7, #4]
	i15765_t msg;
	uint8_t pdu_type;

	if(!(can->id & B31))
 8002048:	687b      	ldr	r3, [r7, #4]
 800204a:	681b      	ldr	r3, [r3, #0]
 800204c:	2b00      	cmp	r3, #0
 800204e:	db22      	blt.n	8002096 <i15765_rx_post+0x56>
	{
		msg.buf = &can->buf[0];
 8002050:	687b      	ldr	r3, [r7, #4]
 8002052:	3304      	adds	r3, #4
 8002054:	613b      	str	r3, [r7, #16]
		msg.buf_len = can->buf_len;
 8002056:	687b      	ldr	r3, [r7, #4]
 8002058:	7b1b      	ldrb	r3, [r3, #12]
 800205a:	82bb      	strh	r3, [r7, #20]
		msg.pri = 0;
 800205c:	2300      	movs	r3, #0
 800205e:	73bb      	strb	r3, [r7, #14]

		if(can->id == 0x7DF)
 8002060:	687b      	ldr	r3, [r7, #4]
 8002062:	681b      	ldr	r3, [r3, #0]
 8002064:	f240 72df 	movw	r2, #2015	@ 0x7df
 8002068:	4293      	cmp	r3, r2
 800206a:	d104      	bne.n	8002076 <i15765_rx_post+0x36>
		{

			/* support incoming functional requests */
			msg.tat = I15765_TAT_NF11;
 800206c:	2377      	movs	r3, #119	@ 0x77
 800206e:	73fb      	strb	r3, [r7, #15]
			//msg.sa = 0xf1;
			msg.sa = I15765CFG_SA;
 8002070:	23f1      	movs	r3, #241	@ 0xf1
 8002072:	733b      	strb	r3, [r7, #12]
 8002074:	e00f      	b.n	8002096 <i15765_rx_post+0x56>

		}
		else if(can->id == UDS_RX_ID)//
 8002076:	687b      	ldr	r3, [r7, #4]
 8002078:	681a      	ldr	r2, [r3, #0]
 800207a:	4b24      	ldr	r3, [pc, #144]	@ (800210c <i15765_rx_post+0xcc>)
 800207c:	681b      	ldr	r3, [r3, #0]
 800207e:	429a      	cmp	r2, r3
 8002080:	d109      	bne.n	8002096 <i15765_rx_post+0x56>
		{
			/* support incoming requests (0xf1 is external test equipment) */
			msg.tat = I15765_TAT_NP11;
 8002082:	2376      	movs	r3, #118	@ 0x76
 8002084:	73fb      	strb	r3, [r7, #15]
			//msg.sa = 0xf1;
			msg.sa = I15765CFG_SA;	//
 8002086:	23f1      	movs	r3, #241	@ 0xf1
 8002088:	733b      	strb	r3, [r7, #12]
			msg.ta = (can->id - 0x7e0) + 1;
 800208a:	687b      	ldr	r3, [r7, #4]
 800208c:	681b      	ldr	r3, [r3, #0]
 800208e:	b2db      	uxtb	r3, r3
 8002090:	3321      	adds	r3, #33	@ 0x21
 8002092:	b2db      	uxtb	r3, r3
 8002094:	737b      	strb	r3, [r7, #13]
		}

	}

	/* SF, FF, CF, or FC? */
	pdu_type = msg.buf[0] >> 4;
 8002096:	693b      	ldr	r3, [r7, #16]
 8002098:	781b      	ldrb	r3, [r3, #0]
 800209a:	091b      	lsrs	r3, r3, #4
 800209c:	77fb      	strb	r3, [r7, #31]

	/* if this message is not for us or not functional, discard it */
	if((ADDR_FUNC(msg.tat) && pdu_type != I15765_PDU_SF))
 800209e:	7bfb      	ldrb	r3, [r7, #15]
 80020a0:	2b77      	cmp	r3, #119	@ 0x77
 80020a2:	d002      	beq.n	80020aa <i15765_rx_post+0x6a>
 80020a4:	7bfb      	ldrb	r3, [r7, #15]
 80020a6:	2bdb      	cmp	r3, #219	@ 0xdb
 80020a8:	d102      	bne.n	80020b0 <i15765_rx_post+0x70>
 80020aa:	7ffb      	ldrb	r3, [r7, #31]
 80020ac:	2b00      	cmp	r3, #0
 80020ae:	d129      	bne.n	8002104 <i15765_rx_post+0xc4>
	{
		return;
	}

	if(pdu_type <= 3)
 80020b0:	7ffb      	ldrb	r3, [r7, #31]
 80020b2:	2b03      	cmp	r3, #3
 80020b4:	d827      	bhi.n	8002106 <i15765_rx_post+0xc6>
	{
		switch(pdu_type)
 80020b6:	7ffb      	ldrb	r3, [r7, #31]
 80020b8:	2b03      	cmp	r3, #3
 80020ba:	d824      	bhi.n	8002106 <i15765_rx_post+0xc6>
 80020bc:	a201      	add	r2, pc, #4	@ (adr r2, 80020c4 <i15765_rx_post+0x84>)
 80020be:	f852 f023 	ldr.w	pc, [r2, r3, lsl #2]
 80020c2:	bf00      	nop
 80020c4:	080020d5 	.word	0x080020d5
 80020c8:	080020e1 	.word	0x080020e1
 80020cc:	080020ed 	.word	0x080020ed
 80020d0:	080020f9 	.word	0x080020f9
		{
		case I15765_PDU_SF:
			i15765_rx_sf(&msg);
 80020d4:	f107 030c 	add.w	r3, r7, #12
 80020d8:	4618      	mov	r0, r3
 80020da:	f7ff fe15 	bl	8001d08 <i15765_rx_sf>
			break;
 80020de:	e012      	b.n	8002106 <i15765_rx_post+0xc6>
		case I15765_PDU_FF:
			i15765_rx_ff(&msg);
 80020e0:	f107 030c 	add.w	r3, r7, #12
 80020e4:	4618      	mov	r0, r3
 80020e6:	f7ff fe33 	bl	8001d50 <i15765_rx_ff>
			break;
 80020ea:	e00c      	b.n	8002106 <i15765_rx_post+0xc6>
		case I15765_PDU_CF:
			i15765_rx_cf(&msg);
 80020ec:	f107 030c 	add.w	r3, r7, #12
 80020f0:	4618      	mov	r0, r3
 80020f2:	f7ff fe93 	bl	8001e1c <i15765_rx_cf>
			break;
 80020f6:	e006      	b.n	8002106 <i15765_rx_post+0xc6>
		case I15765_PDU_FC:
			i15765_rx_fc(&msg);
 80020f8:	f107 030c 	add.w	r3, r7, #12
 80020fc:	4618      	mov	r0, r3
 80020fe:	f7ff ff0b 	bl	8001f18 <i15765_rx_fc>
			break;
 8002102:	e000      	b.n	8002106 <i15765_rx_post+0xc6>
		return;
 8002104:	bf00      	nop
		}
	}
}
 8002106:	3720      	adds	r7, #32
 8002108:	46bd      	mov	sp, r7
 800210a:	bd80      	pop	{r7, pc}
 800210c:	08005de4 	.word	0x08005de4

08002110 <i15765_tx_app>:
** Requests a message to be transmitted, either single or multi-frame
** INPUT: msg - the message to transmit
**        status - pointer to user RAM location for status feedback
*/
void i15765_tx_app(i15765_t *msg, uint8_t *status)
{
 8002110:	b580      	push	{r7, lr}
 8002112:	b082      	sub	sp, #8
 8002114:	af00      	add	r7, sp, #0
 8002116:	6078      	str	r0, [r7, #4]
 8002118:	6039      	str	r1, [r7, #0]

	/* status always has to point somewhere */
	if(status == 0)
 800211a:	683b      	ldr	r3, [r7, #0]
 800211c:	2b00      	cmp	r3, #0
 800211e:	d101      	bne.n	8002124 <i15765_tx_app+0x14>
		status = &i15765_tmp;
 8002120:	4b13      	ldr	r3, [pc, #76]	@ (8002170 <i15765_tx_app+0x60>)
 8002122:	603b      	str	r3, [r7, #0]

	/* load in source address into out going message */
	msg->sa = i15765_sa;
 8002124:	4b13      	ldr	r3, [pc, #76]	@ (8002174 <i15765_tx_app+0x64>)
 8002126:	781a      	ldrb	r2, [r3, #0]
 8002128:	687b      	ldr	r3, [r7, #4]
 800212a:	701a      	strb	r2, [r3, #0]

	/* if its small enough to send in a SF, pack and transmit */
	if(msg->buf_len <= 7)
 800212c:	687b      	ldr	r3, [r7, #4]
 800212e:	891b      	ldrh	r3, [r3, #8]
 8002130:	2b07      	cmp	r3, #7
 8002132:	d80b      	bhi.n	800214c <i15765_tx_app+0x3c>
	{

		*status = (i15765_tx_sf(msg) == 0) ? I15765_SENT : I15765_FAILED;
 8002134:	6878      	ldr	r0, [r7, #4]
 8002136:	f7ff fbef 	bl	8001918 <i15765_tx_sf>
 800213a:	4603      	mov	r3, r0
 800213c:	2b00      	cmp	r3, #0
 800213e:	d101      	bne.n	8002144 <i15765_tx_app+0x34>
 8002140:	2200      	movs	r2, #0
 8002142:	e000      	b.n	8002146 <i15765_tx_app+0x36>
 8002144:	2202      	movs	r2, #2
 8002146:	683b      	ldr	r3, [r7, #0]
 8002148:	701a      	strb	r2, [r3, #0]
	{

		/* too big or no available buffers */
		*status = I15765_FAILED;
	}
}
 800214a:	e00c      	b.n	8002166 <i15765_tx_app+0x56>
	else if(msg->buf_len <= I15765CFG_MF_TX_BUF_SIZE)
 800214c:	687b      	ldr	r3, [r7, #4]
 800214e:	891b      	ldrh	r3, [r3, #8]
 8002150:	f5b3 6f80 	cmp.w	r3, #1024	@ 0x400
 8002154:	d804      	bhi.n	8002160 <i15765_tx_app+0x50>
		i15765_tx_mf(msg, status);
 8002156:	6839      	ldr	r1, [r7, #0]
 8002158:	6878      	ldr	r0, [r7, #4]
 800215a:	f7ff fd2d 	bl	8001bb8 <i15765_tx_mf>
}
 800215e:	e002      	b.n	8002166 <i15765_tx_app+0x56>
		*status = I15765_FAILED;
 8002160:	683b      	ldr	r3, [r7, #0]
 8002162:	2202      	movs	r2, #2
 8002164:	701a      	strb	r2, [r3, #0]
}
 8002166:	bf00      	nop
 8002168:	3708      	adds	r7, #8
 800216a:	46bd      	mov	sp, r7
 800216c:	bd80      	pop	{r7, pc}
 800216e:	bf00      	nop
 8002170:	20000e74 	.word	0x20000e74
 8002174:	20000008 	.word	0x20000008

08002178 <i15765_tx_update>:
/*
** Cycle through our active messages and attempt to continue
** transmitting.  Also, check for timeouts as we go.
*/
void i15765_tx_update(void)
{
 8002178:	b580      	push	{r7, lr}
 800217a:	b082      	sub	sp, #8
 800217c:	af00      	add	r7, sp, #0

	uint8_t i;

	/* for each currently transmitting message, continue */
	for(i = 0; i < I15765CFG_MF_TX_BUF_NUM; i++)
 800217e:	2300      	movs	r3, #0
 8002180:	71fb      	strb	r3, [r7, #7]
 8002182:	e065      	b.n	8002250 <i15765_tx_update+0xd8>
	{

		/* if we are waiting on a transmission to complete, try it again */
		switch(i15765_mftb[i].state)
 8002184:	79fb      	ldrb	r3, [r7, #7]
 8002186:	4a36      	ldr	r2, [pc, #216]	@ (8002260 <i15765_tx_update+0xe8>)
 8002188:	f240 4124 	movw	r1, #1060	@ 0x424
 800218c:	fb01 f303 	mul.w	r3, r1, r3
 8002190:	4413      	add	r3, r2
 8002192:	3318      	adds	r3, #24
 8002194:	781b      	ldrb	r3, [r3, #0]
 8002196:	2b01      	cmp	r3, #1
 8002198:	d002      	beq.n	80021a0 <i15765_tx_update+0x28>
 800219a:	2b03      	cmp	r3, #3
 800219c:	d00b      	beq.n	80021b6 <i15765_tx_update+0x3e>
 800219e:	e015      	b.n	80021cc <i15765_tx_update+0x54>
		{

		case STATE_TX_FF:
			i15765_tx_ff(&i15765_mftb[i]);
 80021a0:	79fb      	ldrb	r3, [r7, #7]
 80021a2:	f240 4224 	movw	r2, #1060	@ 0x424
 80021a6:	fb02 f303 	mul.w	r3, r2, r3
 80021aa:	4a2d      	ldr	r2, [pc, #180]	@ (8002260 <i15765_tx_update+0xe8>)
 80021ac:	4413      	add	r3, r2
 80021ae:	4618      	mov	r0, r3
 80021b0:	f7ff fbfc 	bl	80019ac <i15765_tx_ff>
			break;
 80021b4:	e00a      	b.n	80021cc <i15765_tx_update+0x54>
		case STATE_TX_CF:
			i15765_tx_cf(&i15765_mftb[i]);
 80021b6:	79fb      	ldrb	r3, [r7, #7]
 80021b8:	f240 4224 	movw	r2, #1060	@ 0x424
 80021bc:	fb02 f303 	mul.w	r3, r2, r3
 80021c0:	4a27      	ldr	r2, [pc, #156]	@ (8002260 <i15765_tx_update+0xe8>)
 80021c2:	4413      	add	r3, r2
 80021c4:	4618      	mov	r0, r3
 80021c6:	f7ff fc4d 	bl	8001a64 <i15765_tx_cf>
			break;
 80021ca:	bf00      	nop
		}

		/* update timeout */
		if(i15765_mftb[i].timeout)
 80021cc:	79fb      	ldrb	r3, [r7, #7]
 80021ce:	4a24      	ldr	r2, [pc, #144]	@ (8002260 <i15765_tx_update+0xe8>)
 80021d0:	f240 4124 	movw	r1, #1060	@ 0x424
 80021d4:	fb01 f303 	mul.w	r3, r1, r3
 80021d8:	4413      	add	r3, r2
 80021da:	3320      	adds	r3, #32
 80021dc:	881b      	ldrh	r3, [r3, #0]
 80021de:	2b00      	cmp	r3, #0
 80021e0:	d014      	beq.n	800220c <i15765_tx_update+0x94>
		{

			i15765_mftb[i].timeout--;
 80021e2:	79fb      	ldrb	r3, [r7, #7]
 80021e4:	491e      	ldr	r1, [pc, #120]	@ (8002260 <i15765_tx_update+0xe8>)
 80021e6:	f240 4224 	movw	r2, #1060	@ 0x424
 80021ea:	fb03 f202 	mul.w	r2, r3, r2
 80021ee:	440a      	add	r2, r1
 80021f0:	3220      	adds	r2, #32
 80021f2:	8812      	ldrh	r2, [r2, #0]
 80021f4:	3a01      	subs	r2, #1
 80021f6:	b290      	uxth	r0, r2
 80021f8:	4a19      	ldr	r2, [pc, #100]	@ (8002260 <i15765_tx_update+0xe8>)
 80021fa:	f240 4124 	movw	r1, #1060	@ 0x424
 80021fe:	fb01 f303 	mul.w	r3, r1, r3
 8002202:	4413      	add	r3, r2
 8002204:	3320      	adds	r3, #32
 8002206:	4602      	mov	r2, r0
 8002208:	801a      	strh	r2, [r3, #0]
 800220a:	e01e      	b.n	800224a <i15765_tx_update+0xd2>

		}
		else
		{

			i15765_mftb[i].state = STATE_IDLE;
 800220c:	79fb      	ldrb	r3, [r7, #7]
 800220e:	4a14      	ldr	r2, [pc, #80]	@ (8002260 <i15765_tx_update+0xe8>)
 8002210:	f240 4124 	movw	r1, #1060	@ 0x424
 8002214:	fb01 f303 	mul.w	r3, r1, r3
 8002218:	4413      	add	r3, r2
 800221a:	3318      	adds	r3, #24
 800221c:	2200      	movs	r2, #0
 800221e:	701a      	strb	r2, [r3, #0]
			*i15765_mftb[i].status = I15765_FAILED;
 8002220:	79fb      	ldrb	r3, [r7, #7]
 8002222:	4a0f      	ldr	r2, [pc, #60]	@ (8002260 <i15765_tx_update+0xe8>)
 8002224:	f240 4124 	movw	r1, #1060	@ 0x424
 8002228:	fb01 f303 	mul.w	r3, r1, r3
 800222c:	4413      	add	r3, r2
 800222e:	331c      	adds	r3, #28
 8002230:	681b      	ldr	r3, [r3, #0]
 8002232:	2202      	movs	r2, #2
 8002234:	701a      	strb	r2, [r3, #0]
			i15765_mftb[i].status = &i15765_tmp;
 8002236:	79fb      	ldrb	r3, [r7, #7]
 8002238:	4a09      	ldr	r2, [pc, #36]	@ (8002260 <i15765_tx_update+0xe8>)
 800223a:	f240 4124 	movw	r1, #1060	@ 0x424
 800223e:	fb01 f303 	mul.w	r3, r1, r3
 8002242:	4413      	add	r3, r2
 8002244:	331c      	adds	r3, #28
 8002246:	4a07      	ldr	r2, [pc, #28]	@ (8002264 <i15765_tx_update+0xec>)
 8002248:	601a      	str	r2, [r3, #0]
	for(i = 0; i < I15765CFG_MF_TX_BUF_NUM; i++)
 800224a:	79fb      	ldrb	r3, [r7, #7]
 800224c:	3301      	adds	r3, #1
 800224e:	71fb      	strb	r3, [r7, #7]
 8002250:	79fb      	ldrb	r3, [r7, #7]
 8002252:	2b00      	cmp	r3, #0
 8002254:	d096      	beq.n	8002184 <i15765_tx_update+0xc>
//			i15765_mftb[i].status = 0;

		}
	}
}
 8002256:	bf00      	nop
 8002258:	bf00      	nop
 800225a:	3708      	adds	r7, #8
 800225c:	46bd      	mov	sp, r7
 800225e:	bd80      	pop	{r7, pc}
 8002260:	20000a50 	.word	0x20000a50
 8002264:	20000e74 	.word	0x20000e74

08002268 <i15765_rx_update>:
/*
** Cycle through our active messages and attempt to continue
** reception checking for timeouts as we go.
*/
void i15765_rx_update(void)
{
 8002268:	b580      	push	{r7, lr}
 800226a:	b086      	sub	sp, #24
 800226c:	af00      	add	r7, sp, #0

	can_t can;
	uint8_t i;

	/* read all the CAN frames and pass them up */
	while(can_rx(0, &can) == 0)
 800226e:	e003      	b.n	8002278 <i15765_rx_update+0x10>
		i15765_rx_post(&can);
 8002270:	1d3b      	adds	r3, r7, #4
 8002272:	4618      	mov	r0, r3
 8002274:	f7ff fee4 	bl	8002040 <i15765_rx_post>
	while(can_rx(0, &can) == 0)
 8002278:	1d3b      	adds	r3, r7, #4
 800227a:	4619      	mov	r1, r3
 800227c:	2000      	movs	r0, #0
 800227e:	f7ff f915 	bl	80014ac <can_rx>
 8002282:	4603      	mov	r3, r0
 8002284:	2b00      	cmp	r3, #0
 8002286:	d0f3      	beq.n	8002270 <i15765_rx_update+0x8>

	/* for each active message, check for expiration and cancel if needed */
	for(i = 0; i < I15765CFG_MF_RX_BUF_NUM; i++)
 8002288:	2300      	movs	r3, #0
 800228a:	75fb      	strb	r3, [r7, #23]
 800228c:	e04c      	b.n	8002328 <i15765_rx_update+0xc0>
	{

		/* if we are waiting to send an FC frame, try it again */
		if((i15765_mfrb[i].state == STATE_TX_CTS)
 800228e:	7dfb      	ldrb	r3, [r7, #23]
 8002290:	4a29      	ldr	r2, [pc, #164]	@ (8002338 <i15765_rx_update+0xd0>)
 8002292:	f640 0118 	movw	r1, #2072	@ 0x818
 8002296:	fb01 f303 	mul.w	r3, r1, r3
 800229a:	4413      	add	r3, r2
 800229c:	3314      	adds	r3, #20
 800229e:	781b      	ldrb	r3, [r3, #0]
 80022a0:	2b06      	cmp	r3, #6
 80022a2:	d00a      	beq.n	80022ba <i15765_rx_update+0x52>
		        || (i15765_mfrb[i].state == STATE_TX_OVFLW))
 80022a4:	7dfb      	ldrb	r3, [r7, #23]
 80022a6:	4a24      	ldr	r2, [pc, #144]	@ (8002338 <i15765_rx_update+0xd0>)
 80022a8:	f640 0118 	movw	r1, #2072	@ 0x818
 80022ac:	fb01 f303 	mul.w	r3, r1, r3
 80022b0:	4413      	add	r3, r2
 80022b2:	3314      	adds	r3, #20
 80022b4:	781b      	ldrb	r3, [r3, #0]
 80022b6:	2b07      	cmp	r3, #7
 80022b8:	d109      	bne.n	80022ce <i15765_rx_update+0x66>
			i15765_tx_fc(&i15765_mfrb[i]);
 80022ba:	7dfb      	ldrb	r3, [r7, #23]
 80022bc:	f640 0218 	movw	r2, #2072	@ 0x818
 80022c0:	fb02 f303 	mul.w	r3, r2, r3
 80022c4:	4a1c      	ldr	r2, [pc, #112]	@ (8002338 <i15765_rx_update+0xd0>)
 80022c6:	4413      	add	r3, r2
 80022c8:	4618      	mov	r0, r3
 80022ca:	f7ff fcc3 	bl	8001c54 <i15765_tx_fc>

		/* update timeout */
		if(i15765_mfrb[i].timeout)
 80022ce:	7dfb      	ldrb	r3, [r7, #23]
 80022d0:	4a19      	ldr	r2, [pc, #100]	@ (8002338 <i15765_rx_update+0xd0>)
 80022d2:	f640 0118 	movw	r1, #2072	@ 0x818
 80022d6:	fb01 f303 	mul.w	r3, r1, r3
 80022da:	4413      	add	r3, r2
 80022dc:	3316      	adds	r3, #22
 80022de:	881b      	ldrh	r3, [r3, #0]
 80022e0:	2b00      	cmp	r3, #0
 80022e2:	d014      	beq.n	800230e <i15765_rx_update+0xa6>
			i15765_mfrb[i].timeout--;
 80022e4:	7dfb      	ldrb	r3, [r7, #23]
 80022e6:	4914      	ldr	r1, [pc, #80]	@ (8002338 <i15765_rx_update+0xd0>)
 80022e8:	f640 0218 	movw	r2, #2072	@ 0x818
 80022ec:	fb03 f202 	mul.w	r2, r3, r2
 80022f0:	440a      	add	r2, r1
 80022f2:	3216      	adds	r2, #22
 80022f4:	8812      	ldrh	r2, [r2, #0]
 80022f6:	3a01      	subs	r2, #1
 80022f8:	b290      	uxth	r0, r2
 80022fa:	4a0f      	ldr	r2, [pc, #60]	@ (8002338 <i15765_rx_update+0xd0>)
 80022fc:	f640 0118 	movw	r1, #2072	@ 0x818
 8002300:	fb01 f303 	mul.w	r3, r1, r3
 8002304:	4413      	add	r3, r2
 8002306:	3316      	adds	r3, #22
 8002308:	4602      	mov	r2, r0
 800230a:	801a      	strh	r2, [r3, #0]
 800230c:	e009      	b.n	8002322 <i15765_rx_update+0xba>
		else
			i15765_mfrb[i].state = STATE_IDLE;
 800230e:	7dfb      	ldrb	r3, [r7, #23]
 8002310:	4a09      	ldr	r2, [pc, #36]	@ (8002338 <i15765_rx_update+0xd0>)
 8002312:	f640 0118 	movw	r1, #2072	@ 0x818
 8002316:	fb01 f303 	mul.w	r3, r1, r3
 800231a:	4413      	add	r3, r2
 800231c:	3314      	adds	r3, #20
 800231e:	2200      	movs	r2, #0
 8002320:	701a      	strb	r2, [r3, #0]
	for(i = 0; i < I15765CFG_MF_RX_BUF_NUM; i++)
 8002322:	7dfb      	ldrb	r3, [r7, #23]
 8002324:	3301      	adds	r3, #1
 8002326:	75fb      	strb	r3, [r7, #23]
 8002328:	7dfb      	ldrb	r3, [r7, #23]
 800232a:	2b00      	cmp	r3, #0
 800232c:	d0af      	beq.n	800228e <i15765_rx_update+0x26>
	}
}
 800232e:	bf00      	nop
 8002330:	bf00      	nop
 8002332:	3718      	adds	r7, #24
 8002334:	46bd      	mov	sp, r7
 8002336:	bd80      	pop	{r7, pc}
 8002338:	20000238 	.word	0x20000238

0800233c <i15765_update>:

/*
** This function is the time base for the entire i15765 module.
*/
void i15765_update(void)
{
 800233c:	b580      	push	{r7, lr}
 800233e:	af00      	add	r7, sp, #0
	i15765_rx_update();
 8002340:	f7ff ff92 	bl	8002268 <i15765_rx_update>
	i15765_tx_update();
 8002344:	f7ff ff18 	bl	8002178 <i15765_tx_update>
}
 8002348:	bf00      	nop
 800234a:	bd80      	pop	{r7, pc}

0800234c <i15765app_init>:

/*
** Initialization routine.
*/
void i15765app_init(void)
{
 800234c:	b480      	push	{r7}
 800234e:	af00      	add	r7, sp, #0
    DiagnosticSessionType = 0x02;
 8002350:	4b03      	ldr	r3, [pc, #12]	@ (8002360 <i15765app_init+0x14>)
 8002352:	2202      	movs	r2, #2
 8002354:	701a      	strb	r2, [r3, #0]
}
 8002356:	bf00      	nop
 8002358:	46bd      	mov	sp, r7
 800235a:	f85d 7b04 	ldr.w	r7, [sp], #4
 800235e:	4770      	bx	lr
 8002360:	20000009 	.word	0x20000009

08002364 <i15765app_process>:
uint8_t SID_34_flag = 0;
uint8_t SID_36_flag = 0;
uint8_t SID_37_flag = 0;

void i15765app_process(i15765_t *msg)
{
 8002364:	b580      	push	{r7, lr}
 8002366:	b082      	sub	sp, #8
 8002368:	af00      	add	r7, sp, #0
 800236a:	6078      	str	r0, [r7, #4]
    msg_new.buf_len = msg->buf_len;
 800236c:	687b      	ldr	r3, [r7, #4]
 800236e:	891a      	ldrh	r2, [r3, #8]
 8002370:	4b47      	ldr	r3, [pc, #284]	@ (8002490 <i15765app_process+0x12c>)
 8002372:	811a      	strh	r2, [r3, #8]
    msg_new.ID = msg->ID;
 8002374:	687b      	ldr	r3, [r7, #4]
 8002376:	68db      	ldr	r3, [r3, #12]
 8002378:	4a45      	ldr	r2, [pc, #276]	@ (8002490 <i15765app_process+0x12c>)
 800237a:	60d3      	str	r3, [r2, #12]

    // 深拷贝缓冲区
    memcpy(msg_new_buf, msg->buf, msg->buf_len);
 800237c:	687b      	ldr	r3, [r7, #4]
 800237e:	6859      	ldr	r1, [r3, #4]
 8002380:	687b      	ldr	r3, [r7, #4]
 8002382:	891b      	ldrh	r3, [r3, #8]
 8002384:	461a      	mov	r2, r3
 8002386:	4843      	ldr	r0, [pc, #268]	@ (8002494 <i15765app_process+0x130>)
 8002388:	f003 fb00 	bl	800598c <memcpy>
    msg_new.buf = msg_new_buf;  // 指向我们的缓冲区
 800238c:	4b40      	ldr	r3, [pc, #256]	@ (8002490 <i15765app_process+0x12c>)
 800238e:	4a41      	ldr	r2, [pc, #260]	@ (8002494 <i15765app_process+0x130>)
 8002390:	605a      	str	r2, [r3, #4]

    switch (msg->buf[0])
 8002392:	687b      	ldr	r3, [r7, #4]
 8002394:	685b      	ldr	r3, [r3, #4]
 8002396:	781b      	ldrb	r3, [r3, #0]
 8002398:	3b11      	subs	r3, #17
 800239a:	2b26      	cmp	r3, #38	@ 0x26
 800239c:	d868      	bhi.n	8002470 <i15765app_process+0x10c>
 800239e:	a201      	add	r2, pc, #4	@ (adr r2, 80023a4 <i15765app_process+0x40>)
 80023a0:	f852 f023 	ldr.w	pc, [r2, r3, lsl #2]
 80023a4:	08002441 	.word	0x08002441
 80023a8:	08002471 	.word	0x08002471
 80023ac:	08002471 	.word	0x08002471
 80023b0:	08002471 	.word	0x08002471
 80023b4:	08002471 	.word	0x08002471
 80023b8:	08002471 	.word	0x08002471
 80023bc:	08002471 	.word	0x08002471
 80023c0:	08002471 	.word	0x08002471
 80023c4:	08002471 	.word	0x08002471
 80023c8:	08002471 	.word	0x08002471
 80023cc:	08002471 	.word	0x08002471
 80023d0:	08002471 	.word	0x08002471
 80023d4:	08002471 	.word	0x08002471
 80023d8:	08002471 	.word	0x08002471
 80023dc:	08002471 	.word	0x08002471
 80023e0:	08002471 	.word	0x08002471
 80023e4:	08002471 	.word	0x08002471
 80023e8:	08002471 	.word	0x08002471
 80023ec:	08002471 	.word	0x08002471
 80023f0:	08002471 	.word	0x08002471
 80023f4:	08002471 	.word	0x08002471
 80023f8:	08002471 	.word	0x08002471
 80023fc:	08002471 	.word	0x08002471
 8002400:	08002471 	.word	0x08002471
 8002404:	08002471 	.word	0x08002471
 8002408:	08002471 	.word	0x08002471
 800240c:	08002471 	.word	0x08002471
 8002410:	08002471 	.word	0x08002471
 8002414:	08002471 	.word	0x08002471
 8002418:	08002449 	.word	0x08002449
 800241c:	08002471 	.word	0x08002471
 8002420:	08002471 	.word	0x08002471
 8002424:	08002451 	.word	0x08002451
 8002428:	08002471 	.word	0x08002471
 800242c:	08002471 	.word	0x08002471
 8002430:	08002459 	.word	0x08002459
 8002434:	08002471 	.word	0x08002471
 8002438:	08002461 	.word	0x08002461
 800243c:	08002469 	.word	0x08002469
    {
        case 0x11:
        {
        	SID_11_flag = 1;
 8002440:	4b15      	ldr	r3, [pc, #84]	@ (8002498 <i15765app_process+0x134>)
 8002442:	2201      	movs	r2, #1
 8002444:	701a      	strb	r2, [r3, #0]
//            SID_11_function(msg);
            break;
 8002446:	e01f      	b.n	8002488 <i15765app_process+0x124>
        }
        case 0x2E:
        {
        	SID_2E_flag = 1;
 8002448:	4b14      	ldr	r3, [pc, #80]	@ (800249c <i15765app_process+0x138>)
 800244a:	2201      	movs	r2, #1
 800244c:	701a      	strb	r2, [r3, #0]
//            SID_2E_function(msg);
            break;
 800244e:	e01b      	b.n	8002488 <i15765app_process+0x124>
        }
        case 0x31:
        {
        	SID_31_flag = 1;
 8002450:	4b13      	ldr	r3, [pc, #76]	@ (80024a0 <i15765app_process+0x13c>)
 8002452:	2201      	movs	r2, #1
 8002454:	701a      	strb	r2, [r3, #0]
//            SID_31_function(msg);
            break;
 8002456:	e017      	b.n	8002488 <i15765app_process+0x124>
        }
        case 0x34:
        {
        	SID_34_flag = 1;
 8002458:	4b12      	ldr	r3, [pc, #72]	@ (80024a4 <i15765app_process+0x140>)
 800245a:	2201      	movs	r2, #1
 800245c:	701a      	strb	r2, [r3, #0]
//            SID_34_function(msg);
            break;
 800245e:	e013      	b.n	8002488 <i15765app_process+0x124>
        }
        case 0x36:
        {
        	SID_36_flag = 1;
 8002460:	4b11      	ldr	r3, [pc, #68]	@ (80024a8 <i15765app_process+0x144>)
 8002462:	2201      	movs	r2, #1
 8002464:	701a      	strb	r2, [r3, #0]
//            SID_36_function(msg);
            break;
 8002466:	e00f      	b.n	8002488 <i15765app_process+0x124>
        }
        case 0x37:
        {
        	SID_37_flag = 1;
 8002468:	4b10      	ldr	r3, [pc, #64]	@ (80024ac <i15765app_process+0x148>)
 800246a:	2201      	movs	r2, #1
 800246c:	701a      	strb	r2, [r3, #0]
//            SID_37_function(msg);
            break;
 800246e:	e00b      	b.n	8002488 <i15765app_process+0x124>
        }
        default:
        {
            if (msg->tat == I15765_TAT_NP11)
 8002470:	687b      	ldr	r3, [r7, #4]
 8002472:	78db      	ldrb	r3, [r3, #3]
 8002474:	2b76      	cmp	r3, #118	@ 0x76
 8002476:	d107      	bne.n	8002488 <i15765app_process+0x124>
            {
                NegativeResponse(msg->buf[0], 0x11);
 8002478:	687b      	ldr	r3, [r7, #4]
 800247a:	685b      	ldr	r3, [r3, #4]
 800247c:	781b      	ldrb	r3, [r3, #0]
 800247e:	2111      	movs	r1, #17
 8002480:	4618      	mov	r0, r3
 8002482:	f000 f857 	bl	8002534 <NegativeResponse>
                break;
 8002486:	bf00      	nop
            }
        }
    }
}
 8002488:	bf00      	nop
 800248a:	3708      	adds	r7, #8
 800248c:	46bd      	mov	sp, r7
 800248e:	bd80      	pop	{r7, pc}
 8002490:	20000e78 	.word	0x20000e78
 8002494:	20000e88 	.word	0x20000e88
 8002498:	20001e88 	.word	0x20001e88
 800249c:	20001e89 	.word	0x20001e89
 80024a0:	20001e8a 	.word	0x20001e8a
 80024a4:	20001e8b 	.word	0x20001e8b
 80024a8:	20001e8c 	.word	0x20001e8c
 80024ac:	20001e8d 	.word	0x20001e8d

080024b0 <check_SID_run>:

void check_SID_run(void)
{
 80024b0:	b580      	push	{r7, lr}
 80024b2:	af00      	add	r7, sp, #0
	if(SID_11_flag == 1)
 80024b4:	4b19      	ldr	r3, [pc, #100]	@ (800251c <check_SID_run+0x6c>)
 80024b6:	781b      	ldrb	r3, [r3, #0]
 80024b8:	2b01      	cmp	r3, #1
 80024ba:	d105      	bne.n	80024c8 <check_SID_run+0x18>
	{
		SID_11_flag = 0;
 80024bc:	4b17      	ldr	r3, [pc, #92]	@ (800251c <check_SID_run+0x6c>)
 80024be:	2200      	movs	r2, #0
 80024c0:	701a      	strb	r2, [r3, #0]
		SID_11_function(&msg_new);
 80024c2:	4817      	ldr	r0, [pc, #92]	@ (8002520 <check_SID_run+0x70>)
 80024c4:	f000 f85a 	bl	800257c <SID_11_function>
	}
	if(SID_31_flag == 1)
 80024c8:	4b16      	ldr	r3, [pc, #88]	@ (8002524 <check_SID_run+0x74>)
 80024ca:	781b      	ldrb	r3, [r3, #0]
 80024cc:	2b01      	cmp	r3, #1
 80024ce:	d105      	bne.n	80024dc <check_SID_run+0x2c>
	{
		SID_31_flag = 0;
 80024d0:	4b14      	ldr	r3, [pc, #80]	@ (8002524 <check_SID_run+0x74>)
 80024d2:	2200      	movs	r2, #0
 80024d4:	701a      	strb	r2, [r3, #0]
		SID_31_function(&msg_new);
 80024d6:	4812      	ldr	r0, [pc, #72]	@ (8002520 <check_SID_run+0x70>)
 80024d8:	f000 f8de 	bl	8002698 <SID_31_function>
	}
	if(SID_34_flag == 1)
 80024dc:	4b12      	ldr	r3, [pc, #72]	@ (8002528 <check_SID_run+0x78>)
 80024de:	781b      	ldrb	r3, [r3, #0]
 80024e0:	2b01      	cmp	r3, #1
 80024e2:	d105      	bne.n	80024f0 <check_SID_run+0x40>
	{
		SID_34_flag = 0;
 80024e4:	4b10      	ldr	r3, [pc, #64]	@ (8002528 <check_SID_run+0x78>)
 80024e6:	2200      	movs	r2, #0
 80024e8:	701a      	strb	r2, [r3, #0]
		SID_34_function(&msg_new);
 80024ea:	480d      	ldr	r0, [pc, #52]	@ (8002520 <check_SID_run+0x70>)
 80024ec:	f000 fb0a 	bl	8002b04 <SID_34_function>
	}
	if(SID_36_flag == 1)
 80024f0:	4b0e      	ldr	r3, [pc, #56]	@ (800252c <check_SID_run+0x7c>)
 80024f2:	781b      	ldrb	r3, [r3, #0]
 80024f4:	2b01      	cmp	r3, #1
 80024f6:	d105      	bne.n	8002504 <check_SID_run+0x54>
	{
		SID_36_flag = 0;
 80024f8:	4b0c      	ldr	r3, [pc, #48]	@ (800252c <check_SID_run+0x7c>)
 80024fa:	2200      	movs	r2, #0
 80024fc:	701a      	strb	r2, [r3, #0]
		SID_36_function(&msg_new);
 80024fe:	4808      	ldr	r0, [pc, #32]	@ (8002520 <check_SID_run+0x70>)
 8002500:	f000 fbde 	bl	8002cc0 <SID_36_function>
	}
	if(SID_37_flag == 1)
 8002504:	4b0a      	ldr	r3, [pc, #40]	@ (8002530 <check_SID_run+0x80>)
 8002506:	781b      	ldrb	r3, [r3, #0]
 8002508:	2b01      	cmp	r3, #1
 800250a:	d105      	bne.n	8002518 <check_SID_run+0x68>
	{
		SID_37_flag = 0;
 800250c:	4b08      	ldr	r3, [pc, #32]	@ (8002530 <check_SID_run+0x80>)
 800250e:	2200      	movs	r2, #0
 8002510:	701a      	strb	r2, [r3, #0]
		SID_37_function(&msg_new);
 8002512:	4803      	ldr	r0, [pc, #12]	@ (8002520 <check_SID_run+0x70>)
 8002514:	f000 fd36 	bl	8002f84 <SID_37_function>
	}
}
 8002518:	bf00      	nop
 800251a:	bd80      	pop	{r7, pc}
 800251c:	20001e88 	.word	0x20001e88
 8002520:	20000e78 	.word	0x20000e78
 8002524:	20001e8a 	.word	0x20001e8a
 8002528:	20001e8b 	.word	0x20001e8b
 800252c:	20001e8c 	.word	0x20001e8c
 8002530:	20001e8d 	.word	0x20001e8d

08002534 <NegativeResponse>:
extern uint8_t ota_start_flag;

uint8_t app2_crc_flag = 0;//crc校验成功标志位，成功后应答版本号位新的。

void NegativeResponse(uint8_t sid,uint8_t NegativeResponseCode)
{
 8002534:	b580      	push	{r7, lr}
 8002536:	b08a      	sub	sp, #40	@ 0x28
 8002538:	af00      	add	r7, sp, #0
 800253a:	4603      	mov	r3, r0
 800253c:	460a      	mov	r2, r1
 800253e:	71fb      	strb	r3, [r7, #7]
 8002540:	4613      	mov	r3, r2
 8002542:	71bb      	strb	r3, [r7, #6]
	i15765_t msg_req;
	uint8_t buf[8];
	uint8_t status_rq;

	msg_req.ID = UDS_TX_ID;
 8002544:	4b0c      	ldr	r3, [pc, #48]	@ (8002578 <NegativeResponse+0x44>)
 8002546:	681b      	ldr	r3, [r3, #0]
 8002548:	627b      	str	r3, [r7, #36]	@ 0x24
	msg_req.buf = buf;
 800254a:	f107 0310 	add.w	r3, r7, #16
 800254e:	61fb      	str	r3, [r7, #28]

	buf[0] = 0x7F;//NegativeResponseServiceIdentifier
 8002550:	237f      	movs	r3, #127	@ 0x7f
 8002552:	743b      	strb	r3, [r7, #16]
	buf[1] = sid;
 8002554:	79fb      	ldrb	r3, [r7, #7]
 8002556:	747b      	strb	r3, [r7, #17]
	buf[2] = NegativeResponseCode;
 8002558:	79bb      	ldrb	r3, [r7, #6]
 800255a:	74bb      	strb	r3, [r7, #18]

	msg_req.buf_len = 3;
 800255c:	2303      	movs	r3, #3
 800255e:	843b      	strh	r3, [r7, #32]

	/* transmit message */
	i15765_tx_app(&msg_req, &status_rq);
 8002560:	f107 020f 	add.w	r2, r7, #15
 8002564:	f107 0318 	add.w	r3, r7, #24
 8002568:	4611      	mov	r1, r2
 800256a:	4618      	mov	r0, r3
 800256c:	f7ff fdd0 	bl	8002110 <i15765_tx_app>
}
 8002570:	bf00      	nop
 8002572:	3728      	adds	r7, #40	@ 0x28
 8002574:	46bd      	mov	sp, r7
 8002576:	bd80      	pop	{r7, pc}
 8002578:	08005de8 	.word	0x08005de8

0800257c <SID_11_function>:

void SID_11_function(i15765_t *msg)
{
 800257c:	b580      	push	{r7, lr}
 800257e:	b08a      	sub	sp, #40	@ 0x28
 8002580:	af00      	add	r7, sp, #0
 8002582:	6078      	str	r0, [r7, #4]
	i15765_t msg_req;
	uint8_t buf[8];
	uint8_t status_rq;
	uint8_t PositiveResponseEnable = 0;
 8002584:	2300      	movs	r3, #0
 8002586:	f887 3027 	strb.w	r3, [r7, #39]	@ 0x27

	uint8_t SuppressPosRspMsgIndicationBit;
	uint8_t ResetType;

	/* basic stuff */
	msg_req.buf = buf;
 800258a:	f107 030c 	add.w	r3, r7, #12
 800258e:	61bb      	str	r3, [r7, #24]
	msg_req.pri = 6;
 8002590:	2306      	movs	r3, #6
 8002592:	75bb      	strb	r3, [r7, #22]
	msg_req.ta = 0x0C;
 8002594:	230c      	movs	r3, #12
 8002596:	757b      	strb	r3, [r7, #21]

	if(msg->tat == I15765_TAT_NF11)
 8002598:	687b      	ldr	r3, [r7, #4]
 800259a:	78db      	ldrb	r3, [r3, #3]
 800259c:	2b77      	cmp	r3, #119	@ 0x77
 800259e:	d102      	bne.n	80025a6 <SID_11_function+0x2a>
	{
		msg_req.tat = I15765_TAT_NF11;
 80025a0:	2377      	movs	r3, #119	@ 0x77
 80025a2:	75fb      	strb	r3, [r7, #23]
 80025a4:	e001      	b.n	80025aa <SID_11_function+0x2e>
	}
	else
	{
		msg_req.tat = I15765_TAT_NP11;
 80025a6:	2376      	movs	r3, #118	@ 0x76
 80025a8:	75fb      	strb	r3, [r7, #23]
		NegativeResponse(msg->buf[0],0x7F);
		return;
	}
#endif

	if(DiagnosticSessionType==0x01)
 80025aa:	4b3a      	ldr	r3, [pc, #232]	@ (8002694 <SID_11_function+0x118>)
 80025ac:	781b      	ldrb	r3, [r3, #0]
 80025ae:	2b01      	cmp	r3, #1
 80025b0:	d107      	bne.n	80025c2 <SID_11_function+0x46>
	{
		NegativeResponse(msg->buf[0],0x7F);
 80025b2:	687b      	ldr	r3, [r7, #4]
 80025b4:	685b      	ldr	r3, [r3, #4]
 80025b6:	781b      	ldrb	r3, [r3, #0]
 80025b8:	217f      	movs	r1, #127	@ 0x7f
 80025ba:	4618      	mov	r0, r3
 80025bc:	f7ff ffba 	bl	8002534 <NegativeResponse>
		return;
 80025c0:	e065      	b.n	800268e <SID_11_function+0x112>
	}


	if(msg->buf_len!=2)
 80025c2:	687b      	ldr	r3, [r7, #4]
 80025c4:	891b      	ldrh	r3, [r3, #8]
 80025c6:	2b02      	cmp	r3, #2
 80025c8:	d007      	beq.n	80025da <SID_11_function+0x5e>
	{
		NegativeResponse(msg->buf[0],0x13);
 80025ca:	687b      	ldr	r3, [r7, #4]
 80025cc:	685b      	ldr	r3, [r3, #4]
 80025ce:	781b      	ldrb	r3, [r3, #0]
 80025d0:	2113      	movs	r1, #19
 80025d2:	4618      	mov	r0, r3
 80025d4:	f7ff ffae 	bl	8002534 <NegativeResponse>
		return;
 80025d8:	e059      	b.n	800268e <SID_11_function+0x112>
	}

	SuppressPosRspMsgIndicationBit = msg->buf[1]&0x80;
 80025da:	687b      	ldr	r3, [r7, #4]
 80025dc:	685b      	ldr	r3, [r3, #4]
 80025de:	3301      	adds	r3, #1
 80025e0:	781b      	ldrb	r3, [r3, #0]
 80025e2:	f023 037f 	bic.w	r3, r3, #127	@ 0x7f
 80025e6:	f887 3026 	strb.w	r3, [r7, #38]	@ 0x26
	ResetType = msg->buf[1]&0x7F;
 80025ea:	687b      	ldr	r3, [r7, #4]
 80025ec:	685b      	ldr	r3, [r3, #4]
 80025ee:	3301      	adds	r3, #1
 80025f0:	781b      	ldrb	r3, [r3, #0]
 80025f2:	f003 037f 	and.w	r3, r3, #127	@ 0x7f
 80025f6:	f887 3025 	strb.w	r3, [r7, #37]	@ 0x25

	switch(ResetType)
 80025fa:	f897 3025 	ldrb.w	r3, [r7, #37]	@ 0x25
 80025fe:	2b01      	cmp	r3, #1
 8002600:	d002      	beq.n	8002608 <SID_11_function+0x8c>
 8002602:	2b03      	cmp	r3, #3
 8002604:	d01c      	beq.n	8002640 <SID_11_function+0xc4>
 8002606:	e037      	b.n	8002678 <SID_11_function+0xfc>
	{
		case 0x01:
		{
			if(1)
			{
				PositiveResponseEnable = 1;
 8002608:	2301      	movs	r3, #1
 800260a:	f887 3027 	strb.w	r3, [r7, #39]	@ 0x27
				buf[0] = msg->buf[0]+0x40;// PositiveResponseServiceIdentifier
 800260e:	687b      	ldr	r3, [r7, #4]
 8002610:	685b      	ldr	r3, [r3, #4]
 8002612:	781b      	ldrb	r3, [r3, #0]
 8002614:	3340      	adds	r3, #64	@ 0x40
 8002616:	b2db      	uxtb	r3, r3
 8002618:	733b      	strb	r3, [r7, #12]
				buf[1] = msg->buf[1];// Sub-Function=ResetType
 800261a:	687b      	ldr	r3, [r7, #4]
 800261c:	685b      	ldr	r3, [r3, #4]
 800261e:	785b      	ldrb	r3, [r3, #1]
 8002620:	737b      	strb	r3, [r7, #13]

				msg_req.buf_len = 2;
 8002622:	2302      	movs	r3, #2
 8002624:	83bb      	strh	r3, [r7, #28]
				if(SuppressPosRspMsgIndicationBit != 0x80)
 8002626:	f897 3026 	ldrb.w	r3, [r7, #38]	@ 0x26
 800262a:	2b80      	cmp	r3, #128	@ 0x80
 800262c:	d02c      	beq.n	8002688 <SID_11_function+0x10c>
				{
					i15765_tx_app(&msg_req, &status_rq);
 800262e:	f107 020b 	add.w	r2, r7, #11
 8002632:	f107 0314 	add.w	r3, r7, #20
 8002636:	4611      	mov	r1, r2
 8002638:	4618      	mov	r0, r3
 800263a:	f7ff fd69 	bl	8002110 <i15765_tx_app>
				PositiveResponseEnable = 0;
				NegativeResponse(msg->buf[0],0x22);
				return;
			}

			break;
 800263e:	e023      	b.n	8002688 <SID_11_function+0x10c>
		case 0x03:
		{

			if(1)
			{
				PositiveResponseEnable = 1;
 8002640:	2301      	movs	r3, #1
 8002642:	f887 3027 	strb.w	r3, [r7, #39]	@ 0x27
				buf[0] = msg->buf[0]+0x40;// PositiveResponseServiceIdentifier
 8002646:	687b      	ldr	r3, [r7, #4]
 8002648:	685b      	ldr	r3, [r3, #4]
 800264a:	781b      	ldrb	r3, [r3, #0]
 800264c:	3340      	adds	r3, #64	@ 0x40
 800264e:	b2db      	uxtb	r3, r3
 8002650:	733b      	strb	r3, [r7, #12]
				buf[1] = msg->buf[1];// Sub-Function=ResetType
 8002652:	687b      	ldr	r3, [r7, #4]
 8002654:	685b      	ldr	r3, [r3, #4]
 8002656:	785b      	ldrb	r3, [r3, #1]
 8002658:	737b      	strb	r3, [r7, #13]

				msg_req.buf_len = 2;
 800265a:	2302      	movs	r3, #2
 800265c:	83bb      	strh	r3, [r7, #28]
				if(SuppressPosRspMsgIndicationBit != 0x80)
 800265e:	f897 3026 	ldrb.w	r3, [r7, #38]	@ 0x26
 8002662:	2b80      	cmp	r3, #128	@ 0x80
 8002664:	d012      	beq.n	800268c <SID_11_function+0x110>
				{
					i15765_tx_app(&msg_req, &status_rq);
 8002666:	f107 020b 	add.w	r2, r7, #11
 800266a:	f107 0314 	add.w	r3, r7, #20
 800266e:	4611      	mov	r1, r2
 8002670:	4618      	mov	r0, r3
 8002672:	f7ff fd4d 	bl	8002110 <i15765_tx_app>
				PositiveResponseEnable = 0;
				NegativeResponse(msg->buf[0],0x22);
				return;
			}

			break;
 8002676:	e009      	b.n	800268c <SID_11_function+0x110>
		}
		default:
		{
			NegativeResponse(msg->buf[0],0x12);
 8002678:	687b      	ldr	r3, [r7, #4]
 800267a:	685b      	ldr	r3, [r3, #4]
 800267c:	781b      	ldrb	r3, [r3, #0]
 800267e:	2112      	movs	r1, #18
 8002680:	4618      	mov	r0, r3
 8002682:	f7ff ff57 	bl	8002534 <NegativeResponse>
			return;
 8002686:	e002      	b.n	800268e <SID_11_function+0x112>
			break;
 8002688:	bf00      	nop
 800268a:	e000      	b.n	800268e <SID_11_function+0x112>
			break;
 800268c:	bf00      	nop
		if(ResetType == 0x03)//SoftReset
		{
			//JumpReset();
		}
	}
}
 800268e:	3728      	adds	r7, #40	@ 0x28
 8002690:	46bd      	mov	sp, r7
 8002692:	bd80      	pop	{r7, pc}
 8002694:	20000009 	.word	0x20000009

08002698 <SID_31_function>:
		i15765_tx_app(&msg_req, &status_rq);
	}
}

void SID_31_function(i15765_t *msg)
{
 8002698:	b580      	push	{r7, lr}
 800269a:	b090      	sub	sp, #64	@ 0x40
 800269c:	af00      	add	r7, sp, #0
 800269e:	6078      	str	r0, [r7, #4]
    i15765_t msg_req = {0};
 80026a0:	f107 0320 	add.w	r3, r7, #32
 80026a4:	2200      	movs	r2, #0
 80026a6:	601a      	str	r2, [r3, #0]
 80026a8:	605a      	str	r2, [r3, #4]
 80026aa:	609a      	str	r2, [r3, #8]
 80026ac:	60da      	str	r2, [r3, #12]
    uint8_t response_buf[20] = {0};
 80026ae:	f107 030c 	add.w	r3, r7, #12
 80026b2:	2200      	movs	r2, #0
 80026b4:	601a      	str	r2, [r3, #0]
 80026b6:	605a      	str	r2, [r3, #4]
 80026b8:	609a      	str	r2, [r3, #8]
 80026ba:	60da      	str	r2, [r3, #12]
 80026bc:	611a      	str	r2, [r3, #16]
    uint8_t status_rq = 0;
 80026be:	2300      	movs	r3, #0
 80026c0:	72fb      	strb	r3, [r7, #11]
    uint8_t PositiveResponseEnable = 0;
 80026c2:	2300      	movs	r3, #0
 80026c4:	f887 303f 	strb.w	r3, [r7, #63]	@ 0x3f
	int oReturnCheck;//
    uint8_t result_code = 0x00;
 80026c8:	2300      	movs	r3, #0
 80026ca:	f887 303e 	strb.w	r3, [r7, #62]	@ 0x3e
    // 初始化请求消息
	msg_req.pri = 6;
 80026ce:	2306      	movs	r3, #6
 80026d0:	f887 3022 	strb.w	r3, [r7, #34]	@ 0x22
	msg_req.ta = 0x0C;
 80026d4:	230c      	movs	r3, #12
 80026d6:	f887 3021 	strb.w	r3, [r7, #33]	@ 0x21
	msg_req.buf = response_buf;
 80026da:	f107 030c 	add.w	r3, r7, #12
 80026de:	627b      	str	r3, [r7, #36]	@ 0x24
	if(msg->tat == I15765_TAT_NF11)
 80026e0:	687b      	ldr	r3, [r7, #4]
 80026e2:	78db      	ldrb	r3, [r3, #3]
 80026e4:	2b77      	cmp	r3, #119	@ 0x77
 80026e6:	d103      	bne.n	80026f0 <SID_31_function+0x58>
	{
		msg_req.tat = I15765_TAT_NF11;
 80026e8:	2377      	movs	r3, #119	@ 0x77
 80026ea:	f887 3023 	strb.w	r3, [r7, #35]	@ 0x23
 80026ee:	e002      	b.n	80026f6 <SID_31_function+0x5e>
	}
	else
	{
		msg_req.tat = I15765_TAT_NP11;
 80026f0:	2376      	movs	r3, #118	@ 0x76
 80026f2:	f887 3023 	strb.w	r3, [r7, #35]	@ 0x23
	}


    // 参数检查
    if (msg == NULL || msg->buf == NULL || msg->buf_len < 4)
 80026f6:	687b      	ldr	r3, [r7, #4]
 80026f8:	2b00      	cmp	r3, #0
 80026fa:	d007      	beq.n	800270c <SID_31_function+0x74>
 80026fc:	687b      	ldr	r3, [r7, #4]
 80026fe:	685b      	ldr	r3, [r3, #4]
 8002700:	2b00      	cmp	r3, #0
 8002702:	d003      	beq.n	800270c <SID_31_function+0x74>
 8002704:	687b      	ldr	r3, [r7, #4]
 8002706:	891b      	ldrh	r3, [r3, #8]
 8002708:	2b03      	cmp	r3, #3
 800270a:	d804      	bhi.n	8002716 <SID_31_function+0x7e>
    {
        NegativeResponse(0x31, 0x13); // 参数长度错误
 800270c:	2113      	movs	r1, #19
 800270e:	2031      	movs	r0, #49	@ 0x31
 8002710:	f7ff ff10 	bl	8002534 <NegativeResponse>
        return;
 8002714:	e1f2      	b.n	8002afc <SID_31_function+0x464>
    }

    // 检查RoutineControl类型
    uint8_t RoutineControlType = msg->buf[1] & 0x7F;
 8002716:	687b      	ldr	r3, [r7, #4]
 8002718:	685b      	ldr	r3, [r3, #4]
 800271a:	3301      	adds	r3, #1
 800271c:	781b      	ldrb	r3, [r3, #0]
 800271e:	f003 037f 	and.w	r3, r3, #127	@ 0x7f
 8002722:	f887 3037 	strb.w	r3, [r7, #55]	@ 0x37
    if (RoutineControlType != 0x01) // 只支持StartRoutine
 8002726:	f897 3037 	ldrb.w	r3, [r7, #55]	@ 0x37
 800272a:	2b01      	cmp	r3, #1
 800272c:	d007      	beq.n	800273e <SID_31_function+0xa6>
    {
        NegativeResponse(msg->buf[0], 0x12); // 不支持的服务类型
 800272e:	687b      	ldr	r3, [r7, #4]
 8002730:	685b      	ldr	r3, [r3, #4]
 8002732:	781b      	ldrb	r3, [r3, #0]
 8002734:	2112      	movs	r1, #18
 8002736:	4618      	mov	r0, r3
 8002738:	f7ff fefc 	bl	8002534 <NegativeResponse>
        return;
 800273c:	e1de      	b.n	8002afc <SID_31_function+0x464>
    }

    uint16_t RoutineIdentifier = (uint16_t)msg->buf[2] << 8 | msg->buf[3];
 800273e:	687b      	ldr	r3, [r7, #4]
 8002740:	685b      	ldr	r3, [r3, #4]
 8002742:	3302      	adds	r3, #2
 8002744:	781b      	ldrb	r3, [r3, #0]
 8002746:	b21b      	sxth	r3, r3
 8002748:	021b      	lsls	r3, r3, #8
 800274a:	b21a      	sxth	r2, r3
 800274c:	687b      	ldr	r3, [r7, #4]
 800274e:	685b      	ldr	r3, [r3, #4]
 8002750:	3303      	adds	r3, #3
 8002752:	781b      	ldrb	r3, [r3, #0]
 8002754:	b21b      	sxth	r3, r3
 8002756:	4313      	orrs	r3, r2
 8002758:	b21b      	sxth	r3, r3
 800275a:	86bb      	strh	r3, [r7, #52]	@ 0x34

    // 处理不同的RoutineIdentifier
    switch (RoutineIdentifier)
 800275c:	8ebb      	ldrh	r3, [r7, #52]	@ 0x34
 800275e:	f5b3 4f7f 	cmp.w	r3, #65280	@ 0xff00
 8002762:	d03c      	beq.n	80027de <SID_31_function+0x146>
 8002764:	f5b3 4f7f 	cmp.w	r3, #65280	@ 0xff00
 8002768:	f300 819d 	bgt.w	8002aa6 <SID_31_function+0x40e>
 800276c:	f640 620f 	movw	r2, #3599	@ 0xe0f
 8002770:	4293      	cmp	r3, r2
 8002772:	f000 8108 	beq.w	8002986 <SID_31_function+0x2ee>
 8002776:	f5b3 6f61 	cmp.w	r3, #3600	@ 0xe10
 800277a:	f280 8194 	bge.w	8002aa6 <SID_31_function+0x40e>
 800277e:	f640 620e 	movw	r2, #3598	@ 0xe0e
 8002782:	4293      	cmp	r3, r2
 8002784:	f000 80d1 	beq.w	800292a <SID_31_function+0x292>
 8002788:	f640 620e 	movw	r2, #3598	@ 0xe0e
 800278c:	4293      	cmp	r3, r2
 800278e:	f300 818a 	bgt.w	8002aa6 <SID_31_function+0x40e>
 8002792:	f240 2202 	movw	r2, #514	@ 0x202
 8002796:	4293      	cmp	r3, r2
 8002798:	f000 8088 	beq.w	80028ac <SID_31_function+0x214>
 800279c:	f240 2203 	movw	r2, #515	@ 0x203
 80027a0:	4293      	cmp	r3, r2
 80027a2:	f040 8180 	bne.w	8002aa6 <SID_31_function+0x40e>
    {
        case 0x0203: // 请求升级
            if (msg->buf_len != 4)
 80027a6:	687b      	ldr	r3, [r7, #4]
 80027a8:	891b      	ldrh	r3, [r3, #8]
 80027aa:	2b04      	cmp	r3, #4
 80027ac:	d007      	beq.n	80027be <SID_31_function+0x126>
            {
                NegativeResponse(msg->buf[0], 0x13);
 80027ae:	687b      	ldr	r3, [r7, #4]
 80027b0:	685b      	ldr	r3, [r3, #4]
 80027b2:	781b      	ldrb	r3, [r3, #0]
 80027b4:	2113      	movs	r1, #19
 80027b6:	4618      	mov	r0, r3
 80027b8:	f7ff febc 	bl	8002534 <NegativeResponse>
                return;
 80027bc:	e19e      	b.n	8002afc <SID_31_function+0x464>
            }
            ota_start_flag = 1;
 80027be:	4ba2      	ldr	r3, [pc, #648]	@ (8002a48 <SID_31_function+0x3b0>)
 80027c0:	2201      	movs	r2, #1
 80027c2:	701a      	strb	r2, [r3, #0]
            result_code = 0x00;
 80027c4:	2300      	movs	r3, #0
 80027c6:	f887 303e 	strb.w	r3, [r7, #62]	@ 0x3e
            load_sequence_state = 0x00;
 80027ca:	4ba0      	ldr	r3, [pc, #640]	@ (8002a4c <SID_31_function+0x3b4>)
 80027cc:	2200      	movs	r2, #0
 80027ce:	701a      	strb	r2, [r3, #0]
            app2_crc_flag = 0;
 80027d0:	4b9f      	ldr	r3, [pc, #636]	@ (8002a50 <SID_31_function+0x3b8>)
 80027d2:	2200      	movs	r2, #0
 80027d4:	701a      	strb	r2, [r3, #0]
            PositiveResponseEnable = 1;
 80027d6:	2301      	movs	r3, #1
 80027d8:	f887 303f 	strb.w	r3, [r7, #63]	@ 0x3f
            break;
 80027dc:	e16b      	b.n	8002ab6 <SID_31_function+0x41e>

        case 0xFF00: // 擦除Flash
            if (msg->buf_len != 13)
 80027de:	687b      	ldr	r3, [r7, #4]
 80027e0:	891b      	ldrh	r3, [r3, #8]
 80027e2:	2b0d      	cmp	r3, #13
 80027e4:	d007      	beq.n	80027f6 <SID_31_function+0x15e>
            {
                NegativeResponse(msg->buf[0], 0x13);
 80027e6:	687b      	ldr	r3, [r7, #4]
 80027e8:	685b      	ldr	r3, [r3, #4]
 80027ea:	781b      	ldrb	r3, [r3, #0]
 80027ec:	2113      	movs	r1, #19
 80027ee:	4618      	mov	r0, r3
 80027f0:	f7ff fea0 	bl	8002534 <NegativeResponse>
                return;
 80027f4:	e182      	b.n	8002afc <SID_31_function+0x464>
            }

            // 提取擦除地址和大小
            earse_MemoryAddress = (uint32_t)((msg->buf[5] << 24) | (msg->buf[6] << 16) | (msg->buf[7] << 8) | msg->buf[8]);
 80027f6:	687b      	ldr	r3, [r7, #4]
 80027f8:	685b      	ldr	r3, [r3, #4]
 80027fa:	3305      	adds	r3, #5
 80027fc:	781b      	ldrb	r3, [r3, #0]
 80027fe:	061a      	lsls	r2, r3, #24
 8002800:	687b      	ldr	r3, [r7, #4]
 8002802:	685b      	ldr	r3, [r3, #4]
 8002804:	3306      	adds	r3, #6
 8002806:	781b      	ldrb	r3, [r3, #0]
 8002808:	041b      	lsls	r3, r3, #16
 800280a:	431a      	orrs	r2, r3
 800280c:	687b      	ldr	r3, [r7, #4]
 800280e:	685b      	ldr	r3, [r3, #4]
 8002810:	3307      	adds	r3, #7
 8002812:	781b      	ldrb	r3, [r3, #0]
 8002814:	021b      	lsls	r3, r3, #8
 8002816:	4313      	orrs	r3, r2
 8002818:	687a      	ldr	r2, [r7, #4]
 800281a:	6852      	ldr	r2, [r2, #4]
 800281c:	3208      	adds	r2, #8
 800281e:	7812      	ldrb	r2, [r2, #0]
 8002820:	4313      	orrs	r3, r2
 8002822:	461a      	mov	r2, r3
 8002824:	4b8b      	ldr	r3, [pc, #556]	@ (8002a54 <SID_31_function+0x3bc>)
 8002826:	601a      	str	r2, [r3, #0]
            earse_MemorySize = (uint32_t)((msg->buf[9] << 24) | (msg->buf[10] << 16) | (msg->buf[11] << 8) | msg->buf[12]);
 8002828:	687b      	ldr	r3, [r7, #4]
 800282a:	685b      	ldr	r3, [r3, #4]
 800282c:	3309      	adds	r3, #9
 800282e:	781b      	ldrb	r3, [r3, #0]
 8002830:	061a      	lsls	r2, r3, #24
 8002832:	687b      	ldr	r3, [r7, #4]
 8002834:	685b      	ldr	r3, [r3, #4]
 8002836:	330a      	adds	r3, #10
 8002838:	781b      	ldrb	r3, [r3, #0]
 800283a:	041b      	lsls	r3, r3, #16
 800283c:	431a      	orrs	r2, r3
 800283e:	687b      	ldr	r3, [r7, #4]
 8002840:	685b      	ldr	r3, [r3, #4]
 8002842:	330b      	adds	r3, #11
 8002844:	781b      	ldrb	r3, [r3, #0]
 8002846:	021b      	lsls	r3, r3, #8
 8002848:	4313      	orrs	r3, r2
 800284a:	687a      	ldr	r2, [r7, #4]
 800284c:	6852      	ldr	r2, [r2, #4]
 800284e:	320c      	adds	r2, #12
 8002850:	7812      	ldrb	r2, [r2, #0]
 8002852:	4313      	orrs	r3, r2
 8002854:	461a      	mov	r2, r3
 8002856:	4b80      	ldr	r3, [pc, #512]	@ (8002a58 <SID_31_function+0x3c0>)
 8002858:	601a      	str	r2, [r3, #0]

            // 验证地址范围
            //if ((earse_MemoryAddress != APP_START_ADDRESS) || (earse_MemorySize > (APP_STOP_ADDRESS - APP_START_ADDRESS)))
			//if ((earse_MemoryAddress != APP2_ADDRESS) || (earse_MemorySize > (APP2_ADDRESS - APP1_ADDRESS)))
			if ((earse_MemoryAddress != APP1_ADDRESS) || (earse_MemorySize > (APP2_ADDRESS - APP1_ADDRESS)))
 800285a:	4b7e      	ldr	r3, [pc, #504]	@ (8002a54 <SID_31_function+0x3bc>)
 800285c:	681b      	ldr	r3, [r3, #0]
 800285e:	4a7f      	ldr	r2, [pc, #508]	@ (8002a5c <SID_31_function+0x3c4>)
 8002860:	4293      	cmp	r3, r2
 8002862:	d104      	bne.n	800286e <SID_31_function+0x1d6>
 8002864:	4b7c      	ldr	r3, [pc, #496]	@ (8002a58 <SID_31_function+0x3c0>)
 8002866:	681b      	ldr	r3, [r3, #0]
 8002868:	f5b3 2fa8 	cmp.w	r3, #344064	@ 0x54000
 800286c:	d907      	bls.n	800287e <SID_31_function+0x1e6>
            {
                NegativeResponse(msg->buf[0], 0x31);
 800286e:	687b      	ldr	r3, [r7, #4]
 8002870:	685b      	ldr	r3, [r3, #4]
 8002872:	781b      	ldrb	r3, [r3, #0]
 8002874:	2131      	movs	r1, #49	@ 0x31
 8002876:	4618      	mov	r0, r3
 8002878:	f7ff fe5c 	bl	8002534 <NegativeResponse>
                return;
 800287c:	e13e      	b.n	8002afc <SID_31_function+0x464>
            }

            // 执行擦除操作
            oReturnCheck = flash_erase_app(2);
 800287e:	2002      	movs	r0, #2
 8002880:	f7fe f9ae 	bl	8000be0 <flash_erase_app>
 8002884:	6338      	str	r0, [r7, #48]	@ 0x30

            // 根据擦除结果设置响应
            result_code = (oReturnCheck == 0) ? 0x00 : 0x01;
 8002886:	6b3b      	ldr	r3, [r7, #48]	@ 0x30
 8002888:	2b00      	cmp	r3, #0
 800288a:	bf14      	ite	ne
 800288c:	2301      	movne	r3, #1
 800288e:	2300      	moveq	r3, #0
 8002890:	b2db      	uxtb	r3, r3
 8002892:	f887 303e 	strb.w	r3, [r7, #62]	@ 0x3e
            if (result_code == 0x00)
 8002896:	f897 303e 	ldrb.w	r3, [r7, #62]	@ 0x3e
 800289a:	2b00      	cmp	r3, #0
 800289c:	d102      	bne.n	80028a4 <SID_31_function+0x20c>
            {
                load_sequence_state = 0x01; // 进入数据传输流程
 800289e:	4b6b      	ldr	r3, [pc, #428]	@ (8002a4c <SID_31_function+0x3b4>)
 80028a0:	2201      	movs	r2, #1
 80028a2:	701a      	strb	r2, [r3, #0]
            }

            PositiveResponseEnable = 1;
 80028a4:	2301      	movs	r3, #1
 80028a6:	f887 303f 	strb.w	r3, [r7, #63]	@ 0x3f
            break;
 80028aa:	e104      	b.n	8002ab6 <SID_31_function+0x41e>

        case 0x0202: // CRC32验证
            if (msg->buf_len != 8)
 80028ac:	687b      	ldr	r3, [r7, #4]
 80028ae:	891b      	ldrh	r3, [r3, #8]
 80028b0:	2b08      	cmp	r3, #8
 80028b2:	d007      	beq.n	80028c4 <SID_31_function+0x22c>
            {
                NegativeResponse(msg->buf[0], 0x13);
 80028b4:	687b      	ldr	r3, [r7, #4]
 80028b6:	685b      	ldr	r3, [r3, #4]
 80028b8:	781b      	ldrb	r3, [r3, #0]
 80028ba:	2113      	movs	r1, #19
 80028bc:	4618      	mov	r0, r3
 80028be:	f7ff fe39 	bl	8002534 <NegativeResponse>
                return;
 80028c2:	e11b      	b.n	8002afc <SID_31_function+0x464>
            }

            // 提取CRC32值
            CRC32_value = (uint32_t)(
                (msg->buf[4] << 24) |
 80028c4:	687b      	ldr	r3, [r7, #4]
 80028c6:	685b      	ldr	r3, [r3, #4]
 80028c8:	3304      	adds	r3, #4
 80028ca:	781b      	ldrb	r3, [r3, #0]
 80028cc:	061a      	lsls	r2, r3, #24
                (msg->buf[5] << 16) |
 80028ce:	687b      	ldr	r3, [r7, #4]
 80028d0:	685b      	ldr	r3, [r3, #4]
 80028d2:	3305      	adds	r3, #5
 80028d4:	781b      	ldrb	r3, [r3, #0]
 80028d6:	041b      	lsls	r3, r3, #16
                (msg->buf[4] << 24) |
 80028d8:	431a      	orrs	r2, r3
                (msg->buf[6] << 8) |
 80028da:	687b      	ldr	r3, [r7, #4]
 80028dc:	685b      	ldr	r3, [r3, #4]
 80028de:	3306      	adds	r3, #6
 80028e0:	781b      	ldrb	r3, [r3, #0]
 80028e2:	021b      	lsls	r3, r3, #8
                (msg->buf[5] << 16) |
 80028e4:	4313      	orrs	r3, r2
                msg->buf[7]
 80028e6:	687a      	ldr	r2, [r7, #4]
 80028e8:	6852      	ldr	r2, [r2, #4]
 80028ea:	3207      	adds	r2, #7
 80028ec:	7812      	ldrb	r2, [r2, #0]
                (msg->buf[6] << 8) |
 80028ee:	4313      	orrs	r3, r2
            CRC32_value = (uint32_t)(
 80028f0:	461a      	mov	r2, r3
 80028f2:	4b5b      	ldr	r3, [pc, #364]	@ (8002a60 <SID_31_function+0x3c8>)
 80028f4:	601a      	str	r2, [r3, #0]
            );

            // 验证CRC32
            result_code = (CRC32_value == crc32val) ? 0x00 : 0x01;
 80028f6:	4b5a      	ldr	r3, [pc, #360]	@ (8002a60 <SID_31_function+0x3c8>)
 80028f8:	681a      	ldr	r2, [r3, #0]
 80028fa:	4b5a      	ldr	r3, [pc, #360]	@ (8002a64 <SID_31_function+0x3cc>)
 80028fc:	681b      	ldr	r3, [r3, #0]
 80028fe:	429a      	cmp	r2, r3
 8002900:	bf14      	ite	ne
 8002902:	2301      	movne	r3, #1
 8002904:	2300      	moveq	r3, #0
 8002906:	b2db      	uxtb	r3, r3
 8002908:	f887 303e 	strb.w	r3, [r7, #62]	@ 0x3e
            if(result_code==0)//校验成功
 800290c:	f897 303e 	ldrb.w	r3, [r7, #62]	@ 0x3e
 8002910:	2b00      	cmp	r3, #0
 8002912:	d103      	bne.n	800291c <SID_31_function+0x284>
            {
            	app2_crc_flag = 1;
 8002914:	4b4e      	ldr	r3, [pc, #312]	@ (8002a50 <SID_31_function+0x3b8>)
 8002916:	2201      	movs	r2, #1
 8002918:	701a      	strb	r2, [r3, #0]
 800291a:	e002      	b.n	8002922 <SID_31_function+0x28a>
            }
            else
            {
            	app2_crc_flag = 0;
 800291c:	4b4c      	ldr	r3, [pc, #304]	@ (8002a50 <SID_31_function+0x3b8>)
 800291e:	2200      	movs	r2, #0
 8002920:	701a      	strb	r2, [r3, #0]
            }
            PositiveResponseEnable = 1;
 8002922:	2301      	movs	r3, #1
 8002924:	f887 303f 	strb.w	r3, [r7, #63]	@ 0x3f
            break;
 8002928:	e0c5      	b.n	8002ab6 <SID_31_function+0x41e>

        case 0x0E0E: // 切换旧app版本
            if (msg->buf_len != 4)
 800292a:	687b      	ldr	r3, [r7, #4]
 800292c:	891b      	ldrh	r3, [r3, #8]
 800292e:	2b04      	cmp	r3, #4
 8002930:	d007      	beq.n	8002942 <SID_31_function+0x2aa>
            {
                NegativeResponse(msg->buf[0], 0x13);
 8002932:	687b      	ldr	r3, [r7, #4]
 8002934:	685b      	ldr	r3, [r3, #4]
 8002936:	781b      	ldrb	r3, [r3, #0]
 8002938:	2113      	movs	r1, #19
 800293a:	4618      	mov	r0, r3
 800293c:	f7ff fdfa 	bl	8002534 <NegativeResponse>
                return;
 8002940:	e0dc      	b.n	8002afc <SID_31_function+0x464>
            }

			response_buf[0] = msg->buf[0] + 0x40; // 正响应服务ID
 8002942:	687b      	ldr	r3, [r7, #4]
 8002944:	685b      	ldr	r3, [r3, #4]
 8002946:	781b      	ldrb	r3, [r3, #0]
 8002948:	3340      	adds	r3, #64	@ 0x40
 800294a:	b2db      	uxtb	r3, r3
 800294c:	733b      	strb	r3, [r7, #12]
			response_buf[1] = msg->buf[1];        // RoutineControlType
 800294e:	687b      	ldr	r3, [r7, #4]
 8002950:	685b      	ldr	r3, [r3, #4]
 8002952:	785b      	ldrb	r3, [r3, #1]
 8002954:	737b      	strb	r3, [r7, #13]
			response_buf[2] = msg->buf[2];        // RoutineIdentifier高字节
 8002956:	687b      	ldr	r3, [r7, #4]
 8002958:	685b      	ldr	r3, [r3, #4]
 800295a:	789b      	ldrb	r3, [r3, #2]
 800295c:	73bb      	strb	r3, [r7, #14]
			response_buf[3] = msg->buf[3];        // RoutineIdentifier低字节
 800295e:	687b      	ldr	r3, [r7, #4]
 8002960:	685b      	ldr	r3, [r3, #4]
 8002962:	78db      	ldrb	r3, [r3, #3]
 8002964:	73fb      	strb	r3, [r7, #15]
			response_buf[4] = 0;        // 结果代码
 8002966:	2300      	movs	r3, #0
 8002968:	743b      	strb	r3, [r7, #16]

			// 设置响应消息长度
			msg_req.buf_len = 5;
 800296a:	2305      	movs	r3, #5
 800296c:	853b      	strh	r3, [r7, #40]	@ 0x28

			// 发送响应
			i15765_tx_app(&msg_req, &status_rq);
 800296e:	f107 020b 	add.w	r2, r7, #11
 8002972:	f107 0320 	add.w	r3, r7, #32
 8002976:	4611      	mov	r1, r2
 8002978:	4618      	mov	r0, r3
 800297a:	f7ff fbc9 	bl	8002110 <i15765_tx_app>
			jump_to_app(APP1_ADDRESS);
 800297e:	4837      	ldr	r0, [pc, #220]	@ (8002a5c <SID_31_function+0x3c4>)
 8002980:	f7fe fa36 	bl	8000df0 <jump_to_app>
            break;
 8002984:	e097      	b.n	8002ab6 <SID_31_function+0x41e>

        case 0x0E0F: // 切换新app版本
            if (msg->buf_len != 4)
 8002986:	687b      	ldr	r3, [r7, #4]
 8002988:	891b      	ldrh	r3, [r3, #8]
 800298a:	2b04      	cmp	r3, #4
 800298c:	d007      	beq.n	800299e <SID_31_function+0x306>
            {
                NegativeResponse(msg->buf[0], 0x13);
 800298e:	687b      	ldr	r3, [r7, #4]
 8002990:	685b      	ldr	r3, [r3, #4]
 8002992:	781b      	ldrb	r3, [r3, #0]
 8002994:	2113      	movs	r1, #19
 8002996:	4618      	mov	r0, r3
 8002998:	f7ff fdcc 	bl	8002534 <NegativeResponse>
                return;
 800299c:	e0ae      	b.n	8002afc <SID_31_function+0x464>
            }
#if 1
			//计算固件大小，判断是否可以双备份升级
			if(earse_MemorySize < (APP2_ADDRESS - APP1_ADDRESS))
 800299e:	4b2e      	ldr	r3, [pc, #184]	@ (8002a58 <SID_31_function+0x3c0>)
 80029a0:	681b      	ldr	r3, [r3, #0]
 80029a2:	f5b3 2fa8 	cmp.w	r3, #344064	@ 0x54000
 80029a6:	d27e      	bcs.n	8002aa6 <SID_31_function+0x40e>
			{
				//flash_copy_app();
				app2_copy_to_app1();
 80029a8:	f7fe f9fb 	bl	8000da2 <app2_copy_to_app1>
				//校验CRC
				crc32val = 0xFFFFFFFF;
 80029ac:	4b2d      	ldr	r3, [pc, #180]	@ (8002a64 <SID_31_function+0x3cc>)
 80029ae:	f04f 32ff 	mov.w	r2, #4294967295
 80029b2:	601a      	str	r2, [r3, #0]
				uint8_t app2_data[1];
				for(uint32_t i = 0;i < earse_MemorySize; i++)
 80029b4:	2300      	movs	r3, #0
 80029b6:	63bb      	str	r3, [r7, #56]	@ 0x38
 80029b8:	e015      	b.n	80029e6 <SID_31_function+0x34e>
				{
					app2_data[0] = *(volatile uint8_t*)(APP1_ADDRESS + i);
 80029ba:	6bbb      	ldr	r3, [r7, #56]	@ 0x38
 80029bc:	f103 6300 	add.w	r3, r3, #134217728	@ 0x8000000
 80029c0:	f503 4340 	add.w	r3, r3, #49152	@ 0xc000
 80029c4:	781b      	ldrb	r3, [r3, #0]
 80029c6:	b2db      	uxtb	r3, r3
 80029c8:	723b      	strb	r3, [r7, #8]
					crc32val = crc32(crc32val, app2_data, 1);
 80029ca:	4b26      	ldr	r3, [pc, #152]	@ (8002a64 <SID_31_function+0x3cc>)
 80029cc:	681b      	ldr	r3, [r3, #0]
 80029ce:	f107 0108 	add.w	r1, r7, #8
 80029d2:	2201      	movs	r2, #1
 80029d4:	4618      	mov	r0, r3
 80029d6:	f7fe fd41 	bl	800145c <crc32>
 80029da:	4603      	mov	r3, r0
 80029dc:	4a21      	ldr	r2, [pc, #132]	@ (8002a64 <SID_31_function+0x3cc>)
 80029de:	6013      	str	r3, [r2, #0]
				for(uint32_t i = 0;i < earse_MemorySize; i++)
 80029e0:	6bbb      	ldr	r3, [r7, #56]	@ 0x38
 80029e2:	3301      	adds	r3, #1
 80029e4:	63bb      	str	r3, [r7, #56]	@ 0x38
 80029e6:	4b1c      	ldr	r3, [pc, #112]	@ (8002a58 <SID_31_function+0x3c0>)
 80029e8:	681b      	ldr	r3, [r3, #0]
 80029ea:	6bba      	ldr	r2, [r7, #56]	@ 0x38
 80029ec:	429a      	cmp	r2, r3
 80029ee:	d3e4      	bcc.n	80029ba <SID_31_function+0x322>
				}
				if(CRC32_value == crc32val)
 80029f0:	4b1b      	ldr	r3, [pc, #108]	@ (8002a60 <SID_31_function+0x3c8>)
 80029f2:	681a      	ldr	r2, [r3, #0]
 80029f4:	4b1b      	ldr	r3, [pc, #108]	@ (8002a64 <SID_31_function+0x3cc>)
 80029f6:	681b      	ldr	r3, [r3, #0]
 80029f8:	429a      	cmp	r2, r3
 80029fa:	d135      	bne.n	8002a68 <SID_31_function+0x3d0>
				{
	                response_buf[0] = msg->buf[0] + 0x40; // 正响应服务ID
 80029fc:	687b      	ldr	r3, [r7, #4]
 80029fe:	685b      	ldr	r3, [r3, #4]
 8002a00:	781b      	ldrb	r3, [r3, #0]
 8002a02:	3340      	adds	r3, #64	@ 0x40
 8002a04:	b2db      	uxtb	r3, r3
 8002a06:	733b      	strb	r3, [r7, #12]
	                response_buf[1] = msg->buf[1];        // RoutineControlType
 8002a08:	687b      	ldr	r3, [r7, #4]
 8002a0a:	685b      	ldr	r3, [r3, #4]
 8002a0c:	785b      	ldrb	r3, [r3, #1]
 8002a0e:	737b      	strb	r3, [r7, #13]
	                response_buf[2] = msg->buf[2];        // RoutineIdentifier高字节
 8002a10:	687b      	ldr	r3, [r7, #4]
 8002a12:	685b      	ldr	r3, [r3, #4]
 8002a14:	789b      	ldrb	r3, [r3, #2]
 8002a16:	73bb      	strb	r3, [r7, #14]
	                response_buf[3] = msg->buf[3];        // RoutineIdentifier低字节
 8002a18:	687b      	ldr	r3, [r7, #4]
 8002a1a:	685b      	ldr	r3, [r3, #4]
 8002a1c:	78db      	ldrb	r3, [r3, #3]
 8002a1e:	73fb      	strb	r3, [r7, #15]
	                response_buf[4] = 0;        // 结果代码
 8002a20:	2300      	movs	r3, #0
 8002a22:	743b      	strb	r3, [r7, #16]

	                // 设置响应消息长度
	                msg_req.buf_len = 5;
 8002a24:	2305      	movs	r3, #5
 8002a26:	853b      	strh	r3, [r7, #40]	@ 0x28

	                // 发送响应
	                i15765_tx_app(&msg_req, &status_rq);
 8002a28:	f107 020b 	add.w	r2, r7, #11
 8002a2c:	f107 0320 	add.w	r3, r7, #32
 8002a30:	4611      	mov	r1, r2
 8002a32:	4618      	mov	r0, r3
 8002a34:	f7ff fb6c 	bl	8002110 <i15765_tx_app>

					app_status_set(1,true);
 8002a38:	2101      	movs	r1, #1
 8002a3a:	2001      	movs	r0, #1
 8002a3c:	f7fe f90c 	bl	8000c58 <app_status_set>
					jump_to_app(APP1_ADDRESS);
 8002a40:	4806      	ldr	r0, [pc, #24]	@ (8002a5c <SID_31_function+0x3c4>)
 8002a42:	f7fe f9d5 	bl	8000df0 <jump_to_app>
 8002a46:	e02e      	b.n	8002aa6 <SID_31_function+0x40e>
 8002a48:	200000dc 	.word	0x200000dc
 8002a4c:	20001ea8 	.word	0x20001ea8
 8002a50:	20001eb8 	.word	0x20001eb8
 8002a54:	20001ea0 	.word	0x20001ea0
 8002a58:	20001ea4 	.word	0x20001ea4
 8002a5c:	0800c000 	.word	0x0800c000
 8002a60:	20001eb0 	.word	0x20001eb0
 8002a64:	20000004 	.word	0x20000004
				}
				else
				{
	                response_buf[0] = msg->buf[0] + 0x40; // 正响应服务ID
 8002a68:	687b      	ldr	r3, [r7, #4]
 8002a6a:	685b      	ldr	r3, [r3, #4]
 8002a6c:	781b      	ldrb	r3, [r3, #0]
 8002a6e:	3340      	adds	r3, #64	@ 0x40
 8002a70:	b2db      	uxtb	r3, r3
 8002a72:	733b      	strb	r3, [r7, #12]
	                response_buf[1] = msg->buf[1];        // RoutineControlType
 8002a74:	687b      	ldr	r3, [r7, #4]
 8002a76:	685b      	ldr	r3, [r3, #4]
 8002a78:	785b      	ldrb	r3, [r3, #1]
 8002a7a:	737b      	strb	r3, [r7, #13]
	                response_buf[2] = msg->buf[2];        // RoutineIdentifier高字节
 8002a7c:	687b      	ldr	r3, [r7, #4]
 8002a7e:	685b      	ldr	r3, [r3, #4]
 8002a80:	789b      	ldrb	r3, [r3, #2]
 8002a82:	73bb      	strb	r3, [r7, #14]
	                response_buf[3] = msg->buf[3];        // RoutineIdentifier低字节
 8002a84:	687b      	ldr	r3, [r7, #4]
 8002a86:	685b      	ldr	r3, [r3, #4]
 8002a88:	78db      	ldrb	r3, [r3, #3]
 8002a8a:	73fb      	strb	r3, [r7, #15]
	                response_buf[4] = 1;        // 结果代码
 8002a8c:	2301      	movs	r3, #1
 8002a8e:	743b      	strb	r3, [r7, #16]

	                // 设置响应消息长度
	                msg_req.buf_len = 5;
 8002a90:	2305      	movs	r3, #5
 8002a92:	853b      	strh	r3, [r7, #40]	@ 0x28

	                // 发送响应
	                i15765_tx_app(&msg_req, &status_rq);
 8002a94:	f107 020b 	add.w	r2, r7, #11
 8002a98:	f107 0320 	add.w	r3, r7, #32
 8002a9c:	4611      	mov	r1, r2
 8002a9e:	4618      	mov	r0, r3
 8002aa0:	f7ff fb36 	bl	8002110 <i15765_tx_app>
 8002aa4:	e02a      	b.n	8002afc <SID_31_function+0x464>
				}
			}
#endif

        default:
            NegativeResponse(msg->buf[0], 0x31); // 不支持的服务
 8002aa6:	687b      	ldr	r3, [r7, #4]
 8002aa8:	685b      	ldr	r3, [r3, #4]
 8002aaa:	781b      	ldrb	r3, [r3, #0]
 8002aac:	2131      	movs	r1, #49	@ 0x31
 8002aae:	4618      	mov	r0, r3
 8002ab0:	f7ff fd40 	bl	8002534 <NegativeResponse>
            return;
 8002ab4:	e022      	b.n	8002afc <SID_31_function+0x464>
    }

    // 发送正响应
    if (PositiveResponseEnable == 1)
 8002ab6:	f897 303f 	ldrb.w	r3, [r7, #63]	@ 0x3f
 8002aba:	2b01      	cmp	r3, #1
 8002abc:	d11e      	bne.n	8002afc <SID_31_function+0x464>
    {
        // 构建响应数据
        response_buf[0] = msg->buf[0] + 0x40; // 正响应服务ID
 8002abe:	687b      	ldr	r3, [r7, #4]
 8002ac0:	685b      	ldr	r3, [r3, #4]
 8002ac2:	781b      	ldrb	r3, [r3, #0]
 8002ac4:	3340      	adds	r3, #64	@ 0x40
 8002ac6:	b2db      	uxtb	r3, r3
 8002ac8:	733b      	strb	r3, [r7, #12]
        response_buf[1] = msg->buf[1];        // RoutineControlType
 8002aca:	687b      	ldr	r3, [r7, #4]
 8002acc:	685b      	ldr	r3, [r3, #4]
 8002ace:	785b      	ldrb	r3, [r3, #1]
 8002ad0:	737b      	strb	r3, [r7, #13]
        response_buf[2] = msg->buf[2];        // RoutineIdentifier高字节
 8002ad2:	687b      	ldr	r3, [r7, #4]
 8002ad4:	685b      	ldr	r3, [r3, #4]
 8002ad6:	789b      	ldrb	r3, [r3, #2]
 8002ad8:	73bb      	strb	r3, [r7, #14]
        response_buf[3] = msg->buf[3];        // RoutineIdentifier低字节
 8002ada:	687b      	ldr	r3, [r7, #4]
 8002adc:	685b      	ldr	r3, [r3, #4]
 8002ade:	78db      	ldrb	r3, [r3, #3]
 8002ae0:	73fb      	strb	r3, [r7, #15]
        response_buf[4] = result_code;        // 结果代码
 8002ae2:	f897 303e 	ldrb.w	r3, [r7, #62]	@ 0x3e
 8002ae6:	743b      	strb	r3, [r7, #16]

        // 设置响应消息长度
        msg_req.buf_len = 5;
 8002ae8:	2305      	movs	r3, #5
 8002aea:	853b      	strh	r3, [r7, #40]	@ 0x28

        // 发送响应
        i15765_tx_app(&msg_req, &status_rq);
 8002aec:	f107 020b 	add.w	r2, r7, #11
 8002af0:	f107 0320 	add.w	r3, r7, #32
 8002af4:	4611      	mov	r1, r2
 8002af6:	4618      	mov	r0, r3
 8002af8:	f7ff fb0a 	bl	8002110 <i15765_tx_app>
    }
}
 8002afc:	3740      	adds	r7, #64	@ 0x40
 8002afe:	46bd      	mov	sp, r7
 8002b00:	bd80      	pop	{r7, pc}
 8002b02:	bf00      	nop

08002b04 <SID_34_function>:


void SID_34_function(i15765_t *msg)
{
 8002b04:	b580      	push	{r7, lr}
 8002b06:	b08a      	sub	sp, #40	@ 0x28
 8002b08:	af00      	add	r7, sp, #0
 8002b0a:	6078      	str	r0, [r7, #4]
	i15765_t msg_req;
	uint8_t buf[8];
	uint8_t status_rq;
	uint8_t PositiveResponseEnable = 0;
 8002b0c:	2300      	movs	r3, #0
 8002b0e:	f887 3027 	strb.w	r3, [r7, #39]	@ 0x27

	msg_req.buf = buf;
 8002b12:	f107 030c 	add.w	r3, r7, #12
 8002b16:	61bb      	str	r3, [r7, #24]

	if(msg->buf_len!=11)
 8002b18:	687b      	ldr	r3, [r7, #4]
 8002b1a:	891b      	ldrh	r3, [r3, #8]
 8002b1c:	2b0b      	cmp	r3, #11
 8002b1e:	d007      	beq.n	8002b30 <SID_34_function+0x2c>
	{
		NegativeResponse(msg->buf[0],0x13);
 8002b20:	687b      	ldr	r3, [r7, #4]
 8002b22:	685b      	ldr	r3, [r3, #4]
 8002b24:	781b      	ldrb	r3, [r3, #0]
 8002b26:	2113      	movs	r1, #19
 8002b28:	4618      	mov	r0, r3
 8002b2a:	f7ff fd03 	bl	8002534 <NegativeResponse>
		return;
 8002b2e:	e0ae      	b.n	8002c8e <SID_34_function+0x18a>
	}

	//3
	if(load_sequence_state != 0x01)
 8002b30:	4b58      	ldr	r3, [pc, #352]	@ (8002c94 <SID_34_function+0x190>)
 8002b32:	781b      	ldrb	r3, [r3, #0]
 8002b34:	2b01      	cmp	r3, #1
 8002b36:	d007      	beq.n	8002b48 <SID_34_function+0x44>
	{
		NegativeResponse(msg->buf[0],0x24);	//(24)
 8002b38:	687b      	ldr	r3, [r7, #4]
 8002b3a:	685b      	ldr	r3, [r3, #4]
 8002b3c:	781b      	ldrb	r3, [r3, #0]
 8002b3e:	2124      	movs	r1, #36	@ 0x24
 8002b40:	4618      	mov	r0, r3
 8002b42:	f7ff fcf7 	bl	8002534 <NegativeResponse>
		return;
 8002b46:	e0a2      	b.n	8002c8e <SID_34_function+0x18a>
	}

	DataFormatIdentifier = msg->buf[1];
 8002b48:	687b      	ldr	r3, [r7, #4]
 8002b4a:	685b      	ldr	r3, [r3, #4]
 8002b4c:	785a      	ldrb	r2, [r3, #1]
 8002b4e:	4b52      	ldr	r3, [pc, #328]	@ (8002c98 <SID_34_function+0x194>)
 8002b50:	701a      	strb	r2, [r3, #0]
	addressAndLengthFormatIdentifier = msg->buf[2];//0x44
 8002b52:	687b      	ldr	r3, [r7, #4]
 8002b54:	685b      	ldr	r3, [r3, #4]
 8002b56:	789a      	ldrb	r2, [r3, #2]
 8002b58:	4b50      	ldr	r3, [pc, #320]	@ (8002c9c <SID_34_function+0x198>)
 8002b5a:	701a      	strb	r2, [r3, #0]
	//Flashַ
	load_MemoryAddress = (uint32_t)((uint32_t)msg->buf[3]<<24)|((uint32_t)msg->buf[4]<<16)|((uint32_t)msg->buf[5]<<8)|msg->buf[6];
 8002b5c:	687b      	ldr	r3, [r7, #4]
 8002b5e:	685b      	ldr	r3, [r3, #4]
 8002b60:	3303      	adds	r3, #3
 8002b62:	781b      	ldrb	r3, [r3, #0]
 8002b64:	061a      	lsls	r2, r3, #24
 8002b66:	687b      	ldr	r3, [r7, #4]
 8002b68:	685b      	ldr	r3, [r3, #4]
 8002b6a:	3304      	adds	r3, #4
 8002b6c:	781b      	ldrb	r3, [r3, #0]
 8002b6e:	041b      	lsls	r3, r3, #16
 8002b70:	431a      	orrs	r2, r3
 8002b72:	687b      	ldr	r3, [r7, #4]
 8002b74:	685b      	ldr	r3, [r3, #4]
 8002b76:	3305      	adds	r3, #5
 8002b78:	781b      	ldrb	r3, [r3, #0]
 8002b7a:	021b      	lsls	r3, r3, #8
 8002b7c:	4313      	orrs	r3, r2
 8002b7e:	687a      	ldr	r2, [r7, #4]
 8002b80:	6852      	ldr	r2, [r2, #4]
 8002b82:	3206      	adds	r2, #6
 8002b84:	7812      	ldrb	r2, [r2, #0]
 8002b86:	4313      	orrs	r3, r2
 8002b88:	4a45      	ldr	r2, [pc, #276]	@ (8002ca0 <SID_34_function+0x19c>)
 8002b8a:	6013      	str	r3, [r2, #0]
	load_MemorySize = (uint32_t)((uint32_t)msg->buf[7]<<24)|((uint32_t)msg->buf[8]<<16)|((uint32_t)msg->buf[9]<<8)|msg->buf[10];
 8002b8c:	687b      	ldr	r3, [r7, #4]
 8002b8e:	685b      	ldr	r3, [r3, #4]
 8002b90:	3307      	adds	r3, #7
 8002b92:	781b      	ldrb	r3, [r3, #0]
 8002b94:	061a      	lsls	r2, r3, #24
 8002b96:	687b      	ldr	r3, [r7, #4]
 8002b98:	685b      	ldr	r3, [r3, #4]
 8002b9a:	3308      	adds	r3, #8
 8002b9c:	781b      	ldrb	r3, [r3, #0]
 8002b9e:	041b      	lsls	r3, r3, #16
 8002ba0:	431a      	orrs	r2, r3
 8002ba2:	687b      	ldr	r3, [r7, #4]
 8002ba4:	685b      	ldr	r3, [r3, #4]
 8002ba6:	3309      	adds	r3, #9
 8002ba8:	781b      	ldrb	r3, [r3, #0]
 8002baa:	021b      	lsls	r3, r3, #8
 8002bac:	4313      	orrs	r3, r2
 8002bae:	687a      	ldr	r2, [r7, #4]
 8002bb0:	6852      	ldr	r2, [r2, #4]
 8002bb2:	320a      	adds	r2, #10
 8002bb4:	7812      	ldrb	r2, [r2, #0]
 8002bb6:	4313      	orrs	r3, r2
 8002bb8:	4a3a      	ldr	r2, [pc, #232]	@ (8002ca4 <SID_34_function+0x1a0>)
 8002bba:	6013      	str	r3, [r2, #0]

	if(load_MemorySize%MaxNumberOfBlockLength == 0)
 8002bbc:	4b39      	ldr	r3, [pc, #228]	@ (8002ca4 <SID_34_function+0x1a0>)
 8002bbe:	681b      	ldr	r3, [r3, #0]
 8002bc0:	2280      	movs	r2, #128	@ 0x80
 8002bc2:	fbb3 f1f2 	udiv	r1, r3, r2
 8002bc6:	fb01 f202 	mul.w	r2, r1, r2
 8002bca:	1a9b      	subs	r3, r3, r2
 8002bcc:	2b00      	cmp	r3, #0
 8002bce:	d107      	bne.n	8002be0 <SID_34_function+0xdc>
	{
		load_BlockNum = load_MemorySize/MaxNumberOfBlockLength;
 8002bd0:	4b34      	ldr	r3, [pc, #208]	@ (8002ca4 <SID_34_function+0x1a0>)
 8002bd2:	681b      	ldr	r3, [r3, #0]
 8002bd4:	2280      	movs	r2, #128	@ 0x80
 8002bd6:	fbb3 f3f2 	udiv	r3, r3, r2
 8002bda:	4a33      	ldr	r2, [pc, #204]	@ (8002ca8 <SID_34_function+0x1a4>)
 8002bdc:	6013      	str	r3, [r2, #0]
 8002bde:	e007      	b.n	8002bf0 <SID_34_function+0xec>
	}
	else
	{
		load_BlockNum = load_MemorySize/MaxNumberOfBlockLength + 1;
 8002be0:	4b30      	ldr	r3, [pc, #192]	@ (8002ca4 <SID_34_function+0x1a0>)
 8002be2:	681b      	ldr	r3, [r3, #0]
 8002be4:	2280      	movs	r2, #128	@ 0x80
 8002be6:	fbb3 f3f2 	udiv	r3, r3, r2
 8002bea:	3301      	adds	r3, #1
 8002bec:	4a2e      	ldr	r2, [pc, #184]	@ (8002ca8 <SID_34_function+0x1a4>)
 8002bee:	6013      	str	r3, [r2, #0]
	load_MemoryAddress_next = load_MemoryAddress + load_MemorySize;
	//////////////////////////////////////////////////////////////////////////////////////////////////////////////

#endif

	if((load_MemoryAddress == APP1_ADDRESS)&& load_MemorySize <= (APP2_ADDRESS - APP1_ADDRESS))
 8002bf0:	4b2b      	ldr	r3, [pc, #172]	@ (8002ca0 <SID_34_function+0x19c>)
 8002bf2:	681b      	ldr	r3, [r3, #0]
 8002bf4:	4a2d      	ldr	r2, [pc, #180]	@ (8002cac <SID_34_function+0x1a8>)
 8002bf6:	4293      	cmp	r3, r2
 8002bf8:	d139      	bne.n	8002c6e <SID_34_function+0x16a>
 8002bfa:	4b2a      	ldr	r3, [pc, #168]	@ (8002ca4 <SID_34_function+0x1a0>)
 8002bfc:	681b      	ldr	r3, [r3, #0]
 8002bfe:	f5b3 2fa8 	cmp.w	r3, #344064	@ 0x54000
 8002c02:	d834      	bhi.n	8002c6e <SID_34_function+0x16a>
	{
		load_MemoryAddress = APP2_ADDRESS;//虽是APP1的固件地址，但写在备份区APP2地址
 8002c04:	4b26      	ldr	r3, [pc, #152]	@ (8002ca0 <SID_34_function+0x19c>)
 8002c06:	4a2a      	ldr	r2, [pc, #168]	@ (8002cb0 <SID_34_function+0x1ac>)
 8002c08:	601a      	str	r2, [r3, #0]
		PositiveResponseEnable = 1;
 8002c0a:	2301      	movs	r3, #1
 8002c0c:	f887 3027 	strb.w	r3, [r7, #39]	@ 0x27
		buf[0] = msg->buf[0]+0x40;	// PositiveResponseServiceIdentifier
 8002c10:	687b      	ldr	r3, [r7, #4]
 8002c12:	685b      	ldr	r3, [r3, #4]
 8002c14:	781b      	ldrb	r3, [r3, #0]
 8002c16:	3340      	adds	r3, #64	@ 0x40
 8002c18:	b2db      	uxtb	r3, r3
 8002c1a:	733b      	strb	r3, [r7, #12]
		buf[1] = msg->buf[1];		// LengthFormatIdentifier
 8002c1c:	687b      	ldr	r3, [r7, #4]
 8002c1e:	685b      	ldr	r3, [r3, #4]
 8002c20:	785b      	ldrb	r3, [r3, #1]
 8002c22:	737b      	strb	r3, [r7, #13]

		if(MaxNumberOfBlockLength > 0xFF)
 8002c24:	2380      	movs	r3, #128	@ 0x80
 8002c26:	2bff      	cmp	r3, #255	@ 0xff
 8002c28:	d90a      	bls.n	8002c40 <SID_34_function+0x13c>
		{
			//MaxNumberOfBlockLength
			buf[2] = (uint8)((MaxNumberOfBlockLength>>8)&0xFF);
 8002c2a:	2380      	movs	r3, #128	@ 0x80
 8002c2c:	0a1b      	lsrs	r3, r3, #8
 8002c2e:	b29b      	uxth	r3, r3
 8002c30:	b2db      	uxtb	r3, r3
 8002c32:	73bb      	strb	r3, [r7, #14]
			buf[3] = (uint8)(MaxNumberOfBlockLength&0xFF);
 8002c34:	2380      	movs	r3, #128	@ 0x80
 8002c36:	b2db      	uxtb	r3, r3
 8002c38:	73fb      	strb	r3, [r7, #15]
			msg_req.buf_len = 4;
 8002c3a:	2304      	movs	r3, #4
 8002c3c:	83bb      	strh	r3, [r7, #28]
 8002c3e:	e004      	b.n	8002c4a <SID_34_function+0x146>
		}
		else
		{
			//MaxNumberOfBlockLength
			buf[2] = (uint8) MaxNumberOfBlockLength;
 8002c40:	2380      	movs	r3, #128	@ 0x80
 8002c42:	b2db      	uxtb	r3, r3
 8002c44:	73bb      	strb	r3, [r7, #14]
			msg_req.buf_len = 3;
 8002c46:	2303      	movs	r3, #3
 8002c48:	83bb      	strh	r3, [r7, #28]
		}

		load_sequence_state = 0x02;
 8002c4a:	4b12      	ldr	r3, [pc, #72]	@ (8002c94 <SID_34_function+0x190>)
 8002c4c:	2202      	movs	r2, #2
 8002c4e:	701a      	strb	r2, [r3, #0]
		BlockSequenceCounter_pre = 0;
 8002c50:	4b18      	ldr	r3, [pc, #96]	@ (8002cb4 <SID_34_function+0x1b0>)
 8002c52:	2200      	movs	r2, #0
 8002c54:	801a      	strh	r2, [r3, #0]
		crc32val = 0xFFFFFFFF;
 8002c56:	4b18      	ldr	r3, [pc, #96]	@ (8002cb8 <SID_34_function+0x1b4>)
 8002c58:	f04f 32ff 	mov.w	r2, #4294967295
 8002c5c:	601a      	str	r2, [r3, #0]
		load_BlockCount = 0;
 8002c5e:	4b17      	ldr	r3, [pc, #92]	@ (8002cbc <SID_34_function+0x1b8>)
 8002c60:	2200      	movs	r2, #0
 8002c62:	601a      	str	r2, [r3, #0]
		NegativeResponse(msg->buf[0],31);//
		return;
	}


	if(PositiveResponseEnable==1)
 8002c64:	f897 3027 	ldrb.w	r3, [r7, #39]	@ 0x27
 8002c68:	2b01      	cmp	r3, #1
 8002c6a:	d008      	beq.n	8002c7e <SID_34_function+0x17a>
 8002c6c:	e00f      	b.n	8002c8e <SID_34_function+0x18a>
		NegativeResponse(msg->buf[0],31);//
 8002c6e:	687b      	ldr	r3, [r7, #4]
 8002c70:	685b      	ldr	r3, [r3, #4]
 8002c72:	781b      	ldrb	r3, [r3, #0]
 8002c74:	211f      	movs	r1, #31
 8002c76:	4618      	mov	r0, r3
 8002c78:	f7ff fc5c 	bl	8002534 <NegativeResponse>
		return;
 8002c7c:	e007      	b.n	8002c8e <SID_34_function+0x18a>
	{
		/* transmit message */
		i15765_tx_app(&msg_req, &status_rq);
 8002c7e:	f107 020b 	add.w	r2, r7, #11
 8002c82:	f107 0314 	add.w	r3, r7, #20
 8002c86:	4611      	mov	r1, r2
 8002c88:	4618      	mov	r0, r3
 8002c8a:	f7ff fa41 	bl	8002110 <i15765_tx_app>
	}
}
 8002c8e:	3728      	adds	r7, #40	@ 0x28
 8002c90:	46bd      	mov	sp, r7
 8002c92:	bd80      	pop	{r7, pc}
 8002c94:	20001ea8 	.word	0x20001ea8
 8002c98:	20001e8e 	.word	0x20001e8e
 8002c9c:	20001e8f 	.word	0x20001e8f
 8002ca0:	20001e90 	.word	0x20001e90
 8002ca4:	20001e94 	.word	0x20001e94
 8002ca8:	20001e98 	.word	0x20001e98
 8002cac:	0800c000 	.word	0x0800c000
 8002cb0:	08060000 	.word	0x08060000
 8002cb4:	20001eac 	.word	0x20001eac
 8002cb8:	20000004 	.word	0x20000004
 8002cbc:	20001e9c 	.word	0x20001e9c

08002cc0 <SID_36_function>:

void SID_36_function(i15765_t *msg)
{
 8002cc0:	b580      	push	{r7, lr}
 8002cc2:	f5ad 5d81 	sub.w	sp, sp, #4128	@ 0x1020
 8002cc6:	b084      	sub	sp, #16
 8002cc8:	af00      	add	r7, sp, #0
 8002cca:	f107 0330 	add.w	r3, r7, #48	@ 0x30
 8002cce:	f843 0c2c 	str.w	r0, [r3, #-44]
	i15765_t msg_req;
	uint8_t buf[8];
	uint8_t status_rq;
	uint8_t PositiveResponseEnable = 0;
 8002cd2:	2300      	movs	r3, #0
 8002cd4:	f507 5281 	add.w	r2, r7, #4128	@ 0x1020
 8002cd8:	f102 020d 	add.w	r2, r2, #13
 8002cdc:	7013      	strb	r3, [r2, #0]

	uint16_t i = 0;
 8002cde:	2300      	movs	r3, #0
 8002ce0:	f507 5281 	add.w	r2, r7, #4128	@ 0x1020
 8002ce4:	f102 020e 	add.w	r2, r2, #14
 8002ce8:	8013      	strh	r3, [r2, #0]

	int oReturnCheck;

	uint8_t TransferRequestParameterRecord[4096];

	msg_req.buf = buf;
 8002cea:	f507 5380 	add.w	r3, r7, #4096	@ 0x1000
 8002cee:	f103 0310 	add.w	r3, r3, #16
 8002cf2:	f507 5280 	add.w	r2, r7, #4096	@ 0x1000
 8002cf6:	f102 021c 	add.w	r2, r2, #28
 8002cfa:	6013      	str	r3, [r2, #0]

	if(load_sequence_state != 0x02)
 8002cfc:	4b99      	ldr	r3, [pc, #612]	@ (8002f64 <SID_36_function+0x2a4>)
 8002cfe:	781b      	ldrb	r3, [r3, #0]
 8002d00:	2b02      	cmp	r3, #2
 8002d02:	d00a      	beq.n	8002d1a <SID_36_function+0x5a>
	{
		NegativeResponse(msg->buf[0],0x24);
 8002d04:	f107 0330 	add.w	r3, r7, #48	@ 0x30
 8002d08:	f853 3c2c 	ldr.w	r3, [r3, #-44]
 8002d0c:	685b      	ldr	r3, [r3, #4]
 8002d0e:	781b      	ldrb	r3, [r3, #0]
 8002d10:	2124      	movs	r1, #36	@ 0x24
 8002d12:	4618      	mov	r0, r3
 8002d14:	f7ff fc0e 	bl	8002534 <NegativeResponse>
		return;
 8002d18:	e11f      	b.n	8002f5a <SID_36_function+0x29a>
	}

	BlockSequenceCounter = msg->buf[1];
 8002d1a:	f107 0330 	add.w	r3, r7, #48	@ 0x30
 8002d1e:	f853 3c2c 	ldr.w	r3, [r3, #-44]
 8002d22:	685b      	ldr	r3, [r3, #4]
 8002d24:	3301      	adds	r3, #1
 8002d26:	781b      	ldrb	r3, [r3, #0]
 8002d28:	461a      	mov	r2, r3
 8002d2a:	4b8f      	ldr	r3, [pc, #572]	@ (8002f68 <SID_36_function+0x2a8>)
 8002d2c:	801a      	strh	r2, [r3, #0]
	if(BlockSequenceCounter == 0x00)
 8002d2e:	4b8e      	ldr	r3, [pc, #568]	@ (8002f68 <SID_36_function+0x2a8>)
 8002d30:	881b      	ldrh	r3, [r3, #0]
 8002d32:	2b00      	cmp	r3, #0
 8002d34:	d10e      	bne.n	8002d54 <SID_36_function+0x94>
	{
		if(BlockSequenceCounter_pre != 0xFF)
 8002d36:	4b8d      	ldr	r3, [pc, #564]	@ (8002f6c <SID_36_function+0x2ac>)
 8002d38:	881b      	ldrh	r3, [r3, #0]
 8002d3a:	2bff      	cmp	r3, #255	@ 0xff
 8002d3c:	d01d      	beq.n	8002d7a <SID_36_function+0xba>
		{
			NegativeResponse(msg->buf[0],0x73);//
 8002d3e:	f107 0330 	add.w	r3, r7, #48	@ 0x30
 8002d42:	f853 3c2c 	ldr.w	r3, [r3, #-44]
 8002d46:	685b      	ldr	r3, [r3, #4]
 8002d48:	781b      	ldrb	r3, [r3, #0]
 8002d4a:	2173      	movs	r1, #115	@ 0x73
 8002d4c:	4618      	mov	r0, r3
 8002d4e:	f7ff fbf1 	bl	8002534 <NegativeResponse>
			return;
 8002d52:	e102      	b.n	8002f5a <SID_36_function+0x29a>
		}
	}
	else if(BlockSequenceCounter != (BlockSequenceCounter_pre+1))
 8002d54:	4b84      	ldr	r3, [pc, #528]	@ (8002f68 <SID_36_function+0x2a8>)
 8002d56:	881b      	ldrh	r3, [r3, #0]
 8002d58:	461a      	mov	r2, r3
 8002d5a:	4b84      	ldr	r3, [pc, #528]	@ (8002f6c <SID_36_function+0x2ac>)
 8002d5c:	881b      	ldrh	r3, [r3, #0]
 8002d5e:	3301      	adds	r3, #1
 8002d60:	429a      	cmp	r2, r3
 8002d62:	d00a      	beq.n	8002d7a <SID_36_function+0xba>
	{
		NegativeResponse(msg->buf[0],0x73);//
 8002d64:	f107 0330 	add.w	r3, r7, #48	@ 0x30
 8002d68:	f853 3c2c 	ldr.w	r3, [r3, #-44]
 8002d6c:	685b      	ldr	r3, [r3, #4]
 8002d6e:	781b      	ldrb	r3, [r3, #0]
 8002d70:	2173      	movs	r1, #115	@ 0x73
 8002d72:	4618      	mov	r0, r3
 8002d74:	f7ff fbde 	bl	8002534 <NegativeResponse>
		return;
 8002d78:	e0ef      	b.n	8002f5a <SID_36_function+0x29a>
	}
	BlockSequenceCounter_pre = BlockSequenceCounter;
 8002d7a:	4b7b      	ldr	r3, [pc, #492]	@ (8002f68 <SID_36_function+0x2a8>)
 8002d7c:	881a      	ldrh	r2, [r3, #0]
 8002d7e:	4b7b      	ldr	r3, [pc, #492]	@ (8002f6c <SID_36_function+0x2ac>)
 8002d80:	801a      	strh	r2, [r3, #0]
	//////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////

	for(i=0; i < msg->buf_len-2;i++)
 8002d82:	2300      	movs	r3, #0
 8002d84:	f507 5281 	add.w	r2, r7, #4128	@ 0x1020
 8002d88:	f102 020e 	add.w	r2, r2, #14
 8002d8c:	8013      	strh	r3, [r2, #0]
 8002d8e:	e021      	b.n	8002dd4 <SID_36_function+0x114>
	{
		TransferRequestParameterRecord[i] = msg->buf[2+i];
 8002d90:	f107 0330 	add.w	r3, r7, #48	@ 0x30
 8002d94:	f853 3c2c 	ldr.w	r3, [r3, #-44]
 8002d98:	685b      	ldr	r3, [r3, #4]
 8002d9a:	f507 5281 	add.w	r2, r7, #4128	@ 0x1020
 8002d9e:	f102 020e 	add.w	r2, r2, #14
 8002da2:	8812      	ldrh	r2, [r2, #0]
 8002da4:	3202      	adds	r2, #2
 8002da6:	441a      	add	r2, r3
 8002da8:	f507 5381 	add.w	r3, r7, #4128	@ 0x1020
 8002dac:	f103 030e 	add.w	r3, r3, #14
 8002db0:	881b      	ldrh	r3, [r3, #0]
 8002db2:	7812      	ldrb	r2, [r2, #0]
 8002db4:	f107 0130 	add.w	r1, r7, #48	@ 0x30
 8002db8:	440b      	add	r3, r1
 8002dba:	f803 2c24 	strb.w	r2, [r3, #-36]
	for(i=0; i < msg->buf_len-2;i++)
 8002dbe:	f507 5381 	add.w	r3, r7, #4128	@ 0x1020
 8002dc2:	f103 030e 	add.w	r3, r3, #14
 8002dc6:	881b      	ldrh	r3, [r3, #0]
 8002dc8:	3301      	adds	r3, #1
 8002dca:	f507 5281 	add.w	r2, r7, #4128	@ 0x1020
 8002dce:	f102 020e 	add.w	r2, r2, #14
 8002dd2:	8013      	strh	r3, [r2, #0]
 8002dd4:	f507 5381 	add.w	r3, r7, #4128	@ 0x1020
 8002dd8:	f103 030e 	add.w	r3, r3, #14
 8002ddc:	881a      	ldrh	r2, [r3, #0]
 8002dde:	f107 0330 	add.w	r3, r7, #48	@ 0x30
 8002de2:	f853 3c2c 	ldr.w	r3, [r3, #-44]
 8002de6:	891b      	ldrh	r3, [r3, #8]
 8002de8:	3b02      	subs	r3, #2
 8002dea:	429a      	cmp	r2, r3
 8002dec:	dbd0      	blt.n	8002d90 <SID_36_function+0xd0>
	}
	crc32val = crc32(crc32val, TransferRequestParameterRecord, msg->buf_len-2);
 8002dee:	4b60      	ldr	r3, [pc, #384]	@ (8002f70 <SID_36_function+0x2b0>)
 8002df0:	6818      	ldr	r0, [r3, #0]
 8002df2:	f107 0330 	add.w	r3, r7, #48	@ 0x30
 8002df6:	f853 3c2c 	ldr.w	r3, [r3, #-44]
 8002dfa:	891b      	ldrh	r3, [r3, #8]
 8002dfc:	3b02      	subs	r3, #2
 8002dfe:	461a      	mov	r2, r3
 8002e00:	f107 0310 	add.w	r3, r7, #16
 8002e04:	3b04      	subs	r3, #4
 8002e06:	4619      	mov	r1, r3
 8002e08:	f7fe fb28 	bl	800145c <crc32>
 8002e0c:	4603      	mov	r3, r0
 8002e0e:	4a58      	ldr	r2, [pc, #352]	@ (8002f70 <SID_36_function+0x2b0>)
 8002e10:	6013      	str	r3, [r2, #0]
	oReturnCheck = flash_write_page((load_MemoryAddress + load_BlockCount*MaxNumberOfBlockLength), TransferRequestParameterRecord, msg->buf_len-2, false);
 8002e12:	2380      	movs	r3, #128	@ 0x80
 8002e14:	461a      	mov	r2, r3
 8002e16:	4b57      	ldr	r3, [pc, #348]	@ (8002f74 <SID_36_function+0x2b4>)
 8002e18:	681b      	ldr	r3, [r3, #0]
 8002e1a:	fb03 f202 	mul.w	r2, r3, r2
 8002e1e:	4b56      	ldr	r3, [pc, #344]	@ (8002f78 <SID_36_function+0x2b8>)
 8002e20:	681b      	ldr	r3, [r3, #0]
 8002e22:	18d0      	adds	r0, r2, r3
 8002e24:	f107 0330 	add.w	r3, r7, #48	@ 0x30
 8002e28:	f853 3c2c 	ldr.w	r3, [r3, #-44]
 8002e2c:	891b      	ldrh	r3, [r3, #8]
 8002e2e:	3b02      	subs	r3, #2
 8002e30:	461a      	mov	r2, r3
 8002e32:	f107 0110 	add.w	r1, r7, #16
 8002e36:	3904      	subs	r1, #4
 8002e38:	2300      	movs	r3, #0
 8002e3a:	f7fd ff45 	bl	8000cc8 <flash_write_page>
 8002e3e:	f507 5381 	add.w	r3, r7, #4128	@ 0x1020
 8002e42:	f103 0308 	add.w	r3, r3, #8
 8002e46:	6018      	str	r0, [r3, #0]

	if(!oReturnCheck)
 8002e48:	f507 5381 	add.w	r3, r7, #4128	@ 0x1020
 8002e4c:	f103 0308 	add.w	r3, r3, #8
 8002e50:	681b      	ldr	r3, [r3, #0]
 8002e52:	2b00      	cmp	r3, #0
 8002e54:	d163      	bne.n	8002f1e <SID_36_function+0x25e>
	{
		WriteFlashAlreadySize = WriteFlashAlreadySize + msg->buf_len-2;
 8002e56:	f107 0330 	add.w	r3, r7, #48	@ 0x30
 8002e5a:	f853 3c2c 	ldr.w	r3, [r3, #-44]
 8002e5e:	891b      	ldrh	r3, [r3, #8]
 8002e60:	461a      	mov	r2, r3
 8002e62:	4b46      	ldr	r3, [pc, #280]	@ (8002f7c <SID_36_function+0x2bc>)
 8002e64:	681b      	ldr	r3, [r3, #0]
 8002e66:	4413      	add	r3, r2
 8002e68:	3b02      	subs	r3, #2
 8002e6a:	4a44      	ldr	r2, [pc, #272]	@ (8002f7c <SID_36_function+0x2bc>)
 8002e6c:	6013      	str	r3, [r2, #0]
		//
		PositiveResponseEnable = 1;
 8002e6e:	2301      	movs	r3, #1
 8002e70:	f507 5281 	add.w	r2, r7, #4128	@ 0x1020
 8002e74:	f102 020d 	add.w	r2, r2, #13
 8002e78:	7013      	strb	r3, [r2, #0]
		buf[0] = msg->buf[0]+0x40;	// PositiveResponseServiceIdentifier
 8002e7a:	f107 0330 	add.w	r3, r7, #48	@ 0x30
 8002e7e:	f853 3c2c 	ldr.w	r3, [r3, #-44]
 8002e82:	685b      	ldr	r3, [r3, #4]
 8002e84:	781b      	ldrb	r3, [r3, #0]
 8002e86:	3340      	adds	r3, #64	@ 0x40
 8002e88:	b2db      	uxtb	r3, r3
 8002e8a:	f507 5280 	add.w	r2, r7, #4096	@ 0x1000
 8002e8e:	f102 0210 	add.w	r2, r2, #16
 8002e92:	7013      	strb	r3, [r2, #0]
		buf[1] = msg->buf[1];		// BlockSequenceCounter
 8002e94:	f107 0330 	add.w	r3, r7, #48	@ 0x30
 8002e98:	f853 3c2c 	ldr.w	r3, [r3, #-44]
 8002e9c:	685b      	ldr	r3, [r3, #4]
 8002e9e:	785b      	ldrb	r3, [r3, #1]
 8002ea0:	f507 5280 	add.w	r2, r7, #4096	@ 0x1000
 8002ea4:	f102 0211 	add.w	r2, r2, #17
 8002ea8:	7013      	strb	r3, [r2, #0]
		buf[2] = (uint8)((crc32val>>24)&0xFF);
 8002eaa:	4b31      	ldr	r3, [pc, #196]	@ (8002f70 <SID_36_function+0x2b0>)
 8002eac:	681b      	ldr	r3, [r3, #0]
 8002eae:	0e1b      	lsrs	r3, r3, #24
 8002eb0:	b2db      	uxtb	r3, r3
 8002eb2:	f507 5280 	add.w	r2, r7, #4096	@ 0x1000
 8002eb6:	f102 0212 	add.w	r2, r2, #18
 8002eba:	7013      	strb	r3, [r2, #0]
		buf[3] = (uint8)((crc32val>>16)&0xFF);
 8002ebc:	4b2c      	ldr	r3, [pc, #176]	@ (8002f70 <SID_36_function+0x2b0>)
 8002ebe:	681b      	ldr	r3, [r3, #0]
 8002ec0:	0c1b      	lsrs	r3, r3, #16
 8002ec2:	b2db      	uxtb	r3, r3
 8002ec4:	f507 5280 	add.w	r2, r7, #4096	@ 0x1000
 8002ec8:	f102 0213 	add.w	r2, r2, #19
 8002ecc:	7013      	strb	r3, [r2, #0]
		buf[4] = (uint8)((crc32val>>8)&0xFF);
 8002ece:	4b28      	ldr	r3, [pc, #160]	@ (8002f70 <SID_36_function+0x2b0>)
 8002ed0:	681b      	ldr	r3, [r3, #0]
 8002ed2:	0a1b      	lsrs	r3, r3, #8
 8002ed4:	b2db      	uxtb	r3, r3
 8002ed6:	f507 5280 	add.w	r2, r7, #4096	@ 0x1000
 8002eda:	f102 0214 	add.w	r2, r2, #20
 8002ede:	7013      	strb	r3, [r2, #0]
		buf[5] = (uint8)((crc32val>>0)&0xFF);
 8002ee0:	4b23      	ldr	r3, [pc, #140]	@ (8002f70 <SID_36_function+0x2b0>)
 8002ee2:	681b      	ldr	r3, [r3, #0]
 8002ee4:	b2db      	uxtb	r3, r3
 8002ee6:	f507 5280 	add.w	r2, r7, #4096	@ 0x1000
 8002eea:	f102 0215 	add.w	r2, r2, #21
 8002eee:	7013      	strb	r3, [r2, #0]
		msg_req.buf_len = 6;
 8002ef0:	2306      	movs	r3, #6
 8002ef2:	f507 5281 	add.w	r2, r7, #4128	@ 0x1020
 8002ef6:	8013      	strh	r3, [r2, #0]
		/////////////////////////////////////////////////////////////////

		load_BlockCount++;
 8002ef8:	4b1e      	ldr	r3, [pc, #120]	@ (8002f74 <SID_36_function+0x2b4>)
 8002efa:	681b      	ldr	r3, [r3, #0]
 8002efc:	3301      	adds	r3, #1
 8002efe:	4a1d      	ldr	r2, [pc, #116]	@ (8002f74 <SID_36_function+0x2b4>)
 8002f00:	6013      	str	r3, [r2, #0]
		if(load_BlockCount==load_BlockNum)
 8002f02:	4b1c      	ldr	r3, [pc, #112]	@ (8002f74 <SID_36_function+0x2b4>)
 8002f04:	681a      	ldr	r2, [r3, #0]
 8002f06:	4b1e      	ldr	r3, [pc, #120]	@ (8002f80 <SID_36_function+0x2c0>)
 8002f08:	681b      	ldr	r3, [r3, #0]
 8002f0a:	429a      	cmp	r2, r3
 8002f0c:	d103      	bne.n	8002f16 <SID_36_function+0x256>
		{
			load_sequence_state = 0x03;
 8002f0e:	4b15      	ldr	r3, [pc, #84]	@ (8002f64 <SID_36_function+0x2a4>)
 8002f10:	2203      	movs	r2, #3
 8002f12:	701a      	strb	r2, [r3, #0]
 8002f14:	e00e      	b.n	8002f34 <SID_36_function+0x274>
		}
		else
		{
			load_sequence_state = 0x02;
 8002f16:	4b13      	ldr	r3, [pc, #76]	@ (8002f64 <SID_36_function+0x2a4>)
 8002f18:	2202      	movs	r2, #2
 8002f1a:	701a      	strb	r2, [r3, #0]
 8002f1c:	e00a      	b.n	8002f34 <SID_36_function+0x274>
		}
	}
	else
	{
		// Indicate that the flash programming failed.
		NegativeResponse(msg->buf[0],0x70);//
 8002f1e:	f107 0330 	add.w	r3, r7, #48	@ 0x30
 8002f22:	f853 3c2c 	ldr.w	r3, [r3, #-44]
 8002f26:	685b      	ldr	r3, [r3, #4]
 8002f28:	781b      	ldrb	r3, [r3, #0]
 8002f2a:	2170      	movs	r1, #112	@ 0x70
 8002f2c:	4618      	mov	r0, r3
 8002f2e:	f7ff fb01 	bl	8002534 <NegativeResponse>
		return;
 8002f32:	e012      	b.n	8002f5a <SID_36_function+0x29a>
	}
	////////////////////////////////////////////////////////////////////

	if(PositiveResponseEnable==1)
 8002f34:	f507 5381 	add.w	r3, r7, #4128	@ 0x1020
 8002f38:	f103 030d 	add.w	r3, r3, #13
 8002f3c:	781b      	ldrb	r3, [r3, #0]
 8002f3e:	2b01      	cmp	r3, #1
 8002f40:	d10b      	bne.n	8002f5a <SID_36_function+0x29a>
	{
		/* transmit message */
		i15765_tx_app(&msg_req, &status_rq);
 8002f42:	f507 5280 	add.w	r2, r7, #4096	@ 0x1000
 8002f46:	f102 020f 	add.w	r2, r2, #15
 8002f4a:	f507 5380 	add.w	r3, r7, #4096	@ 0x1000
 8002f4e:	f103 0318 	add.w	r3, r3, #24
 8002f52:	4611      	mov	r1, r2
 8002f54:	4618      	mov	r0, r3
 8002f56:	f7ff f8db 	bl	8002110 <i15765_tx_app>
	}
}
 8002f5a:	f507 5781 	add.w	r7, r7, #4128	@ 0x1020
 8002f5e:	3710      	adds	r7, #16
 8002f60:	46bd      	mov	sp, r7
 8002f62:	bd80      	pop	{r7, pc}
 8002f64:	20001ea8 	.word	0x20001ea8
 8002f68:	20001eaa 	.word	0x20001eaa
 8002f6c:	20001eac 	.word	0x20001eac
 8002f70:	20000004 	.word	0x20000004
 8002f74:	20001e9c 	.word	0x20001e9c
 8002f78:	20001e90 	.word	0x20001e90
 8002f7c:	20001eb4 	.word	0x20001eb4
 8002f80:	20001e98 	.word	0x20001e98

08002f84 <SID_37_function>:

void SID_37_function(i15765_t *msg)
{
 8002f84:	b580      	push	{r7, lr}
 8002f86:	b08a      	sub	sp, #40	@ 0x28
 8002f88:	af00      	add	r7, sp, #0
 8002f8a:	6078      	str	r0, [r7, #4]
	i15765_t msg_req;
	uint8_t buf[8];
	uint8_t status_rq;

	/* basic stuff */
	msg_req.buf = buf;
 8002f8c:	f107 0310 	add.w	r3, r7, #16
 8002f90:	61fb      	str	r3, [r7, #28]
	msg_req.pri = 6;
 8002f92:	2306      	movs	r3, #6
 8002f94:	76bb      	strb	r3, [r7, #26]
	msg_req.ta = 0x0C;
 8002f96:	230c      	movs	r3, #12
 8002f98:	767b      	strb	r3, [r7, #25]

	if(msg->buf_len != 1)
 8002f9a:	687b      	ldr	r3, [r7, #4]
 8002f9c:	891b      	ldrh	r3, [r3, #8]
 8002f9e:	2b01      	cmp	r3, #1
 8002fa0:	d007      	beq.n	8002fb2 <SID_37_function+0x2e>
	{
		NegativeResponse(msg->buf[0],0x13);	//
 8002fa2:	687b      	ldr	r3, [r7, #4]
 8002fa4:	685b      	ldr	r3, [r3, #4]
 8002fa6:	781b      	ldrb	r3, [r3, #0]
 8002fa8:	2113      	movs	r1, #19
 8002faa:	4618      	mov	r0, r3
 8002fac:	f7ff fac2 	bl	8002534 <NegativeResponse>
		return;
 8002fb0:	e024      	b.n	8002ffc <SID_37_function+0x78>
	}

//	if(load_sequence_state != 0x02)
	if(load_sequence_state != 0x03)
 8002fb2:	4b14      	ldr	r3, [pc, #80]	@ (8003004 <SID_37_function+0x80>)
 8002fb4:	781b      	ldrb	r3, [r3, #0]
 8002fb6:	2b03      	cmp	r3, #3
 8002fb8:	d007      	beq.n	8002fca <SID_37_function+0x46>
	{
		NegativeResponse(msg->buf[0],0x24);	//(24)
 8002fba:	687b      	ldr	r3, [r7, #4]
 8002fbc:	685b      	ldr	r3, [r3, #4]
 8002fbe:	781b      	ldrb	r3, [r3, #0]
 8002fc0:	2124      	movs	r1, #36	@ 0x24
 8002fc2:	4618      	mov	r0, r3
 8002fc4:	f7ff fab6 	bl	8002534 <NegativeResponse>
		return;
 8002fc8:	e018      	b.n	8002ffc <SID_37_function+0x78>
	}
	else
	{
		buf[0] = msg->buf[0]+0x40;	// PositiveResponseServiceIdentifier
 8002fca:	687b      	ldr	r3, [r7, #4]
 8002fcc:	685b      	ldr	r3, [r3, #4]
 8002fce:	781b      	ldrb	r3, [r3, #0]
 8002fd0:	3340      	adds	r3, #64	@ 0x40
 8002fd2:	b2db      	uxtb	r3, r3
 8002fd4:	743b      	strb	r3, [r7, #16]

		msg_req.buf_len = 1;
 8002fd6:	2301      	movs	r3, #1
 8002fd8:	843b      	strh	r3, [r7, #32]
		/* transmit message */
		i15765_tx_app(&msg_req, &status_rq);
 8002fda:	f107 020f 	add.w	r2, r7, #15
 8002fde:	f107 0318 	add.w	r3, r7, #24
 8002fe2:	4611      	mov	r1, r2
 8002fe4:	4618      	mov	r0, r3
 8002fe6:	f7ff f893 	bl	8002110 <i15765_tx_app>

		//
		load_sequence_state = 0x00;
 8002fea:	4b06      	ldr	r3, [pc, #24]	@ (8003004 <SID_37_function+0x80>)
 8002fec:	2200      	movs	r2, #0
 8002fee:	701a      	strb	r2, [r3, #0]
		load_BlockCount = 0;
 8002ff0:	4b05      	ldr	r3, [pc, #20]	@ (8003008 <SID_37_function+0x84>)
 8002ff2:	2200      	movs	r2, #0
 8002ff4:	601a      	str	r2, [r3, #0]
		BlockSequenceCounter_pre = 0;
 8002ff6:	4b05      	ldr	r3, [pc, #20]	@ (800300c <SID_37_function+0x88>)
 8002ff8:	2200      	movs	r2, #0
 8002ffa:	801a      	strh	r2, [r3, #0]
	}
}
 8002ffc:	3728      	adds	r7, #40	@ 0x28
 8002ffe:	46bd      	mov	sp, r7
 8003000:	bd80      	pop	{r7, pc}
 8003002:	bf00      	nop
 8003004:	20001ea8 	.word	0x20001ea8
 8003008:	20001e9c 	.word	0x20001e9c
 800300c:	20001eac 	.word	0x20001eac

08003010 <HAL_Init>:
  *         need to ensure that the SysTick time base is always set to 1 millisecond
  *         to have correct HAL operation.
  * @retval HAL status
  */
HAL_StatusTypeDef HAL_Init(void)
{
 8003010:	b580      	push	{r7, lr}
 8003012:	af00      	add	r7, sp, #0
  /* Configure Flash prefetch, Instruction cache, Data cache */ 
#if (INSTRUCTION_CACHE_ENABLE != 0U)
  __HAL_FLASH_INSTRUCTION_CACHE_ENABLE();
 8003014:	4b0e      	ldr	r3, [pc, #56]	@ (8003050 <HAL_Init+0x40>)
 8003016:	681b      	ldr	r3, [r3, #0]
 8003018:	4a0d      	ldr	r2, [pc, #52]	@ (8003050 <HAL_Init+0x40>)
 800301a:	f443 7300 	orr.w	r3, r3, #512	@ 0x200
 800301e:	6013      	str	r3, [r2, #0]
#endif /* INSTRUCTION_CACHE_ENABLE */

#if (DATA_CACHE_ENABLE != 0U)
  __HAL_FLASH_DATA_CACHE_ENABLE();
 8003020:	4b0b      	ldr	r3, [pc, #44]	@ (8003050 <HAL_Init+0x40>)
 8003022:	681b      	ldr	r3, [r3, #0]
 8003024:	4a0a      	ldr	r2, [pc, #40]	@ (8003050 <HAL_Init+0x40>)
 8003026:	f443 6380 	orr.w	r3, r3, #1024	@ 0x400
 800302a:	6013      	str	r3, [r2, #0]
#endif /* DATA_CACHE_ENABLE */

#if (PREFETCH_ENABLE != 0U)
  __HAL_FLASH_PREFETCH_BUFFER_ENABLE();
 800302c:	4b08      	ldr	r3, [pc, #32]	@ (8003050 <HAL_Init+0x40>)
 800302e:	681b      	ldr	r3, [r3, #0]
 8003030:	4a07      	ldr	r2, [pc, #28]	@ (8003050 <HAL_Init+0x40>)
 8003032:	f443 7380 	orr.w	r3, r3, #256	@ 0x100
 8003036:	6013      	str	r3, [r2, #0]
#endif /* PREFETCH_ENABLE */

  /* Set Interrupt Group Priority */
  HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4);
 8003038:	2003      	movs	r0, #3
 800303a:	f001 f8bf 	bl	80041bc <HAL_NVIC_SetPriorityGrouping>

  /* Use systick as time base source and configure 1ms tick (default clock after Reset is HSI) */
  HAL_InitTick(TICK_INT_PRIORITY);
 800303e:	200f      	movs	r0, #15
 8003040:	f000 f83e 	bl	80030c0 <HAL_InitTick>

  /* Init the low level hardware */
  HAL_MspInit();
 8003044:	f7fe f884 	bl	8001150 <HAL_MspInit>

  /* Return function status */
  return HAL_OK;
 8003048:	2300      	movs	r3, #0
}
 800304a:	4618      	mov	r0, r3
 800304c:	bd80      	pop	{r7, pc}
 800304e:	bf00      	nop
 8003050:	40023c00 	.word	0x40023c00

08003054 <HAL_DeInit>:
  * @brief  This function de-Initializes common part of the HAL and stops the systick.
  *         This function is optional.   
  * @retval HAL status
  */
HAL_StatusTypeDef HAL_DeInit(void)
{
 8003054:	b580      	push	{r7, lr}
 8003056:	af00      	add	r7, sp, #0
  /* Reset of all peripherals */
  __HAL_RCC_APB1_FORCE_RESET();
 8003058:	4b11      	ldr	r3, [pc, #68]	@ (80030a0 <HAL_DeInit+0x4c>)
 800305a:	4a12      	ldr	r2, [pc, #72]	@ (80030a4 <HAL_DeInit+0x50>)
 800305c:	621a      	str	r2, [r3, #32]
  __HAL_RCC_APB1_RELEASE_RESET();
 800305e:	4b10      	ldr	r3, [pc, #64]	@ (80030a0 <HAL_DeInit+0x4c>)
 8003060:	2200      	movs	r2, #0
 8003062:	621a      	str	r2, [r3, #32]

  __HAL_RCC_APB2_FORCE_RESET();
 8003064:	4b0e      	ldr	r3, [pc, #56]	@ (80030a0 <HAL_DeInit+0x4c>)
 8003066:	4a10      	ldr	r2, [pc, #64]	@ (80030a8 <HAL_DeInit+0x54>)
 8003068:	625a      	str	r2, [r3, #36]	@ 0x24
  __HAL_RCC_APB2_RELEASE_RESET();
 800306a:	4b0d      	ldr	r3, [pc, #52]	@ (80030a0 <HAL_DeInit+0x4c>)
 800306c:	2200      	movs	r2, #0
 800306e:	625a      	str	r2, [r3, #36]	@ 0x24

  __HAL_RCC_AHB1_FORCE_RESET();
 8003070:	4b0b      	ldr	r3, [pc, #44]	@ (80030a0 <HAL_DeInit+0x4c>)
 8003072:	4a0e      	ldr	r2, [pc, #56]	@ (80030ac <HAL_DeInit+0x58>)
 8003074:	611a      	str	r2, [r3, #16]
  __HAL_RCC_AHB1_RELEASE_RESET();
 8003076:	4b0a      	ldr	r3, [pc, #40]	@ (80030a0 <HAL_DeInit+0x4c>)
 8003078:	2200      	movs	r2, #0
 800307a:	611a      	str	r2, [r3, #16]

  __HAL_RCC_AHB2_FORCE_RESET();
 800307c:	4b08      	ldr	r3, [pc, #32]	@ (80030a0 <HAL_DeInit+0x4c>)
 800307e:	22c1      	movs	r2, #193	@ 0xc1
 8003080:	615a      	str	r2, [r3, #20]
  __HAL_RCC_AHB2_RELEASE_RESET();
 8003082:	4b07      	ldr	r3, [pc, #28]	@ (80030a0 <HAL_DeInit+0x4c>)
 8003084:	2200      	movs	r2, #0
 8003086:	615a      	str	r2, [r3, #20]

  __HAL_RCC_AHB3_FORCE_RESET();
 8003088:	4b05      	ldr	r3, [pc, #20]	@ (80030a0 <HAL_DeInit+0x4c>)
 800308a:	2201      	movs	r2, #1
 800308c:	619a      	str	r2, [r3, #24]
  __HAL_RCC_AHB3_RELEASE_RESET();
 800308e:	4b04      	ldr	r3, [pc, #16]	@ (80030a0 <HAL_DeInit+0x4c>)
 8003090:	2200      	movs	r2, #0
 8003092:	619a      	str	r2, [r3, #24]

  /* De-Init the low level hardware */
  HAL_MspDeInit();
 8003094:	f000 f80c 	bl	80030b0 <HAL_MspDeInit>
    
  /* Return function status */
  return HAL_OK;
 8003098:	2300      	movs	r3, #0
}
 800309a:	4618      	mov	r0, r3
 800309c:	bd80      	pop	{r7, pc}
 800309e:	bf00      	nop
 80030a0:	40023800 	.word	0x40023800
 80030a4:	f6fec9ff 	.word	0xf6fec9ff
 80030a8:	04777933 	.word	0x04777933
 80030ac:	206011ff 	.word	0x206011ff

080030b0 <HAL_MspDeInit>:
/**
  * @brief  DeInitializes the MSP.
  * @retval None
  */
__weak void HAL_MspDeInit(void)
{
 80030b0:	b480      	push	{r7}
 80030b2:	af00      	add	r7, sp, #0
  /* NOTE : This function should not be modified, when the callback is needed,
            the HAL_MspDeInit could be implemented in the user file
   */ 
}
 80030b4:	bf00      	nop
 80030b6:	46bd      	mov	sp, r7
 80030b8:	f85d 7b04 	ldr.w	r7, [sp], #4
 80030bc:	4770      	bx	lr
	...

080030c0 <HAL_InitTick>:
  *       implementation  in user file.
  * @param TickPriority Tick interrupt priority.
  * @retval HAL status
  */
__weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority)
{
 80030c0:	b580      	push	{r7, lr}
 80030c2:	b082      	sub	sp, #8
 80030c4:	af00      	add	r7, sp, #0
 80030c6:	6078      	str	r0, [r7, #4]
  /* Configure the SysTick to have interrupt in 1ms time basis*/
  if (HAL_SYSTICK_Config(SystemCoreClock / (1000U / uwTickFreq)) > 0U)
 80030c8:	4b12      	ldr	r3, [pc, #72]	@ (8003114 <HAL_InitTick+0x54>)
 80030ca:	681a      	ldr	r2, [r3, #0]
 80030cc:	4b12      	ldr	r3, [pc, #72]	@ (8003118 <HAL_InitTick+0x58>)
 80030ce:	781b      	ldrb	r3, [r3, #0]
 80030d0:	4619      	mov	r1, r3
 80030d2:	f44f 737a 	mov.w	r3, #1000	@ 0x3e8
 80030d6:	fbb3 f3f1 	udiv	r3, r3, r1
 80030da:	fbb2 f3f3 	udiv	r3, r2, r3
 80030de:	4618      	mov	r0, r3
 80030e0:	f001 f8af 	bl	8004242 <HAL_SYSTICK_Config>
 80030e4:	4603      	mov	r3, r0
 80030e6:	2b00      	cmp	r3, #0
 80030e8:	d001      	beq.n	80030ee <HAL_InitTick+0x2e>
  {
    return HAL_ERROR;
 80030ea:	2301      	movs	r3, #1
 80030ec:	e00e      	b.n	800310c <HAL_InitTick+0x4c>
  }

  /* Configure the SysTick IRQ priority */
  if (TickPriority < (1UL << __NVIC_PRIO_BITS))
 80030ee:	687b      	ldr	r3, [r7, #4]
 80030f0:	2b0f      	cmp	r3, #15
 80030f2:	d80a      	bhi.n	800310a <HAL_InitTick+0x4a>
  {
    HAL_NVIC_SetPriority(SysTick_IRQn, TickPriority, 0U);
 80030f4:	2200      	movs	r2, #0
 80030f6:	6879      	ldr	r1, [r7, #4]
 80030f8:	f04f 30ff 	mov.w	r0, #4294967295
 80030fc:	f001 f869 	bl	80041d2 <HAL_NVIC_SetPriority>
    uwTickPrio = TickPriority;
 8003100:	4a06      	ldr	r2, [pc, #24]	@ (800311c <HAL_InitTick+0x5c>)
 8003102:	687b      	ldr	r3, [r7, #4]
 8003104:	6013      	str	r3, [r2, #0]
  {
    return HAL_ERROR;
  }

  /* Return function status */
  return HAL_OK;
 8003106:	2300      	movs	r3, #0
 8003108:	e000      	b.n	800310c <HAL_InitTick+0x4c>
    return HAL_ERROR;
 800310a:	2301      	movs	r3, #1
}
 800310c:	4618      	mov	r0, r3
 800310e:	3708      	adds	r7, #8
 8003110:	46bd      	mov	sp, r7
 8003112:	bd80      	pop	{r7, pc}
 8003114:	20000000 	.word	0x20000000
 8003118:	20000010 	.word	0x20000010
 800311c:	2000000c 	.word	0x2000000c

08003120 <HAL_IncTick>:
 * @note This function is declared as __weak to be overwritten in case of other 
  *      implementations in user file.
  * @retval None
  */
__weak void HAL_IncTick(void)
{
 8003120:	b480      	push	{r7}
 8003122:	af00      	add	r7, sp, #0
  uwTick += uwTickFreq;
 8003124:	4b06      	ldr	r3, [pc, #24]	@ (8003140 <HAL_IncTick+0x20>)
 8003126:	781b      	ldrb	r3, [r3, #0]
 8003128:	461a      	mov	r2, r3
 800312a:	4b06      	ldr	r3, [pc, #24]	@ (8003144 <HAL_IncTick+0x24>)
 800312c:	681b      	ldr	r3, [r3, #0]
 800312e:	4413      	add	r3, r2
 8003130:	4a04      	ldr	r2, [pc, #16]	@ (8003144 <HAL_IncTick+0x24>)
 8003132:	6013      	str	r3, [r2, #0]
}
 8003134:	bf00      	nop
 8003136:	46bd      	mov	sp, r7
 8003138:	f85d 7b04 	ldr.w	r7, [sp], #4
 800313c:	4770      	bx	lr
 800313e:	bf00      	nop
 8003140:	20000010 	.word	0x20000010
 8003144:	20001ebc 	.word	0x20001ebc

08003148 <HAL_GetTick>:
  * @note This function is declared as __weak to be overwritten in case of other 
  *       implementations in user file.
  * @retval tick value
  */
__weak uint32_t HAL_GetTick(void)
{
 8003148:	b480      	push	{r7}
 800314a:	af00      	add	r7, sp, #0
  return uwTick;
 800314c:	4b03      	ldr	r3, [pc, #12]	@ (800315c <HAL_GetTick+0x14>)
 800314e:	681b      	ldr	r3, [r3, #0]
}
 8003150:	4618      	mov	r0, r3
 8003152:	46bd      	mov	sp, r7
 8003154:	f85d 7b04 	ldr.w	r7, [sp], #4
 8003158:	4770      	bx	lr
 800315a:	bf00      	nop
 800315c:	20001ebc 	.word	0x20001ebc

08003160 <HAL_CAN_Init>:
  * @param  hcan pointer to a CAN_HandleTypeDef structure that contains
  *         the configuration information for the specified CAN.
  * @retval HAL status
  */
HAL_StatusTypeDef HAL_CAN_Init(CAN_HandleTypeDef *hcan)
{
 8003160:	b580      	push	{r7, lr}
 8003162:	b084      	sub	sp, #16
 8003164:	af00      	add	r7, sp, #0
 8003166:	6078      	str	r0, [r7, #4]
  uint32_t tickstart;

  /* Check CAN handle */
  if (hcan == NULL)
 8003168:	687b      	ldr	r3, [r7, #4]
 800316a:	2b00      	cmp	r3, #0
 800316c:	d101      	bne.n	8003172 <HAL_CAN_Init+0x12>
  {
    return HAL_ERROR;
 800316e:	2301      	movs	r3, #1
 8003170:	e0ed      	b.n	800334e <HAL_CAN_Init+0x1ee>
    /* Init the low level hardware: CLOCK, NVIC */
    hcan->MspInitCallback(hcan);
  }

#else
  if (hcan->State == HAL_CAN_STATE_RESET)
 8003172:	687b      	ldr	r3, [r7, #4]
 8003174:	f893 3020 	ldrb.w	r3, [r3, #32]
 8003178:	b2db      	uxtb	r3, r3
 800317a:	2b00      	cmp	r3, #0
 800317c:	d102      	bne.n	8003184 <HAL_CAN_Init+0x24>
  {
    /* Init the low level hardware: CLOCK, NVIC */
    HAL_CAN_MspInit(hcan);
 800317e:	6878      	ldr	r0, [r7, #4]
 8003180:	f7fd f9f0 	bl	8000564 <HAL_CAN_MspInit>
  }
#endif /* USE_HAL_CAN_REGISTER_CALLBACKS */

  /* Request initialisation */
  SET_BIT(hcan->Instance->MCR, CAN_MCR_INRQ);
 8003184:	687b      	ldr	r3, [r7, #4]
 8003186:	681b      	ldr	r3, [r3, #0]
 8003188:	681a      	ldr	r2, [r3, #0]
 800318a:	687b      	ldr	r3, [r7, #4]
 800318c:	681b      	ldr	r3, [r3, #0]
 800318e:	f042 0201 	orr.w	r2, r2, #1
 8003192:	601a      	str	r2, [r3, #0]

  /* Get tick */
  tickstart = HAL_GetTick();
 8003194:	f7ff ffd8 	bl	8003148 <HAL_GetTick>
 8003198:	60f8      	str	r0, [r7, #12]

  /* Wait initialisation acknowledge */
  while ((hcan->Instance->MSR & CAN_MSR_INAK) == 0U)
 800319a:	e012      	b.n	80031c2 <HAL_CAN_Init+0x62>
  {
    if ((HAL_GetTick() - tickstart) > CAN_TIMEOUT_VALUE)
 800319c:	f7ff ffd4 	bl	8003148 <HAL_GetTick>
 80031a0:	4602      	mov	r2, r0
 80031a2:	68fb      	ldr	r3, [r7, #12]
 80031a4:	1ad3      	subs	r3, r2, r3
 80031a6:	2b0a      	cmp	r3, #10
 80031a8:	d90b      	bls.n	80031c2 <HAL_CAN_Init+0x62>
    {
      /* Update error code */
      hcan->ErrorCode |= HAL_CAN_ERROR_TIMEOUT;
 80031aa:	687b      	ldr	r3, [r7, #4]
 80031ac:	6a5b      	ldr	r3, [r3, #36]	@ 0x24
 80031ae:	f443 3200 	orr.w	r2, r3, #131072	@ 0x20000
 80031b2:	687b      	ldr	r3, [r7, #4]
 80031b4:	625a      	str	r2, [r3, #36]	@ 0x24

      /* Change CAN state */
      hcan->State = HAL_CAN_STATE_ERROR;
 80031b6:	687b      	ldr	r3, [r7, #4]
 80031b8:	2205      	movs	r2, #5
 80031ba:	f883 2020 	strb.w	r2, [r3, #32]

      return HAL_ERROR;
 80031be:	2301      	movs	r3, #1
 80031c0:	e0c5      	b.n	800334e <HAL_CAN_Init+0x1ee>
  while ((hcan->Instance->MSR & CAN_MSR_INAK) == 0U)
 80031c2:	687b      	ldr	r3, [r7, #4]
 80031c4:	681b      	ldr	r3, [r3, #0]
 80031c6:	685b      	ldr	r3, [r3, #4]
 80031c8:	f003 0301 	and.w	r3, r3, #1
 80031cc:	2b00      	cmp	r3, #0
 80031ce:	d0e5      	beq.n	800319c <HAL_CAN_Init+0x3c>
    }
  }

  /* Exit from sleep mode */
  CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_SLEEP);
 80031d0:	687b      	ldr	r3, [r7, #4]
 80031d2:	681b      	ldr	r3, [r3, #0]
 80031d4:	681a      	ldr	r2, [r3, #0]
 80031d6:	687b      	ldr	r3, [r7, #4]
 80031d8:	681b      	ldr	r3, [r3, #0]
 80031da:	f022 0202 	bic.w	r2, r2, #2
 80031de:	601a      	str	r2, [r3, #0]

  /* Get tick */
  tickstart = HAL_GetTick();
 80031e0:	f7ff ffb2 	bl	8003148 <HAL_GetTick>
 80031e4:	60f8      	str	r0, [r7, #12]

  /* Check Sleep mode leave acknowledge */
  while ((hcan->Instance->MSR & CAN_MSR_SLAK) != 0U)
 80031e6:	e012      	b.n	800320e <HAL_CAN_Init+0xae>
  {
    if ((HAL_GetTick() - tickstart) > CAN_TIMEOUT_VALUE)
 80031e8:	f7ff ffae 	bl	8003148 <HAL_GetTick>
 80031ec:	4602      	mov	r2, r0
 80031ee:	68fb      	ldr	r3, [r7, #12]
 80031f0:	1ad3      	subs	r3, r2, r3
 80031f2:	2b0a      	cmp	r3, #10
 80031f4:	d90b      	bls.n	800320e <HAL_CAN_Init+0xae>
    {
      /* Update error code */
      hcan->ErrorCode |= HAL_CAN_ERROR_TIMEOUT;
 80031f6:	687b      	ldr	r3, [r7, #4]
 80031f8:	6a5b      	ldr	r3, [r3, #36]	@ 0x24
 80031fa:	f443 3200 	orr.w	r2, r3, #131072	@ 0x20000
 80031fe:	687b      	ldr	r3, [r7, #4]
 8003200:	625a      	str	r2, [r3, #36]	@ 0x24

      /* Change CAN state */
      hcan->State = HAL_CAN_STATE_ERROR;
 8003202:	687b      	ldr	r3, [r7, #4]
 8003204:	2205      	movs	r2, #5
 8003206:	f883 2020 	strb.w	r2, [r3, #32]

      return HAL_ERROR;
 800320a:	2301      	movs	r3, #1
 800320c:	e09f      	b.n	800334e <HAL_CAN_Init+0x1ee>
  while ((hcan->Instance->MSR & CAN_MSR_SLAK) != 0U)
 800320e:	687b      	ldr	r3, [r7, #4]
 8003210:	681b      	ldr	r3, [r3, #0]
 8003212:	685b      	ldr	r3, [r3, #4]
 8003214:	f003 0302 	and.w	r3, r3, #2
 8003218:	2b00      	cmp	r3, #0
 800321a:	d1e5      	bne.n	80031e8 <HAL_CAN_Init+0x88>
    }
  }

  /* Set the time triggered communication mode */
  if (hcan->Init.TimeTriggeredMode == ENABLE)
 800321c:	687b      	ldr	r3, [r7, #4]
 800321e:	7e1b      	ldrb	r3, [r3, #24]
 8003220:	2b01      	cmp	r3, #1
 8003222:	d108      	bne.n	8003236 <HAL_CAN_Init+0xd6>
  {
    SET_BIT(hcan->Instance->MCR, CAN_MCR_TTCM);
 8003224:	687b      	ldr	r3, [r7, #4]
 8003226:	681b      	ldr	r3, [r3, #0]
 8003228:	681a      	ldr	r2, [r3, #0]
 800322a:	687b      	ldr	r3, [r7, #4]
 800322c:	681b      	ldr	r3, [r3, #0]
 800322e:	f042 0280 	orr.w	r2, r2, #128	@ 0x80
 8003232:	601a      	str	r2, [r3, #0]
 8003234:	e007      	b.n	8003246 <HAL_CAN_Init+0xe6>
  }
  else
  {
    CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_TTCM);
 8003236:	687b      	ldr	r3, [r7, #4]
 8003238:	681b      	ldr	r3, [r3, #0]
 800323a:	681a      	ldr	r2, [r3, #0]
 800323c:	687b      	ldr	r3, [r7, #4]
 800323e:	681b      	ldr	r3, [r3, #0]
 8003240:	f022 0280 	bic.w	r2, r2, #128	@ 0x80
 8003244:	601a      	str	r2, [r3, #0]
  }

  /* Set the automatic bus-off management */
  if (hcan->Init.AutoBusOff == ENABLE)
 8003246:	687b      	ldr	r3, [r7, #4]
 8003248:	7e5b      	ldrb	r3, [r3, #25]
 800324a:	2b01      	cmp	r3, #1
 800324c:	d108      	bne.n	8003260 <HAL_CAN_Init+0x100>
  {
    SET_BIT(hcan->Instance->MCR, CAN_MCR_ABOM);
 800324e:	687b      	ldr	r3, [r7, #4]
 8003250:	681b      	ldr	r3, [r3, #0]
 8003252:	681a      	ldr	r2, [r3, #0]
 8003254:	687b      	ldr	r3, [r7, #4]
 8003256:	681b      	ldr	r3, [r3, #0]
 8003258:	f042 0240 	orr.w	r2, r2, #64	@ 0x40
 800325c:	601a      	str	r2, [r3, #0]
 800325e:	e007      	b.n	8003270 <HAL_CAN_Init+0x110>
  }
  else
  {
    CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_ABOM);
 8003260:	687b      	ldr	r3, [r7, #4]
 8003262:	681b      	ldr	r3, [r3, #0]
 8003264:	681a      	ldr	r2, [r3, #0]
 8003266:	687b      	ldr	r3, [r7, #4]
 8003268:	681b      	ldr	r3, [r3, #0]
 800326a:	f022 0240 	bic.w	r2, r2, #64	@ 0x40
 800326e:	601a      	str	r2, [r3, #0]
  }

  /* Set the automatic wake-up mode */
  if (hcan->Init.AutoWakeUp == ENABLE)
 8003270:	687b      	ldr	r3, [r7, #4]
 8003272:	7e9b      	ldrb	r3, [r3, #26]
 8003274:	2b01      	cmp	r3, #1
 8003276:	d108      	bne.n	800328a <HAL_CAN_Init+0x12a>
  {
    SET_BIT(hcan->Instance->MCR, CAN_MCR_AWUM);
 8003278:	687b      	ldr	r3, [r7, #4]
 800327a:	681b      	ldr	r3, [r3, #0]
 800327c:	681a      	ldr	r2, [r3, #0]
 800327e:	687b      	ldr	r3, [r7, #4]
 8003280:	681b      	ldr	r3, [r3, #0]
 8003282:	f042 0220 	orr.w	r2, r2, #32
 8003286:	601a      	str	r2, [r3, #0]
 8003288:	e007      	b.n	800329a <HAL_CAN_Init+0x13a>
  }
  else
  {
    CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_AWUM);
 800328a:	687b      	ldr	r3, [r7, #4]
 800328c:	681b      	ldr	r3, [r3, #0]
 800328e:	681a      	ldr	r2, [r3, #0]
 8003290:	687b      	ldr	r3, [r7, #4]
 8003292:	681b      	ldr	r3, [r3, #0]
 8003294:	f022 0220 	bic.w	r2, r2, #32
 8003298:	601a      	str	r2, [r3, #0]
  }

  /* Set the automatic retransmission */
  if (hcan->Init.AutoRetransmission == ENABLE)
 800329a:	687b      	ldr	r3, [r7, #4]
 800329c:	7edb      	ldrb	r3, [r3, #27]
 800329e:	2b01      	cmp	r3, #1
 80032a0:	d108      	bne.n	80032b4 <HAL_CAN_Init+0x154>
  {
    CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_NART);
 80032a2:	687b      	ldr	r3, [r7, #4]
 80032a4:	681b      	ldr	r3, [r3, #0]
 80032a6:	681a      	ldr	r2, [r3, #0]
 80032a8:	687b      	ldr	r3, [r7, #4]
 80032aa:	681b      	ldr	r3, [r3, #0]
 80032ac:	f022 0210 	bic.w	r2, r2, #16
 80032b0:	601a      	str	r2, [r3, #0]
 80032b2:	e007      	b.n	80032c4 <HAL_CAN_Init+0x164>
  }
  else
  {
    SET_BIT(hcan->Instance->MCR, CAN_MCR_NART);
 80032b4:	687b      	ldr	r3, [r7, #4]
 80032b6:	681b      	ldr	r3, [r3, #0]
 80032b8:	681a      	ldr	r2, [r3, #0]
 80032ba:	687b      	ldr	r3, [r7, #4]
 80032bc:	681b      	ldr	r3, [r3, #0]
 80032be:	f042 0210 	orr.w	r2, r2, #16
 80032c2:	601a      	str	r2, [r3, #0]
  }

  /* Set the receive FIFO locked mode */
  if (hcan->Init.ReceiveFifoLocked == ENABLE)
 80032c4:	687b      	ldr	r3, [r7, #4]
 80032c6:	7f1b      	ldrb	r3, [r3, #28]
 80032c8:	2b01      	cmp	r3, #1
 80032ca:	d108      	bne.n	80032de <HAL_CAN_Init+0x17e>
  {
    SET_BIT(hcan->Instance->MCR, CAN_MCR_RFLM);
 80032cc:	687b      	ldr	r3, [r7, #4]
 80032ce:	681b      	ldr	r3, [r3, #0]
 80032d0:	681a      	ldr	r2, [r3, #0]
 80032d2:	687b      	ldr	r3, [r7, #4]
 80032d4:	681b      	ldr	r3, [r3, #0]
 80032d6:	f042 0208 	orr.w	r2, r2, #8
 80032da:	601a      	str	r2, [r3, #0]
 80032dc:	e007      	b.n	80032ee <HAL_CAN_Init+0x18e>
  }
  else
  {
    CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_RFLM);
 80032de:	687b      	ldr	r3, [r7, #4]
 80032e0:	681b      	ldr	r3, [r3, #0]
 80032e2:	681a      	ldr	r2, [r3, #0]
 80032e4:	687b      	ldr	r3, [r7, #4]
 80032e6:	681b      	ldr	r3, [r3, #0]
 80032e8:	f022 0208 	bic.w	r2, r2, #8
 80032ec:	601a      	str	r2, [r3, #0]
  }

  /* Set the transmit FIFO priority */
  if (hcan->Init.TransmitFifoPriority == ENABLE)
 80032ee:	687b      	ldr	r3, [r7, #4]
 80032f0:	7f5b      	ldrb	r3, [r3, #29]
 80032f2:	2b01      	cmp	r3, #1
 80032f4:	d108      	bne.n	8003308 <HAL_CAN_Init+0x1a8>
  {
    SET_BIT(hcan->Instance->MCR, CAN_MCR_TXFP);
 80032f6:	687b      	ldr	r3, [r7, #4]
 80032f8:	681b      	ldr	r3, [r3, #0]
 80032fa:	681a      	ldr	r2, [r3, #0]
 80032fc:	687b      	ldr	r3, [r7, #4]
 80032fe:	681b      	ldr	r3, [r3, #0]
 8003300:	f042 0204 	orr.w	r2, r2, #4
 8003304:	601a      	str	r2, [r3, #0]
 8003306:	e007      	b.n	8003318 <HAL_CAN_Init+0x1b8>
  }
  else
  {
    CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_TXFP);
 8003308:	687b      	ldr	r3, [r7, #4]
 800330a:	681b      	ldr	r3, [r3, #0]
 800330c:	681a      	ldr	r2, [r3, #0]
 800330e:	687b      	ldr	r3, [r7, #4]
 8003310:	681b      	ldr	r3, [r3, #0]
 8003312:	f022 0204 	bic.w	r2, r2, #4
 8003316:	601a      	str	r2, [r3, #0]
  }

  /* Set the bit timing register */
  WRITE_REG(hcan->Instance->BTR, (uint32_t)(hcan->Init.Mode           |
 8003318:	687b      	ldr	r3, [r7, #4]
 800331a:	689a      	ldr	r2, [r3, #8]
 800331c:	687b      	ldr	r3, [r7, #4]
 800331e:	68db      	ldr	r3, [r3, #12]
 8003320:	431a      	orrs	r2, r3
 8003322:	687b      	ldr	r3, [r7, #4]
 8003324:	691b      	ldr	r3, [r3, #16]
 8003326:	431a      	orrs	r2, r3
 8003328:	687b      	ldr	r3, [r7, #4]
 800332a:	695b      	ldr	r3, [r3, #20]
 800332c:	ea42 0103 	orr.w	r1, r2, r3
 8003330:	687b      	ldr	r3, [r7, #4]
 8003332:	685b      	ldr	r3, [r3, #4]
 8003334:	1e5a      	subs	r2, r3, #1
 8003336:	687b      	ldr	r3, [r7, #4]
 8003338:	681b      	ldr	r3, [r3, #0]
 800333a:	430a      	orrs	r2, r1
 800333c:	61da      	str	r2, [r3, #28]
                                            hcan->Init.TimeSeg1       |
                                            hcan->Init.TimeSeg2       |
                                            (hcan->Init.Prescaler - 1U)));

  /* Initialize the error code */
  hcan->ErrorCode = HAL_CAN_ERROR_NONE;
 800333e:	687b      	ldr	r3, [r7, #4]
 8003340:	2200      	movs	r2, #0
 8003342:	625a      	str	r2, [r3, #36]	@ 0x24

  /* Initialize the CAN state */
  hcan->State = HAL_CAN_STATE_READY;
 8003344:	687b      	ldr	r3, [r7, #4]
 8003346:	2201      	movs	r2, #1
 8003348:	f883 2020 	strb.w	r2, [r3, #32]

  /* Return function status */
  return HAL_OK;
 800334c:	2300      	movs	r3, #0
}
 800334e:	4618      	mov	r0, r3
 8003350:	3710      	adds	r7, #16
 8003352:	46bd      	mov	sp, r7
 8003354:	bd80      	pop	{r7, pc}

08003356 <HAL_CAN_DeInit>:
  * @param  hcan pointer to a CAN_HandleTypeDef structure that contains
  *         the configuration information for the specified CAN.
  * @retval HAL status
  */
HAL_StatusTypeDef HAL_CAN_DeInit(CAN_HandleTypeDef *hcan)
{
 8003356:	b580      	push	{r7, lr}
 8003358:	b082      	sub	sp, #8
 800335a:	af00      	add	r7, sp, #0
 800335c:	6078      	str	r0, [r7, #4]
  /* Check CAN handle */
  if (hcan == NULL)
 800335e:	687b      	ldr	r3, [r7, #4]
 8003360:	2b00      	cmp	r3, #0
 8003362:	d101      	bne.n	8003368 <HAL_CAN_DeInit+0x12>
  {
    return HAL_ERROR;
 8003364:	2301      	movs	r3, #1
 8003366:	e015      	b.n	8003394 <HAL_CAN_DeInit+0x3e>

  /* Check the parameters */
  assert_param(IS_CAN_ALL_INSTANCE(hcan->Instance));

  /* Stop the CAN module */
  (void)HAL_CAN_Stop(hcan);
 8003368:	6878      	ldr	r0, [r7, #4]
 800336a:	f000 f939 	bl	80035e0 <HAL_CAN_Stop>
  /* DeInit the low level hardware: CLOCK, NVIC */
  hcan->MspDeInitCallback(hcan);

#else
  /* DeInit the low level hardware: CLOCK, NVIC */
  HAL_CAN_MspDeInit(hcan);
 800336e:	6878      	ldr	r0, [r7, #4]
 8003370:	f7fd f948 	bl	8000604 <HAL_CAN_MspDeInit>
#endif /* USE_HAL_CAN_REGISTER_CALLBACKS */

  /* Reset the CAN peripheral */
  SET_BIT(hcan->Instance->MCR, CAN_MCR_RESET);
 8003374:	687b      	ldr	r3, [r7, #4]
 8003376:	681b      	ldr	r3, [r3, #0]
 8003378:	681a      	ldr	r2, [r3, #0]
 800337a:	687b      	ldr	r3, [r7, #4]
 800337c:	681b      	ldr	r3, [r3, #0]
 800337e:	f442 4200 	orr.w	r2, r2, #32768	@ 0x8000
 8003382:	601a      	str	r2, [r3, #0]

  /* Reset the CAN ErrorCode */
  hcan->ErrorCode = HAL_CAN_ERROR_NONE;
 8003384:	687b      	ldr	r3, [r7, #4]
 8003386:	2200      	movs	r2, #0
 8003388:	625a      	str	r2, [r3, #36]	@ 0x24

  /* Change CAN state */
  hcan->State = HAL_CAN_STATE_RESET;
 800338a:	687b      	ldr	r3, [r7, #4]
 800338c:	2200      	movs	r2, #0
 800338e:	f883 2020 	strb.w	r2, [r3, #32]

  /* Return function status */
  return HAL_OK;
 8003392:	2300      	movs	r3, #0
}
 8003394:	4618      	mov	r0, r3
 8003396:	3708      	adds	r7, #8
 8003398:	46bd      	mov	sp, r7
 800339a:	bd80      	pop	{r7, pc}

0800339c <HAL_CAN_ConfigFilter>:
  * @param  sFilterConfig pointer to a CAN_FilterTypeDef structure that
  *         contains the filter configuration information.
  * @retval None
  */
HAL_StatusTypeDef HAL_CAN_ConfigFilter(CAN_HandleTypeDef *hcan, const CAN_FilterTypeDef *sFilterConfig)
{
 800339c:	b480      	push	{r7}
 800339e:	b087      	sub	sp, #28
 80033a0:	af00      	add	r7, sp, #0
 80033a2:	6078      	str	r0, [r7, #4]
 80033a4:	6039      	str	r1, [r7, #0]
  uint32_t filternbrbitpos;
  CAN_TypeDef *can_ip;
  HAL_CAN_StateTypeDef state = hcan->State;
 80033a6:	687b      	ldr	r3, [r7, #4]
 80033a8:	f893 3020 	ldrb.w	r3, [r3, #32]
 80033ac:	75fb      	strb	r3, [r7, #23]

  if ((state == HAL_CAN_STATE_READY) ||
 80033ae:	7dfb      	ldrb	r3, [r7, #23]
 80033b0:	2b01      	cmp	r3, #1
 80033b2:	d003      	beq.n	80033bc <HAL_CAN_ConfigFilter+0x20>
 80033b4:	7dfb      	ldrb	r3, [r7, #23]
 80033b6:	2b02      	cmp	r3, #2
 80033b8:	f040 80be 	bne.w	8003538 <HAL_CAN_ConfigFilter+0x19c>
      assert_param(IS_CAN_FILTER_BANK_DUAL(sFilterConfig->SlaveStartFilterBank));
    }
#elif defined(CAN2)
    /* CAN1 and CAN2 are dual instances with 28 common filters banks */
    /* Select master instance to access the filter banks */
    can_ip = CAN1;
 80033bc:	4b65      	ldr	r3, [pc, #404]	@ (8003554 <HAL_CAN_ConfigFilter+0x1b8>)
 80033be:	613b      	str	r3, [r7, #16]
    /* Check the parameters */
    assert_param(IS_CAN_FILTER_BANK_SINGLE(sFilterConfig->FilterBank));
#endif /* CAN3 */

    /* Initialisation mode for the filter */
    SET_BIT(can_ip->FMR, CAN_FMR_FINIT);
 80033c0:	693b      	ldr	r3, [r7, #16]
 80033c2:	f8d3 3200 	ldr.w	r3, [r3, #512]	@ 0x200
 80033c6:	f043 0201 	orr.w	r2, r3, #1
 80033ca:	693b      	ldr	r3, [r7, #16]
 80033cc:	f8c3 2200 	str.w	r2, [r3, #512]	@ 0x200
      SET_BIT(can_ip->FMR, sFilterConfig->SlaveStartFilterBank << CAN_FMR_CAN2SB_Pos);
    }

#elif defined(CAN2)
    /* Select the start filter number of CAN2 slave instance */
    CLEAR_BIT(can_ip->FMR, CAN_FMR_CAN2SB);
 80033d0:	693b      	ldr	r3, [r7, #16]
 80033d2:	f8d3 3200 	ldr.w	r3, [r3, #512]	@ 0x200
 80033d6:	f423 527c 	bic.w	r2, r3, #16128	@ 0x3f00
 80033da:	693b      	ldr	r3, [r7, #16]
 80033dc:	f8c3 2200 	str.w	r2, [r3, #512]	@ 0x200
    SET_BIT(can_ip->FMR, sFilterConfig->SlaveStartFilterBank << CAN_FMR_CAN2SB_Pos);
 80033e0:	693b      	ldr	r3, [r7, #16]
 80033e2:	f8d3 2200 	ldr.w	r2, [r3, #512]	@ 0x200
 80033e6:	683b      	ldr	r3, [r7, #0]
 80033e8:	6a5b      	ldr	r3, [r3, #36]	@ 0x24
 80033ea:	021b      	lsls	r3, r3, #8
 80033ec:	431a      	orrs	r2, r3
 80033ee:	693b      	ldr	r3, [r7, #16]
 80033f0:	f8c3 2200 	str.w	r2, [r3, #512]	@ 0x200

#endif /* CAN3 */
    /* Convert filter number into bit position */
    filternbrbitpos = (uint32_t)1 << (sFilterConfig->FilterBank & 0x1FU);
 80033f4:	683b      	ldr	r3, [r7, #0]
 80033f6:	695b      	ldr	r3, [r3, #20]
 80033f8:	f003 031f 	and.w	r3, r3, #31
 80033fc:	2201      	movs	r2, #1
 80033fe:	fa02 f303 	lsl.w	r3, r2, r3
 8003402:	60fb      	str	r3, [r7, #12]

    /* Filter Deactivation */
    CLEAR_BIT(can_ip->FA1R, filternbrbitpos);
 8003404:	693b      	ldr	r3, [r7, #16]
 8003406:	f8d3 221c 	ldr.w	r2, [r3, #540]	@ 0x21c
 800340a:	68fb      	ldr	r3, [r7, #12]
 800340c:	43db      	mvns	r3, r3
 800340e:	401a      	ands	r2, r3
 8003410:	693b      	ldr	r3, [r7, #16]
 8003412:	f8c3 221c 	str.w	r2, [r3, #540]	@ 0x21c

    /* Filter Scale */
    if (sFilterConfig->FilterScale == CAN_FILTERSCALE_16BIT)
 8003416:	683b      	ldr	r3, [r7, #0]
 8003418:	69db      	ldr	r3, [r3, #28]
 800341a:	2b00      	cmp	r3, #0
 800341c:	d123      	bne.n	8003466 <HAL_CAN_ConfigFilter+0xca>
    {
      /* 16-bit scale for the filter */
      CLEAR_BIT(can_ip->FS1R, filternbrbitpos);
 800341e:	693b      	ldr	r3, [r7, #16]
 8003420:	f8d3 220c 	ldr.w	r2, [r3, #524]	@ 0x20c
 8003424:	68fb      	ldr	r3, [r7, #12]
 8003426:	43db      	mvns	r3, r3
 8003428:	401a      	ands	r2, r3
 800342a:	693b      	ldr	r3, [r7, #16]
 800342c:	f8c3 220c 	str.w	r2, [r3, #524]	@ 0x20c

      /* First 16-bit identifier and First 16-bit mask */
      /* Or First 16-bit identifier and Second 16-bit identifier */
      can_ip->sFilterRegister[sFilterConfig->FilterBank].FR1 =
        ((0x0000FFFFU & (uint32_t)sFilterConfig->FilterMaskIdLow) << 16U) |
 8003430:	683b      	ldr	r3, [r7, #0]
 8003432:	68db      	ldr	r3, [r3, #12]
 8003434:	0419      	lsls	r1, r3, #16
        (0x0000FFFFU & (uint32_t)sFilterConfig->FilterIdLow);
 8003436:	683b      	ldr	r3, [r7, #0]
 8003438:	685b      	ldr	r3, [r3, #4]
 800343a:	b29b      	uxth	r3, r3
      can_ip->sFilterRegister[sFilterConfig->FilterBank].FR1 =
 800343c:	683a      	ldr	r2, [r7, #0]
 800343e:	6952      	ldr	r2, [r2, #20]
        ((0x0000FFFFU & (uint32_t)sFilterConfig->FilterMaskIdLow) << 16U) |
 8003440:	4319      	orrs	r1, r3
      can_ip->sFilterRegister[sFilterConfig->FilterBank].FR1 =
 8003442:	693b      	ldr	r3, [r7, #16]
 8003444:	3248      	adds	r2, #72	@ 0x48
 8003446:	f843 1032 	str.w	r1, [r3, r2, lsl #3]

      /* Second 16-bit identifier and Second 16-bit mask */
      /* Or Third 16-bit identifier and Fourth 16-bit identifier */
      can_ip->sFilterRegister[sFilterConfig->FilterBank].FR2 =
        ((0x0000FFFFU & (uint32_t)sFilterConfig->FilterMaskIdHigh) << 16U) |
 800344a:	683b      	ldr	r3, [r7, #0]
 800344c:	689b      	ldr	r3, [r3, #8]
 800344e:	0419      	lsls	r1, r3, #16
        (0x0000FFFFU & (uint32_t)sFilterConfig->FilterIdHigh);
 8003450:	683b      	ldr	r3, [r7, #0]
 8003452:	681b      	ldr	r3, [r3, #0]
 8003454:	b29a      	uxth	r2, r3
      can_ip->sFilterRegister[sFilterConfig->FilterBank].FR2 =
 8003456:	683b      	ldr	r3, [r7, #0]
 8003458:	695b      	ldr	r3, [r3, #20]
        ((0x0000FFFFU & (uint32_t)sFilterConfig->FilterMaskIdHigh) << 16U) |
 800345a:	430a      	orrs	r2, r1
      can_ip->sFilterRegister[sFilterConfig->FilterBank].FR2 =
 800345c:	6939      	ldr	r1, [r7, #16]
 800345e:	3348      	adds	r3, #72	@ 0x48
 8003460:	00db      	lsls	r3, r3, #3
 8003462:	440b      	add	r3, r1
 8003464:	605a      	str	r2, [r3, #4]
    }

    if (sFilterConfig->FilterScale == CAN_FILTERSCALE_32BIT)
 8003466:	683b      	ldr	r3, [r7, #0]
 8003468:	69db      	ldr	r3, [r3, #28]
 800346a:	2b01      	cmp	r3, #1
 800346c:	d122      	bne.n	80034b4 <HAL_CAN_ConfigFilter+0x118>
    {
      /* 32-bit scale for the filter */
      SET_BIT(can_ip->FS1R, filternbrbitpos);
 800346e:	693b      	ldr	r3, [r7, #16]
 8003470:	f8d3 220c 	ldr.w	r2, [r3, #524]	@ 0x20c
 8003474:	68fb      	ldr	r3, [r7, #12]
 8003476:	431a      	orrs	r2, r3
 8003478:	693b      	ldr	r3, [r7, #16]
 800347a:	f8c3 220c 	str.w	r2, [r3, #524]	@ 0x20c

      /* 32-bit identifier or First 32-bit identifier */
      can_ip->sFilterRegister[sFilterConfig->FilterBank].FR1 =
        ((0x0000FFFFU & (uint32_t)sFilterConfig->FilterIdHigh) << 16U) |
 800347e:	683b      	ldr	r3, [r7, #0]
 8003480:	681b      	ldr	r3, [r3, #0]
 8003482:	0419      	lsls	r1, r3, #16
        (0x0000FFFFU & (uint32_t)sFilterConfig->FilterIdLow);
 8003484:	683b      	ldr	r3, [r7, #0]
 8003486:	685b      	ldr	r3, [r3, #4]
 8003488:	b29b      	uxth	r3, r3
      can_ip->sFilterRegister[sFilterConfig->FilterBank].FR1 =
 800348a:	683a      	ldr	r2, [r7, #0]
 800348c:	6952      	ldr	r2, [r2, #20]
        ((0x0000FFFFU & (uint32_t)sFilterConfig->FilterIdHigh) << 16U) |
 800348e:	4319      	orrs	r1, r3
      can_ip->sFilterRegister[sFilterConfig->FilterBank].FR1 =
 8003490:	693b      	ldr	r3, [r7, #16]
 8003492:	3248      	adds	r2, #72	@ 0x48
 8003494:	f843 1032 	str.w	r1, [r3, r2, lsl #3]

      /* 32-bit mask or Second 32-bit identifier */
      can_ip->sFilterRegister[sFilterConfig->FilterBank].FR2 =
        ((0x0000FFFFU & (uint32_t)sFilterConfig->FilterMaskIdHigh) << 16U) |
 8003498:	683b      	ldr	r3, [r7, #0]
 800349a:	689b      	ldr	r3, [r3, #8]
 800349c:	0419      	lsls	r1, r3, #16
        (0x0000FFFFU & (uint32_t)sFilterConfig->FilterMaskIdLow);
 800349e:	683b      	ldr	r3, [r7, #0]
 80034a0:	68db      	ldr	r3, [r3, #12]
 80034a2:	b29a      	uxth	r2, r3
      can_ip->sFilterRegister[sFilterConfig->FilterBank].FR2 =
 80034a4:	683b      	ldr	r3, [r7, #0]
 80034a6:	695b      	ldr	r3, [r3, #20]
        ((0x0000FFFFU & (uint32_t)sFilterConfig->FilterMaskIdHigh) << 16U) |
 80034a8:	430a      	orrs	r2, r1
      can_ip->sFilterRegister[sFilterConfig->FilterBank].FR2 =
 80034aa:	6939      	ldr	r1, [r7, #16]
 80034ac:	3348      	adds	r3, #72	@ 0x48
 80034ae:	00db      	lsls	r3, r3, #3
 80034b0:	440b      	add	r3, r1
 80034b2:	605a      	str	r2, [r3, #4]
    }

    /* Filter Mode */
    if (sFilterConfig->FilterMode == CAN_FILTERMODE_IDMASK)
 80034b4:	683b      	ldr	r3, [r7, #0]
 80034b6:	699b      	ldr	r3, [r3, #24]
 80034b8:	2b00      	cmp	r3, #0
 80034ba:	d109      	bne.n	80034d0 <HAL_CAN_ConfigFilter+0x134>
    {
      /* Id/Mask mode for the filter*/
      CLEAR_BIT(can_ip->FM1R, filternbrbitpos);
 80034bc:	693b      	ldr	r3, [r7, #16]
 80034be:	f8d3 2204 	ldr.w	r2, [r3, #516]	@ 0x204
 80034c2:	68fb      	ldr	r3, [r7, #12]
 80034c4:	43db      	mvns	r3, r3
 80034c6:	401a      	ands	r2, r3
 80034c8:	693b      	ldr	r3, [r7, #16]
 80034ca:	f8c3 2204 	str.w	r2, [r3, #516]	@ 0x204
 80034ce:	e007      	b.n	80034e0 <HAL_CAN_ConfigFilter+0x144>
    }
    else /* CAN_FilterInitStruct->CAN_FilterMode == CAN_FilterMode_IdList */
    {
      /* Identifier list mode for the filter*/
      SET_BIT(can_ip->FM1R, filternbrbitpos);
 80034d0:	693b      	ldr	r3, [r7, #16]
 80034d2:	f8d3 2204 	ldr.w	r2, [r3, #516]	@ 0x204
 80034d6:	68fb      	ldr	r3, [r7, #12]
 80034d8:	431a      	orrs	r2, r3
 80034da:	693b      	ldr	r3, [r7, #16]
 80034dc:	f8c3 2204 	str.w	r2, [r3, #516]	@ 0x204
    }

    /* Filter FIFO assignment */
    if (sFilterConfig->FilterFIFOAssignment == CAN_FILTER_FIFO0)
 80034e0:	683b      	ldr	r3, [r7, #0]
 80034e2:	691b      	ldr	r3, [r3, #16]
 80034e4:	2b00      	cmp	r3, #0
 80034e6:	d109      	bne.n	80034fc <HAL_CAN_ConfigFilter+0x160>
    {
      /* FIFO 0 assignation for the filter */
      CLEAR_BIT(can_ip->FFA1R, filternbrbitpos);
 80034e8:	693b      	ldr	r3, [r7, #16]
 80034ea:	f8d3 2214 	ldr.w	r2, [r3, #532]	@ 0x214
 80034ee:	68fb      	ldr	r3, [r7, #12]
 80034f0:	43db      	mvns	r3, r3
 80034f2:	401a      	ands	r2, r3
 80034f4:	693b      	ldr	r3, [r7, #16]
 80034f6:	f8c3 2214 	str.w	r2, [r3, #532]	@ 0x214
 80034fa:	e007      	b.n	800350c <HAL_CAN_ConfigFilter+0x170>
    }
    else
    {
      /* FIFO 1 assignation for the filter */
      SET_BIT(can_ip->FFA1R, filternbrbitpos);
 80034fc:	693b      	ldr	r3, [r7, #16]
 80034fe:	f8d3 2214 	ldr.w	r2, [r3, #532]	@ 0x214
 8003502:	68fb      	ldr	r3, [r7, #12]
 8003504:	431a      	orrs	r2, r3
 8003506:	693b      	ldr	r3, [r7, #16]
 8003508:	f8c3 2214 	str.w	r2, [r3, #532]	@ 0x214
    }

    /* Filter activation */
    if (sFilterConfig->FilterActivation == CAN_FILTER_ENABLE)
 800350c:	683b      	ldr	r3, [r7, #0]
 800350e:	6a1b      	ldr	r3, [r3, #32]
 8003510:	2b01      	cmp	r3, #1
 8003512:	d107      	bne.n	8003524 <HAL_CAN_ConfigFilter+0x188>
    {
      SET_BIT(can_ip->FA1R, filternbrbitpos);
 8003514:	693b      	ldr	r3, [r7, #16]
 8003516:	f8d3 221c 	ldr.w	r2, [r3, #540]	@ 0x21c
 800351a:	68fb      	ldr	r3, [r7, #12]
 800351c:	431a      	orrs	r2, r3
 800351e:	693b      	ldr	r3, [r7, #16]
 8003520:	f8c3 221c 	str.w	r2, [r3, #540]	@ 0x21c
    }

    /* Leave the initialisation mode for the filter */
    CLEAR_BIT(can_ip->FMR, CAN_FMR_FINIT);
 8003524:	693b      	ldr	r3, [r7, #16]
 8003526:	f8d3 3200 	ldr.w	r3, [r3, #512]	@ 0x200
 800352a:	f023 0201 	bic.w	r2, r3, #1
 800352e:	693b      	ldr	r3, [r7, #16]
 8003530:	f8c3 2200 	str.w	r2, [r3, #512]	@ 0x200

    /* Return function status */
    return HAL_OK;
 8003534:	2300      	movs	r3, #0
 8003536:	e006      	b.n	8003546 <HAL_CAN_ConfigFilter+0x1aa>
  }
  else
  {
    /* Update error code */
    hcan->ErrorCode |= HAL_CAN_ERROR_NOT_INITIALIZED;
 8003538:	687b      	ldr	r3, [r7, #4]
 800353a:	6a5b      	ldr	r3, [r3, #36]	@ 0x24
 800353c:	f443 2280 	orr.w	r2, r3, #262144	@ 0x40000
 8003540:	687b      	ldr	r3, [r7, #4]
 8003542:	625a      	str	r2, [r3, #36]	@ 0x24

    return HAL_ERROR;
 8003544:	2301      	movs	r3, #1
  }
}
 8003546:	4618      	mov	r0, r3
 8003548:	371c      	adds	r7, #28
 800354a:	46bd      	mov	sp, r7
 800354c:	f85d 7b04 	ldr.w	r7, [sp], #4
 8003550:	4770      	bx	lr
 8003552:	bf00      	nop
 8003554:	40006400 	.word	0x40006400

08003558 <HAL_CAN_Start>:
  * @param  hcan pointer to an CAN_HandleTypeDef structure that contains
  *         the configuration information for the specified CAN.
  * @retval HAL status
  */
HAL_StatusTypeDef HAL_CAN_Start(CAN_HandleTypeDef *hcan)
{
 8003558:	b580      	push	{r7, lr}
 800355a:	b084      	sub	sp, #16
 800355c:	af00      	add	r7, sp, #0
 800355e:	6078      	str	r0, [r7, #4]
  uint32_t tickstart;

  if (hcan->State == HAL_CAN_STATE_READY)
 8003560:	687b      	ldr	r3, [r7, #4]
 8003562:	f893 3020 	ldrb.w	r3, [r3, #32]
 8003566:	b2db      	uxtb	r3, r3
 8003568:	2b01      	cmp	r3, #1
 800356a:	d12e      	bne.n	80035ca <HAL_CAN_Start+0x72>
  {
    /* Change CAN peripheral state */
    hcan->State = HAL_CAN_STATE_LISTENING;
 800356c:	687b      	ldr	r3, [r7, #4]
 800356e:	2202      	movs	r2, #2
 8003570:	f883 2020 	strb.w	r2, [r3, #32]

    /* Request leave initialisation */
    CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_INRQ);
 8003574:	687b      	ldr	r3, [r7, #4]
 8003576:	681b      	ldr	r3, [r3, #0]
 8003578:	681a      	ldr	r2, [r3, #0]
 800357a:	687b      	ldr	r3, [r7, #4]
 800357c:	681b      	ldr	r3, [r3, #0]
 800357e:	f022 0201 	bic.w	r2, r2, #1
 8003582:	601a      	str	r2, [r3, #0]

    /* Get tick */
    tickstart = HAL_GetTick();
 8003584:	f7ff fde0 	bl	8003148 <HAL_GetTick>
 8003588:	60f8      	str	r0, [r7, #12]

    /* Wait the acknowledge */
    while ((hcan->Instance->MSR & CAN_MSR_INAK) != 0U)
 800358a:	e012      	b.n	80035b2 <HAL_CAN_Start+0x5a>
    {
      /* Check for the Timeout */
      if ((HAL_GetTick() - tickstart) > CAN_TIMEOUT_VALUE)
 800358c:	f7ff fddc 	bl	8003148 <HAL_GetTick>
 8003590:	4602      	mov	r2, r0
 8003592:	68fb      	ldr	r3, [r7, #12]
 8003594:	1ad3      	subs	r3, r2, r3
 8003596:	2b0a      	cmp	r3, #10
 8003598:	d90b      	bls.n	80035b2 <HAL_CAN_Start+0x5a>
      {
        /* Update error code */
        hcan->ErrorCode |= HAL_CAN_ERROR_TIMEOUT;
 800359a:	687b      	ldr	r3, [r7, #4]
 800359c:	6a5b      	ldr	r3, [r3, #36]	@ 0x24
 800359e:	f443 3200 	orr.w	r2, r3, #131072	@ 0x20000
 80035a2:	687b      	ldr	r3, [r7, #4]
 80035a4:	625a      	str	r2, [r3, #36]	@ 0x24

        /* Change CAN state */
        hcan->State = HAL_CAN_STATE_ERROR;
 80035a6:	687b      	ldr	r3, [r7, #4]
 80035a8:	2205      	movs	r2, #5
 80035aa:	f883 2020 	strb.w	r2, [r3, #32]

        return HAL_ERROR;
 80035ae:	2301      	movs	r3, #1
 80035b0:	e012      	b.n	80035d8 <HAL_CAN_Start+0x80>
    while ((hcan->Instance->MSR & CAN_MSR_INAK) != 0U)
 80035b2:	687b      	ldr	r3, [r7, #4]
 80035b4:	681b      	ldr	r3, [r3, #0]
 80035b6:	685b      	ldr	r3, [r3, #4]
 80035b8:	f003 0301 	and.w	r3, r3, #1
 80035bc:	2b00      	cmp	r3, #0
 80035be:	d1e5      	bne.n	800358c <HAL_CAN_Start+0x34>
      }
    }

    /* Reset the CAN ErrorCode */
    hcan->ErrorCode = HAL_CAN_ERROR_NONE;
 80035c0:	687b      	ldr	r3, [r7, #4]
 80035c2:	2200      	movs	r2, #0
 80035c4:	625a      	str	r2, [r3, #36]	@ 0x24

    /* Return function status */
    return HAL_OK;
 80035c6:	2300      	movs	r3, #0
 80035c8:	e006      	b.n	80035d8 <HAL_CAN_Start+0x80>
  }
  else
  {
    /* Update error code */
    hcan->ErrorCode |= HAL_CAN_ERROR_NOT_READY;
 80035ca:	687b      	ldr	r3, [r7, #4]
 80035cc:	6a5b      	ldr	r3, [r3, #36]	@ 0x24
 80035ce:	f443 2200 	orr.w	r2, r3, #524288	@ 0x80000
 80035d2:	687b      	ldr	r3, [r7, #4]
 80035d4:	625a      	str	r2, [r3, #36]	@ 0x24

    return HAL_ERROR;
 80035d6:	2301      	movs	r3, #1
  }
}
 80035d8:	4618      	mov	r0, r3
 80035da:	3710      	adds	r7, #16
 80035dc:	46bd      	mov	sp, r7
 80035de:	bd80      	pop	{r7, pc}

080035e0 <HAL_CAN_Stop>:
  * @param  hcan pointer to an CAN_HandleTypeDef structure that contains
  *         the configuration information for the specified CAN.
  * @retval HAL status
  */
HAL_StatusTypeDef HAL_CAN_Stop(CAN_HandleTypeDef *hcan)
{
 80035e0:	b580      	push	{r7, lr}
 80035e2:	b084      	sub	sp, #16
 80035e4:	af00      	add	r7, sp, #0
 80035e6:	6078      	str	r0, [r7, #4]
  uint32_t tickstart;

  if (hcan->State == HAL_CAN_STATE_LISTENING)
 80035e8:	687b      	ldr	r3, [r7, #4]
 80035ea:	f893 3020 	ldrb.w	r3, [r3, #32]
 80035ee:	b2db      	uxtb	r3, r3
 80035f0:	2b02      	cmp	r3, #2
 80035f2:	d133      	bne.n	800365c <HAL_CAN_Stop+0x7c>
  {
    /* Request initialisation */
    SET_BIT(hcan->Instance->MCR, CAN_MCR_INRQ);
 80035f4:	687b      	ldr	r3, [r7, #4]
 80035f6:	681b      	ldr	r3, [r3, #0]
 80035f8:	681a      	ldr	r2, [r3, #0]
 80035fa:	687b      	ldr	r3, [r7, #4]
 80035fc:	681b      	ldr	r3, [r3, #0]
 80035fe:	f042 0201 	orr.w	r2, r2, #1
 8003602:	601a      	str	r2, [r3, #0]

    /* Get tick */
    tickstart = HAL_GetTick();
 8003604:	f7ff fda0 	bl	8003148 <HAL_GetTick>
 8003608:	60f8      	str	r0, [r7, #12]

    /* Wait the acknowledge */
    while ((hcan->Instance->MSR & CAN_MSR_INAK) == 0U)
 800360a:	e012      	b.n	8003632 <HAL_CAN_Stop+0x52>
    {
      /* Check for the Timeout */
      if ((HAL_GetTick() - tickstart) > CAN_TIMEOUT_VALUE)
 800360c:	f7ff fd9c 	bl	8003148 <HAL_GetTick>
 8003610:	4602      	mov	r2, r0
 8003612:	68fb      	ldr	r3, [r7, #12]
 8003614:	1ad3      	subs	r3, r2, r3
 8003616:	2b0a      	cmp	r3, #10
 8003618:	d90b      	bls.n	8003632 <HAL_CAN_Stop+0x52>
      {
        /* Update error code */
        hcan->ErrorCode |= HAL_CAN_ERROR_TIMEOUT;
 800361a:	687b      	ldr	r3, [r7, #4]
 800361c:	6a5b      	ldr	r3, [r3, #36]	@ 0x24
 800361e:	f443 3200 	orr.w	r2, r3, #131072	@ 0x20000
 8003622:	687b      	ldr	r3, [r7, #4]
 8003624:	625a      	str	r2, [r3, #36]	@ 0x24

        /* Change CAN state */
        hcan->State = HAL_CAN_STATE_ERROR;
 8003626:	687b      	ldr	r3, [r7, #4]
 8003628:	2205      	movs	r2, #5
 800362a:	f883 2020 	strb.w	r2, [r3, #32]

        return HAL_ERROR;
 800362e:	2301      	movs	r3, #1
 8003630:	e01b      	b.n	800366a <HAL_CAN_Stop+0x8a>
    while ((hcan->Instance->MSR & CAN_MSR_INAK) == 0U)
 8003632:	687b      	ldr	r3, [r7, #4]
 8003634:	681b      	ldr	r3, [r3, #0]
 8003636:	685b      	ldr	r3, [r3, #4]
 8003638:	f003 0301 	and.w	r3, r3, #1
 800363c:	2b00      	cmp	r3, #0
 800363e:	d0e5      	beq.n	800360c <HAL_CAN_Stop+0x2c>
      }
    }

    /* Exit from sleep mode */
    CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_SLEEP);
 8003640:	687b      	ldr	r3, [r7, #4]
 8003642:	681b      	ldr	r3, [r3, #0]
 8003644:	681a      	ldr	r2, [r3, #0]
 8003646:	687b      	ldr	r3, [r7, #4]
 8003648:	681b      	ldr	r3, [r3, #0]
 800364a:	f022 0202 	bic.w	r2, r2, #2
 800364e:	601a      	str	r2, [r3, #0]

    /* Change CAN peripheral state */
    hcan->State = HAL_CAN_STATE_READY;
 8003650:	687b      	ldr	r3, [r7, #4]
 8003652:	2201      	movs	r2, #1
 8003654:	f883 2020 	strb.w	r2, [r3, #32]

    /* Return function status */
    return HAL_OK;
 8003658:	2300      	movs	r3, #0
 800365a:	e006      	b.n	800366a <HAL_CAN_Stop+0x8a>
  }
  else
  {
    /* Update error code */
    hcan->ErrorCode |= HAL_CAN_ERROR_NOT_STARTED;
 800365c:	687b      	ldr	r3, [r7, #4]
 800365e:	6a5b      	ldr	r3, [r3, #36]	@ 0x24
 8003660:	f443 1280 	orr.w	r2, r3, #1048576	@ 0x100000
 8003664:	687b      	ldr	r3, [r7, #4]
 8003666:	625a      	str	r2, [r3, #36]	@ 0x24

    return HAL_ERROR;
 8003668:	2301      	movs	r3, #1
  }
}
 800366a:	4618      	mov	r0, r3
 800366c:	3710      	adds	r7, #16
 800366e:	46bd      	mov	sp, r7
 8003670:	bd80      	pop	{r7, pc}

08003672 <HAL_CAN_AddTxMessage>:
  *         This parameter can be a value of @arg CAN_Tx_Mailboxes.
  * @retval HAL status
  */
HAL_StatusTypeDef HAL_CAN_AddTxMessage(CAN_HandleTypeDef *hcan, const CAN_TxHeaderTypeDef *pHeader,
                                       const uint8_t aData[], uint32_t *pTxMailbox)
{
 8003672:	b480      	push	{r7}
 8003674:	b089      	sub	sp, #36	@ 0x24
 8003676:	af00      	add	r7, sp, #0
 8003678:	60f8      	str	r0, [r7, #12]
 800367a:	60b9      	str	r1, [r7, #8]
 800367c:	607a      	str	r2, [r7, #4]
 800367e:	603b      	str	r3, [r7, #0]
  uint32_t transmitmailbox;
  HAL_CAN_StateTypeDef state = hcan->State;
 8003680:	68fb      	ldr	r3, [r7, #12]
 8003682:	f893 3020 	ldrb.w	r3, [r3, #32]
 8003686:	77fb      	strb	r3, [r7, #31]
  uint32_t tsr = READ_REG(hcan->Instance->TSR);
 8003688:	68fb      	ldr	r3, [r7, #12]
 800368a:	681b      	ldr	r3, [r3, #0]
 800368c:	689b      	ldr	r3, [r3, #8]
 800368e:	61bb      	str	r3, [r7, #24]
  {
    assert_param(IS_CAN_EXTID(pHeader->ExtId));
  }
  assert_param(IS_FUNCTIONAL_STATE(pHeader->TransmitGlobalTime));

  if ((state == HAL_CAN_STATE_READY) ||
 8003690:	7ffb      	ldrb	r3, [r7, #31]
 8003692:	2b01      	cmp	r3, #1
 8003694:	d003      	beq.n	800369e <HAL_CAN_AddTxMessage+0x2c>
 8003696:	7ffb      	ldrb	r3, [r7, #31]
 8003698:	2b02      	cmp	r3, #2
 800369a:	f040 80ad 	bne.w	80037f8 <HAL_CAN_AddTxMessage+0x186>
      (state == HAL_CAN_STATE_LISTENING))
  {
    /* Check that all the Tx mailboxes are not full */
    if (((tsr & CAN_TSR_TME0) != 0U) ||
 800369e:	69bb      	ldr	r3, [r7, #24]
 80036a0:	f003 6380 	and.w	r3, r3, #67108864	@ 0x4000000
 80036a4:	2b00      	cmp	r3, #0
 80036a6:	d10a      	bne.n	80036be <HAL_CAN_AddTxMessage+0x4c>
        ((tsr & CAN_TSR_TME1) != 0U) ||
 80036a8:	69bb      	ldr	r3, [r7, #24]
 80036aa:	f003 6300 	and.w	r3, r3, #134217728	@ 0x8000000
    if (((tsr & CAN_TSR_TME0) != 0U) ||
 80036ae:	2b00      	cmp	r3, #0
 80036b0:	d105      	bne.n	80036be <HAL_CAN_AddTxMessage+0x4c>
        ((tsr & CAN_TSR_TME2) != 0U))
 80036b2:	69bb      	ldr	r3, [r7, #24]
 80036b4:	f003 5380 	and.w	r3, r3, #268435456	@ 0x10000000
        ((tsr & CAN_TSR_TME1) != 0U) ||
 80036b8:	2b00      	cmp	r3, #0
 80036ba:	f000 8095 	beq.w	80037e8 <HAL_CAN_AddTxMessage+0x176>
    {
      /* Select an empty transmit mailbox */
      transmitmailbox = (tsr & CAN_TSR_CODE) >> CAN_TSR_CODE_Pos;
 80036be:	69bb      	ldr	r3, [r7, #24]
 80036c0:	0e1b      	lsrs	r3, r3, #24
 80036c2:	f003 0303 	and.w	r3, r3, #3
 80036c6:	617b      	str	r3, [r7, #20]

      /* Store the Tx mailbox */
      *pTxMailbox = (uint32_t)1 << transmitmailbox;
 80036c8:	2201      	movs	r2, #1
 80036ca:	697b      	ldr	r3, [r7, #20]
 80036cc:	409a      	lsls	r2, r3
 80036ce:	683b      	ldr	r3, [r7, #0]
 80036d0:	601a      	str	r2, [r3, #0]

      /* Set up the Id */
      if (pHeader->IDE == CAN_ID_STD)
 80036d2:	68bb      	ldr	r3, [r7, #8]
 80036d4:	689b      	ldr	r3, [r3, #8]
 80036d6:	2b00      	cmp	r3, #0
 80036d8:	d10d      	bne.n	80036f6 <HAL_CAN_AddTxMessage+0x84>
      {
        hcan->Instance->sTxMailBox[transmitmailbox].TIR = ((pHeader->StdId << CAN_TI0R_STID_Pos) |
 80036da:	68bb      	ldr	r3, [r7, #8]
 80036dc:	681b      	ldr	r3, [r3, #0]
 80036de:	055a      	lsls	r2, r3, #21
                                                           pHeader->RTR);
 80036e0:	68bb      	ldr	r3, [r7, #8]
 80036e2:	68db      	ldr	r3, [r3, #12]
        hcan->Instance->sTxMailBox[transmitmailbox].TIR = ((pHeader->StdId << CAN_TI0R_STID_Pos) |
 80036e4:	68f9      	ldr	r1, [r7, #12]
 80036e6:	6809      	ldr	r1, [r1, #0]
 80036e8:	431a      	orrs	r2, r3
 80036ea:	697b      	ldr	r3, [r7, #20]
 80036ec:	3318      	adds	r3, #24
 80036ee:	011b      	lsls	r3, r3, #4
 80036f0:	440b      	add	r3, r1
 80036f2:	601a      	str	r2, [r3, #0]
 80036f4:	e00f      	b.n	8003716 <HAL_CAN_AddTxMessage+0xa4>
      }
      else
      {
        hcan->Instance->sTxMailBox[transmitmailbox].TIR = ((pHeader->ExtId << CAN_TI0R_EXID_Pos) |
 80036f6:	68bb      	ldr	r3, [r7, #8]
 80036f8:	685b      	ldr	r3, [r3, #4]
 80036fa:	00da      	lsls	r2, r3, #3
                                                           pHeader->IDE |
 80036fc:	68bb      	ldr	r3, [r7, #8]
 80036fe:	689b      	ldr	r3, [r3, #8]
        hcan->Instance->sTxMailBox[transmitmailbox].TIR = ((pHeader->ExtId << CAN_TI0R_EXID_Pos) |
 8003700:	431a      	orrs	r2, r3
                                                           pHeader->RTR);
 8003702:	68bb      	ldr	r3, [r7, #8]
 8003704:	68db      	ldr	r3, [r3, #12]
        hcan->Instance->sTxMailBox[transmitmailbox].TIR = ((pHeader->ExtId << CAN_TI0R_EXID_Pos) |
 8003706:	68f9      	ldr	r1, [r7, #12]
 8003708:	6809      	ldr	r1, [r1, #0]
                                                           pHeader->IDE |
 800370a:	431a      	orrs	r2, r3
        hcan->Instance->sTxMailBox[transmitmailbox].TIR = ((pHeader->ExtId << CAN_TI0R_EXID_Pos) |
 800370c:	697b      	ldr	r3, [r7, #20]
 800370e:	3318      	adds	r3, #24
 8003710:	011b      	lsls	r3, r3, #4
 8003712:	440b      	add	r3, r1
 8003714:	601a      	str	r2, [r3, #0]
      }

      /* Set up the DLC */
      hcan->Instance->sTxMailBox[transmitmailbox].TDTR = (pHeader->DLC);
 8003716:	68fb      	ldr	r3, [r7, #12]
 8003718:	6819      	ldr	r1, [r3, #0]
 800371a:	68bb      	ldr	r3, [r7, #8]
 800371c:	691a      	ldr	r2, [r3, #16]
 800371e:	697b      	ldr	r3, [r7, #20]
 8003720:	3318      	adds	r3, #24
 8003722:	011b      	lsls	r3, r3, #4
 8003724:	440b      	add	r3, r1
 8003726:	3304      	adds	r3, #4
 8003728:	601a      	str	r2, [r3, #0]

      /* Set up the Transmit Global Time mode */
      if (pHeader->TransmitGlobalTime == ENABLE)
 800372a:	68bb      	ldr	r3, [r7, #8]
 800372c:	7d1b      	ldrb	r3, [r3, #20]
 800372e:	2b01      	cmp	r3, #1
 8003730:	d111      	bne.n	8003756 <HAL_CAN_AddTxMessage+0xe4>
      {
        SET_BIT(hcan->Instance->sTxMailBox[transmitmailbox].TDTR, CAN_TDT0R_TGT);
 8003732:	68fb      	ldr	r3, [r7, #12]
 8003734:	681a      	ldr	r2, [r3, #0]
 8003736:	697b      	ldr	r3, [r7, #20]
 8003738:	3318      	adds	r3, #24
 800373a:	011b      	lsls	r3, r3, #4
 800373c:	4413      	add	r3, r2
 800373e:	3304      	adds	r3, #4
 8003740:	681b      	ldr	r3, [r3, #0]
 8003742:	68fa      	ldr	r2, [r7, #12]
 8003744:	6811      	ldr	r1, [r2, #0]
 8003746:	f443 7280 	orr.w	r2, r3, #256	@ 0x100
 800374a:	697b      	ldr	r3, [r7, #20]
 800374c:	3318      	adds	r3, #24
 800374e:	011b      	lsls	r3, r3, #4
 8003750:	440b      	add	r3, r1
 8003752:	3304      	adds	r3, #4
 8003754:	601a      	str	r2, [r3, #0]
      }

      /* Set up the data field */
      WRITE_REG(hcan->Instance->sTxMailBox[transmitmailbox].TDHR,
 8003756:	687b      	ldr	r3, [r7, #4]
 8003758:	3307      	adds	r3, #7
 800375a:	781b      	ldrb	r3, [r3, #0]
 800375c:	061a      	lsls	r2, r3, #24
 800375e:	687b      	ldr	r3, [r7, #4]
 8003760:	3306      	adds	r3, #6
 8003762:	781b      	ldrb	r3, [r3, #0]
 8003764:	041b      	lsls	r3, r3, #16
 8003766:	431a      	orrs	r2, r3
 8003768:	687b      	ldr	r3, [r7, #4]
 800376a:	3305      	adds	r3, #5
 800376c:	781b      	ldrb	r3, [r3, #0]
 800376e:	021b      	lsls	r3, r3, #8
 8003770:	4313      	orrs	r3, r2
 8003772:	687a      	ldr	r2, [r7, #4]
 8003774:	3204      	adds	r2, #4
 8003776:	7812      	ldrb	r2, [r2, #0]
 8003778:	4610      	mov	r0, r2
 800377a:	68fa      	ldr	r2, [r7, #12]
 800377c:	6811      	ldr	r1, [r2, #0]
 800377e:	ea43 0200 	orr.w	r2, r3, r0
 8003782:	697b      	ldr	r3, [r7, #20]
 8003784:	011b      	lsls	r3, r3, #4
 8003786:	440b      	add	r3, r1
 8003788:	f503 73c6 	add.w	r3, r3, #396	@ 0x18c
 800378c:	601a      	str	r2, [r3, #0]
                ((uint32_t)aData[7] << CAN_TDH0R_DATA7_Pos) |
                ((uint32_t)aData[6] << CAN_TDH0R_DATA6_Pos) |
                ((uint32_t)aData[5] << CAN_TDH0R_DATA5_Pos) |
                ((uint32_t)aData[4] << CAN_TDH0R_DATA4_Pos));
      WRITE_REG(hcan->Instance->sTxMailBox[transmitmailbox].TDLR,
 800378e:	687b      	ldr	r3, [r7, #4]
 8003790:	3303      	adds	r3, #3
 8003792:	781b      	ldrb	r3, [r3, #0]
 8003794:	061a      	lsls	r2, r3, #24
 8003796:	687b      	ldr	r3, [r7, #4]
 8003798:	3302      	adds	r3, #2
 800379a:	781b      	ldrb	r3, [r3, #0]
 800379c:	041b      	lsls	r3, r3, #16
 800379e:	431a      	orrs	r2, r3
 80037a0:	687b      	ldr	r3, [r7, #4]
 80037a2:	3301      	adds	r3, #1
 80037a4:	781b      	ldrb	r3, [r3, #0]
 80037a6:	021b      	lsls	r3, r3, #8
 80037a8:	4313      	orrs	r3, r2
 80037aa:	687a      	ldr	r2, [r7, #4]
 80037ac:	7812      	ldrb	r2, [r2, #0]
 80037ae:	4610      	mov	r0, r2
 80037b0:	68fa      	ldr	r2, [r7, #12]
 80037b2:	6811      	ldr	r1, [r2, #0]
 80037b4:	ea43 0200 	orr.w	r2, r3, r0
 80037b8:	697b      	ldr	r3, [r7, #20]
 80037ba:	011b      	lsls	r3, r3, #4
 80037bc:	440b      	add	r3, r1
 80037be:	f503 73c4 	add.w	r3, r3, #392	@ 0x188
 80037c2:	601a      	str	r2, [r3, #0]
                ((uint32_t)aData[2] << CAN_TDL0R_DATA2_Pos) |
                ((uint32_t)aData[1] << CAN_TDL0R_DATA1_Pos) |
                ((uint32_t)aData[0] << CAN_TDL0R_DATA0_Pos));

      /* Request transmission */
      SET_BIT(hcan->Instance->sTxMailBox[transmitmailbox].TIR, CAN_TI0R_TXRQ);
 80037c4:	68fb      	ldr	r3, [r7, #12]
 80037c6:	681a      	ldr	r2, [r3, #0]
 80037c8:	697b      	ldr	r3, [r7, #20]
 80037ca:	3318      	adds	r3, #24
 80037cc:	011b      	lsls	r3, r3, #4
 80037ce:	4413      	add	r3, r2
 80037d0:	681b      	ldr	r3, [r3, #0]
 80037d2:	68fa      	ldr	r2, [r7, #12]
 80037d4:	6811      	ldr	r1, [r2, #0]
 80037d6:	f043 0201 	orr.w	r2, r3, #1
 80037da:	697b      	ldr	r3, [r7, #20]
 80037dc:	3318      	adds	r3, #24
 80037de:	011b      	lsls	r3, r3, #4
 80037e0:	440b      	add	r3, r1
 80037e2:	601a      	str	r2, [r3, #0]

      /* Return function status */
      return HAL_OK;
 80037e4:	2300      	movs	r3, #0
 80037e6:	e00e      	b.n	8003806 <HAL_CAN_AddTxMessage+0x194>
    }
    else
    {
      /* Update error code */
      hcan->ErrorCode |= HAL_CAN_ERROR_PARAM;
 80037e8:	68fb      	ldr	r3, [r7, #12]
 80037ea:	6a5b      	ldr	r3, [r3, #36]	@ 0x24
 80037ec:	f443 1200 	orr.w	r2, r3, #2097152	@ 0x200000
 80037f0:	68fb      	ldr	r3, [r7, #12]
 80037f2:	625a      	str	r2, [r3, #36]	@ 0x24

      return HAL_ERROR;
 80037f4:	2301      	movs	r3, #1
 80037f6:	e006      	b.n	8003806 <HAL_CAN_AddTxMessage+0x194>
    }
  }
  else
  {
    /* Update error code */
    hcan->ErrorCode |= HAL_CAN_ERROR_NOT_INITIALIZED;
 80037f8:	68fb      	ldr	r3, [r7, #12]
 80037fa:	6a5b      	ldr	r3, [r3, #36]	@ 0x24
 80037fc:	f443 2280 	orr.w	r2, r3, #262144	@ 0x40000
 8003800:	68fb      	ldr	r3, [r7, #12]
 8003802:	625a      	str	r2, [r3, #36]	@ 0x24

    return HAL_ERROR;
 8003804:	2301      	movs	r3, #1
  }
}
 8003806:	4618      	mov	r0, r3
 8003808:	3724      	adds	r7, #36	@ 0x24
 800380a:	46bd      	mov	sp, r7
 800380c:	f85d 7b04 	ldr.w	r7, [sp], #4
 8003810:	4770      	bx	lr

08003812 <HAL_CAN_AbortTxRequest>:
  * @param  TxMailboxes List of the Tx Mailboxes to abort.
  *         This parameter can be any combination of @arg CAN_Tx_Mailboxes.
  * @retval HAL status
  */
HAL_StatusTypeDef HAL_CAN_AbortTxRequest(CAN_HandleTypeDef *hcan, uint32_t TxMailboxes)
{
 8003812:	b480      	push	{r7}
 8003814:	b085      	sub	sp, #20
 8003816:	af00      	add	r7, sp, #0
 8003818:	6078      	str	r0, [r7, #4]
 800381a:	6039      	str	r1, [r7, #0]
  HAL_CAN_StateTypeDef state = hcan->State;
 800381c:	687b      	ldr	r3, [r7, #4]
 800381e:	f893 3020 	ldrb.w	r3, [r3, #32]
 8003822:	73fb      	strb	r3, [r7, #15]

  /* Check function parameters */
  assert_param(IS_CAN_TX_MAILBOX_LIST(TxMailboxes));

  if ((state == HAL_CAN_STATE_READY) ||
 8003824:	7bfb      	ldrb	r3, [r7, #15]
 8003826:	2b01      	cmp	r3, #1
 8003828:	d002      	beq.n	8003830 <HAL_CAN_AbortTxRequest+0x1e>
 800382a:	7bfb      	ldrb	r3, [r7, #15]
 800382c:	2b02      	cmp	r3, #2
 800382e:	d128      	bne.n	8003882 <HAL_CAN_AbortTxRequest+0x70>
      (state == HAL_CAN_STATE_LISTENING))
  {
    /* Check Tx Mailbox 0 */
    if ((TxMailboxes & CAN_TX_MAILBOX0) != 0U)
 8003830:	683b      	ldr	r3, [r7, #0]
 8003832:	f003 0301 	and.w	r3, r3, #1
 8003836:	2b00      	cmp	r3, #0
 8003838:	d007      	beq.n	800384a <HAL_CAN_AbortTxRequest+0x38>
    {
      /* Add cancellation request for Tx Mailbox 0 */
      SET_BIT(hcan->Instance->TSR, CAN_TSR_ABRQ0);
 800383a:	687b      	ldr	r3, [r7, #4]
 800383c:	681b      	ldr	r3, [r3, #0]
 800383e:	689a      	ldr	r2, [r3, #8]
 8003840:	687b      	ldr	r3, [r7, #4]
 8003842:	681b      	ldr	r3, [r3, #0]
 8003844:	f042 0280 	orr.w	r2, r2, #128	@ 0x80
 8003848:	609a      	str	r2, [r3, #8]
    }

    /* Check Tx Mailbox 1 */
    if ((TxMailboxes & CAN_TX_MAILBOX1) != 0U)
 800384a:	683b      	ldr	r3, [r7, #0]
 800384c:	f003 0302 	and.w	r3, r3, #2
 8003850:	2b00      	cmp	r3, #0
 8003852:	d007      	beq.n	8003864 <HAL_CAN_AbortTxRequest+0x52>
    {
      /* Add cancellation request for Tx Mailbox 1 */
      SET_BIT(hcan->Instance->TSR, CAN_TSR_ABRQ1);
 8003854:	687b      	ldr	r3, [r7, #4]
 8003856:	681b      	ldr	r3, [r3, #0]
 8003858:	689a      	ldr	r2, [r3, #8]
 800385a:	687b      	ldr	r3, [r7, #4]
 800385c:	681b      	ldr	r3, [r3, #0]
 800385e:	f442 4200 	orr.w	r2, r2, #32768	@ 0x8000
 8003862:	609a      	str	r2, [r3, #8]
    }

    /* Check Tx Mailbox 2 */
    if ((TxMailboxes & CAN_TX_MAILBOX2) != 0U)
 8003864:	683b      	ldr	r3, [r7, #0]
 8003866:	f003 0304 	and.w	r3, r3, #4
 800386a:	2b00      	cmp	r3, #0
 800386c:	d007      	beq.n	800387e <HAL_CAN_AbortTxRequest+0x6c>
    {
      /* Add cancellation request for Tx Mailbox 2 */
      SET_BIT(hcan->Instance->TSR, CAN_TSR_ABRQ2);
 800386e:	687b      	ldr	r3, [r7, #4]
 8003870:	681b      	ldr	r3, [r3, #0]
 8003872:	689a      	ldr	r2, [r3, #8]
 8003874:	687b      	ldr	r3, [r7, #4]
 8003876:	681b      	ldr	r3, [r3, #0]
 8003878:	f442 0200 	orr.w	r2, r2, #8388608	@ 0x800000
 800387c:	609a      	str	r2, [r3, #8]
    }

    /* Return function status */
    return HAL_OK;
 800387e:	2300      	movs	r3, #0
 8003880:	e006      	b.n	8003890 <HAL_CAN_AbortTxRequest+0x7e>
  }
  else
  {
    /* Update error code */
    hcan->ErrorCode |= HAL_CAN_ERROR_NOT_INITIALIZED;
 8003882:	687b      	ldr	r3, [r7, #4]
 8003884:	6a5b      	ldr	r3, [r3, #36]	@ 0x24
 8003886:	f443 2280 	orr.w	r2, r3, #262144	@ 0x40000
 800388a:	687b      	ldr	r3, [r7, #4]
 800388c:	625a      	str	r2, [r3, #36]	@ 0x24

    return HAL_ERROR;
 800388e:	2301      	movs	r3, #1
  }
}
 8003890:	4618      	mov	r0, r3
 8003892:	3714      	adds	r7, #20
 8003894:	46bd      	mov	sp, r7
 8003896:	f85d 7b04 	ldr.w	r7, [sp], #4
 800389a:	4770      	bx	lr

0800389c <HAL_CAN_IsTxMessagePending>:
  *          - 0 : No pending transmission request on any selected Tx Mailboxes.
  *          - 1 : Pending transmission request on at least one of the selected
  *                Tx Mailbox.
  */
uint32_t HAL_CAN_IsTxMessagePending(const CAN_HandleTypeDef *hcan, uint32_t TxMailboxes)
{
 800389c:	b480      	push	{r7}
 800389e:	b085      	sub	sp, #20
 80038a0:	af00      	add	r7, sp, #0
 80038a2:	6078      	str	r0, [r7, #4]
 80038a4:	6039      	str	r1, [r7, #0]
  uint32_t status = 0U;
 80038a6:	2300      	movs	r3, #0
 80038a8:	60fb      	str	r3, [r7, #12]
  HAL_CAN_StateTypeDef state = hcan->State;
 80038aa:	687b      	ldr	r3, [r7, #4]
 80038ac:	f893 3020 	ldrb.w	r3, [r3, #32]
 80038b0:	72fb      	strb	r3, [r7, #11]

  /* Check function parameters */
  assert_param(IS_CAN_TX_MAILBOX_LIST(TxMailboxes));

  if ((state == HAL_CAN_STATE_READY) ||
 80038b2:	7afb      	ldrb	r3, [r7, #11]
 80038b4:	2b01      	cmp	r3, #1
 80038b6:	d002      	beq.n	80038be <HAL_CAN_IsTxMessagePending+0x22>
 80038b8:	7afb      	ldrb	r3, [r7, #11]
 80038ba:	2b02      	cmp	r3, #2
 80038bc:	d10b      	bne.n	80038d6 <HAL_CAN_IsTxMessagePending+0x3a>
      (state == HAL_CAN_STATE_LISTENING))
  {
    /* Check pending transmission request on the selected Tx Mailboxes */
    if ((hcan->Instance->TSR & (TxMailboxes << CAN_TSR_TME0_Pos)) != (TxMailboxes << CAN_TSR_TME0_Pos))
 80038be:	687b      	ldr	r3, [r7, #4]
 80038c0:	681b      	ldr	r3, [r3, #0]
 80038c2:	689a      	ldr	r2, [r3, #8]
 80038c4:	683b      	ldr	r3, [r7, #0]
 80038c6:	069b      	lsls	r3, r3, #26
 80038c8:	401a      	ands	r2, r3
 80038ca:	683b      	ldr	r3, [r7, #0]
 80038cc:	069b      	lsls	r3, r3, #26
 80038ce:	429a      	cmp	r2, r3
 80038d0:	d001      	beq.n	80038d6 <HAL_CAN_IsTxMessagePending+0x3a>
    {
      status = 1U;
 80038d2:	2301      	movs	r3, #1
 80038d4:	60fb      	str	r3, [r7, #12]
    }
  }

  /* Return status */
  return status;
 80038d6:	68fb      	ldr	r3, [r7, #12]
}
 80038d8:	4618      	mov	r0, r3
 80038da:	3714      	adds	r7, #20
 80038dc:	46bd      	mov	sp, r7
 80038de:	f85d 7b04 	ldr.w	r7, [sp], #4
 80038e2:	4770      	bx	lr

080038e4 <HAL_CAN_GetRxMessage>:
  * @param  aData array where the payload of the Rx frame will be stored.
  * @retval HAL status
  */
HAL_StatusTypeDef HAL_CAN_GetRxMessage(CAN_HandleTypeDef *hcan, uint32_t RxFifo,
                                       CAN_RxHeaderTypeDef *pHeader, uint8_t aData[])
{
 80038e4:	b480      	push	{r7}
 80038e6:	b087      	sub	sp, #28
 80038e8:	af00      	add	r7, sp, #0
 80038ea:	60f8      	str	r0, [r7, #12]
 80038ec:	60b9      	str	r1, [r7, #8]
 80038ee:	607a      	str	r2, [r7, #4]
 80038f0:	603b      	str	r3, [r7, #0]
  HAL_CAN_StateTypeDef state = hcan->State;
 80038f2:	68fb      	ldr	r3, [r7, #12]
 80038f4:	f893 3020 	ldrb.w	r3, [r3, #32]
 80038f8:	75fb      	strb	r3, [r7, #23]

  assert_param(IS_CAN_RX_FIFO(RxFifo));

  if ((state == HAL_CAN_STATE_READY) ||
 80038fa:	7dfb      	ldrb	r3, [r7, #23]
 80038fc:	2b01      	cmp	r3, #1
 80038fe:	d003      	beq.n	8003908 <HAL_CAN_GetRxMessage+0x24>
 8003900:	7dfb      	ldrb	r3, [r7, #23]
 8003902:	2b02      	cmp	r3, #2
 8003904:	f040 8103 	bne.w	8003b0e <HAL_CAN_GetRxMessage+0x22a>
      (state == HAL_CAN_STATE_LISTENING))
  {
    /* Check the Rx FIFO */
    if (RxFifo == CAN_RX_FIFO0) /* Rx element is assigned to Rx FIFO 0 */
 8003908:	68bb      	ldr	r3, [r7, #8]
 800390a:	2b00      	cmp	r3, #0
 800390c:	d10e      	bne.n	800392c <HAL_CAN_GetRxMessage+0x48>
    {
      /* Check that the Rx FIFO 0 is not empty */
      if ((hcan->Instance->RF0R & CAN_RF0R_FMP0) == 0U)
 800390e:	68fb      	ldr	r3, [r7, #12]
 8003910:	681b      	ldr	r3, [r3, #0]
 8003912:	68db      	ldr	r3, [r3, #12]
 8003914:	f003 0303 	and.w	r3, r3, #3
 8003918:	2b00      	cmp	r3, #0
 800391a:	d116      	bne.n	800394a <HAL_CAN_GetRxMessage+0x66>
      {
        /* Update error code */
        hcan->ErrorCode |= HAL_CAN_ERROR_PARAM;
 800391c:	68fb      	ldr	r3, [r7, #12]
 800391e:	6a5b      	ldr	r3, [r3, #36]	@ 0x24
 8003920:	f443 1200 	orr.w	r2, r3, #2097152	@ 0x200000
 8003924:	68fb      	ldr	r3, [r7, #12]
 8003926:	625a      	str	r2, [r3, #36]	@ 0x24

        return HAL_ERROR;
 8003928:	2301      	movs	r3, #1
 800392a:	e0f7      	b.n	8003b1c <HAL_CAN_GetRxMessage+0x238>
      }
    }
    else /* Rx element is assigned to Rx FIFO 1 */
    {
      /* Check that the Rx FIFO 1 is not empty */
      if ((hcan->Instance->RF1R & CAN_RF1R_FMP1) == 0U)
 800392c:	68fb      	ldr	r3, [r7, #12]
 800392e:	681b      	ldr	r3, [r3, #0]
 8003930:	691b      	ldr	r3, [r3, #16]
 8003932:	f003 0303 	and.w	r3, r3, #3
 8003936:	2b00      	cmp	r3, #0
 8003938:	d107      	bne.n	800394a <HAL_CAN_GetRxMessage+0x66>
      {
        /* Update error code */
        hcan->ErrorCode |= HAL_CAN_ERROR_PARAM;
 800393a:	68fb      	ldr	r3, [r7, #12]
 800393c:	6a5b      	ldr	r3, [r3, #36]	@ 0x24
 800393e:	f443 1200 	orr.w	r2, r3, #2097152	@ 0x200000
 8003942:	68fb      	ldr	r3, [r7, #12]
 8003944:	625a      	str	r2, [r3, #36]	@ 0x24

        return HAL_ERROR;
 8003946:	2301      	movs	r3, #1
 8003948:	e0e8      	b.n	8003b1c <HAL_CAN_GetRxMessage+0x238>
      }
    }

    /* Get the header */
    pHeader->IDE = CAN_RI0R_IDE & hcan->Instance->sFIFOMailBox[RxFifo].RIR;
 800394a:	68fb      	ldr	r3, [r7, #12]
 800394c:	681a      	ldr	r2, [r3, #0]
 800394e:	68bb      	ldr	r3, [r7, #8]
 8003950:	331b      	adds	r3, #27
 8003952:	011b      	lsls	r3, r3, #4
 8003954:	4413      	add	r3, r2
 8003956:	681b      	ldr	r3, [r3, #0]
 8003958:	f003 0204 	and.w	r2, r3, #4
 800395c:	687b      	ldr	r3, [r7, #4]
 800395e:	609a      	str	r2, [r3, #8]
    if (pHeader->IDE == CAN_ID_STD)
 8003960:	687b      	ldr	r3, [r7, #4]
 8003962:	689b      	ldr	r3, [r3, #8]
 8003964:	2b00      	cmp	r3, #0
 8003966:	d10c      	bne.n	8003982 <HAL_CAN_GetRxMessage+0x9e>
    {
      pHeader->StdId = (CAN_RI0R_STID & hcan->Instance->sFIFOMailBox[RxFifo].RIR) >> CAN_TI0R_STID_Pos;
 8003968:	68fb      	ldr	r3, [r7, #12]
 800396a:	681a      	ldr	r2, [r3, #0]
 800396c:	68bb      	ldr	r3, [r7, #8]
 800396e:	331b      	adds	r3, #27
 8003970:	011b      	lsls	r3, r3, #4
 8003972:	4413      	add	r3, r2
 8003974:	681b      	ldr	r3, [r3, #0]
 8003976:	0d5b      	lsrs	r3, r3, #21
 8003978:	f3c3 020a 	ubfx	r2, r3, #0, #11
 800397c:	687b      	ldr	r3, [r7, #4]
 800397e:	601a      	str	r2, [r3, #0]
 8003980:	e00b      	b.n	800399a <HAL_CAN_GetRxMessage+0xb6>
    }
    else
    {
      pHeader->ExtId = ((CAN_RI0R_EXID | CAN_RI0R_STID) &
                        hcan->Instance->sFIFOMailBox[RxFifo].RIR) >> CAN_RI0R_EXID_Pos;
 8003982:	68fb      	ldr	r3, [r7, #12]
 8003984:	681a      	ldr	r2, [r3, #0]
 8003986:	68bb      	ldr	r3, [r7, #8]
 8003988:	331b      	adds	r3, #27
 800398a:	011b      	lsls	r3, r3, #4
 800398c:	4413      	add	r3, r2
 800398e:	681b      	ldr	r3, [r3, #0]
 8003990:	08db      	lsrs	r3, r3, #3
 8003992:	f023 4260 	bic.w	r2, r3, #3758096384	@ 0xe0000000
      pHeader->ExtId = ((CAN_RI0R_EXID | CAN_RI0R_STID) &
 8003996:	687b      	ldr	r3, [r7, #4]
 8003998:	605a      	str	r2, [r3, #4]
    }
    pHeader->RTR = (CAN_RI0R_RTR & hcan->Instance->sFIFOMailBox[RxFifo].RIR);
 800399a:	68fb      	ldr	r3, [r7, #12]
 800399c:	681a      	ldr	r2, [r3, #0]
 800399e:	68bb      	ldr	r3, [r7, #8]
 80039a0:	331b      	adds	r3, #27
 80039a2:	011b      	lsls	r3, r3, #4
 80039a4:	4413      	add	r3, r2
 80039a6:	681b      	ldr	r3, [r3, #0]
 80039a8:	f003 0202 	and.w	r2, r3, #2
 80039ac:	687b      	ldr	r3, [r7, #4]
 80039ae:	60da      	str	r2, [r3, #12]
    if (((CAN_RDT0R_DLC & hcan->Instance->sFIFOMailBox[RxFifo].RDTR) >> CAN_RDT0R_DLC_Pos) >= 8U)
 80039b0:	68fb      	ldr	r3, [r7, #12]
 80039b2:	681a      	ldr	r2, [r3, #0]
 80039b4:	68bb      	ldr	r3, [r7, #8]
 80039b6:	331b      	adds	r3, #27
 80039b8:	011b      	lsls	r3, r3, #4
 80039ba:	4413      	add	r3, r2
 80039bc:	3304      	adds	r3, #4
 80039be:	681b      	ldr	r3, [r3, #0]
 80039c0:	f003 0308 	and.w	r3, r3, #8
 80039c4:	2b00      	cmp	r3, #0
 80039c6:	d003      	beq.n	80039d0 <HAL_CAN_GetRxMessage+0xec>
    {
      /* Truncate DLC to 8 if received field is over range */
      pHeader->DLC = 8U;
 80039c8:	687b      	ldr	r3, [r7, #4]
 80039ca:	2208      	movs	r2, #8
 80039cc:	611a      	str	r2, [r3, #16]
 80039ce:	e00b      	b.n	80039e8 <HAL_CAN_GetRxMessage+0x104>
    }
    else
    {
      pHeader->DLC = (CAN_RDT0R_DLC & hcan->Instance->sFIFOMailBox[RxFifo].RDTR) >> CAN_RDT0R_DLC_Pos;
 80039d0:	68fb      	ldr	r3, [r7, #12]
 80039d2:	681a      	ldr	r2, [r3, #0]
 80039d4:	68bb      	ldr	r3, [r7, #8]
 80039d6:	331b      	adds	r3, #27
 80039d8:	011b      	lsls	r3, r3, #4
 80039da:	4413      	add	r3, r2
 80039dc:	3304      	adds	r3, #4
 80039de:	681b      	ldr	r3, [r3, #0]
 80039e0:	f003 020f 	and.w	r2, r3, #15
 80039e4:	687b      	ldr	r3, [r7, #4]
 80039e6:	611a      	str	r2, [r3, #16]
    }
    pHeader->FilterMatchIndex = (CAN_RDT0R_FMI & hcan->Instance->sFIFOMailBox[RxFifo].RDTR) >> CAN_RDT0R_FMI_Pos;
 80039e8:	68fb      	ldr	r3, [r7, #12]
 80039ea:	681a      	ldr	r2, [r3, #0]
 80039ec:	68bb      	ldr	r3, [r7, #8]
 80039ee:	331b      	adds	r3, #27
 80039f0:	011b      	lsls	r3, r3, #4
 80039f2:	4413      	add	r3, r2
 80039f4:	3304      	adds	r3, #4
 80039f6:	681b      	ldr	r3, [r3, #0]
 80039f8:	0a1b      	lsrs	r3, r3, #8
 80039fa:	b2da      	uxtb	r2, r3
 80039fc:	687b      	ldr	r3, [r7, #4]
 80039fe:	619a      	str	r2, [r3, #24]
    pHeader->Timestamp = (CAN_RDT0R_TIME & hcan->Instance->sFIFOMailBox[RxFifo].RDTR) >> CAN_RDT0R_TIME_Pos;
 8003a00:	68fb      	ldr	r3, [r7, #12]
 8003a02:	681a      	ldr	r2, [r3, #0]
 8003a04:	68bb      	ldr	r3, [r7, #8]
 8003a06:	331b      	adds	r3, #27
 8003a08:	011b      	lsls	r3, r3, #4
 8003a0a:	4413      	add	r3, r2
 8003a0c:	3304      	adds	r3, #4
 8003a0e:	681b      	ldr	r3, [r3, #0]
 8003a10:	0c1b      	lsrs	r3, r3, #16
 8003a12:	b29a      	uxth	r2, r3
 8003a14:	687b      	ldr	r3, [r7, #4]
 8003a16:	615a      	str	r2, [r3, #20]

    /* Get the data */
    aData[0] = (uint8_t)((CAN_RDL0R_DATA0 & hcan->Instance->sFIFOMailBox[RxFifo].RDLR) >> CAN_RDL0R_DATA0_Pos);
 8003a18:	68fb      	ldr	r3, [r7, #12]
 8003a1a:	681a      	ldr	r2, [r3, #0]
 8003a1c:	68bb      	ldr	r3, [r7, #8]
 8003a1e:	011b      	lsls	r3, r3, #4
 8003a20:	4413      	add	r3, r2
 8003a22:	f503 73dc 	add.w	r3, r3, #440	@ 0x1b8
 8003a26:	681b      	ldr	r3, [r3, #0]
 8003a28:	b2da      	uxtb	r2, r3
 8003a2a:	683b      	ldr	r3, [r7, #0]
 8003a2c:	701a      	strb	r2, [r3, #0]
    aData[1] = (uint8_t)((CAN_RDL0R_DATA1 & hcan->Instance->sFIFOMailBox[RxFifo].RDLR) >> CAN_RDL0R_DATA1_Pos);
 8003a2e:	68fb      	ldr	r3, [r7, #12]
 8003a30:	681a      	ldr	r2, [r3, #0]
 8003a32:	68bb      	ldr	r3, [r7, #8]
 8003a34:	011b      	lsls	r3, r3, #4
 8003a36:	4413      	add	r3, r2
 8003a38:	f503 73dc 	add.w	r3, r3, #440	@ 0x1b8
 8003a3c:	681b      	ldr	r3, [r3, #0]
 8003a3e:	0a1a      	lsrs	r2, r3, #8
 8003a40:	683b      	ldr	r3, [r7, #0]
 8003a42:	3301      	adds	r3, #1
 8003a44:	b2d2      	uxtb	r2, r2
 8003a46:	701a      	strb	r2, [r3, #0]
    aData[2] = (uint8_t)((CAN_RDL0R_DATA2 & hcan->Instance->sFIFOMailBox[RxFifo].RDLR) >> CAN_RDL0R_DATA2_Pos);
 8003a48:	68fb      	ldr	r3, [r7, #12]
 8003a4a:	681a      	ldr	r2, [r3, #0]
 8003a4c:	68bb      	ldr	r3, [r7, #8]
 8003a4e:	011b      	lsls	r3, r3, #4
 8003a50:	4413      	add	r3, r2
 8003a52:	f503 73dc 	add.w	r3, r3, #440	@ 0x1b8
 8003a56:	681b      	ldr	r3, [r3, #0]
 8003a58:	0c1a      	lsrs	r2, r3, #16
 8003a5a:	683b      	ldr	r3, [r7, #0]
 8003a5c:	3302      	adds	r3, #2
 8003a5e:	b2d2      	uxtb	r2, r2
 8003a60:	701a      	strb	r2, [r3, #0]
    aData[3] = (uint8_t)((CAN_RDL0R_DATA3 & hcan->Instance->sFIFOMailBox[RxFifo].RDLR) >> CAN_RDL0R_DATA3_Pos);
 8003a62:	68fb      	ldr	r3, [r7, #12]
 8003a64:	681a      	ldr	r2, [r3, #0]
 8003a66:	68bb      	ldr	r3, [r7, #8]
 8003a68:	011b      	lsls	r3, r3, #4
 8003a6a:	4413      	add	r3, r2
 8003a6c:	f503 73dc 	add.w	r3, r3, #440	@ 0x1b8
 8003a70:	681b      	ldr	r3, [r3, #0]
 8003a72:	0e1a      	lsrs	r2, r3, #24
 8003a74:	683b      	ldr	r3, [r7, #0]
 8003a76:	3303      	adds	r3, #3
 8003a78:	b2d2      	uxtb	r2, r2
 8003a7a:	701a      	strb	r2, [r3, #0]
    aData[4] = (uint8_t)((CAN_RDH0R_DATA4 & hcan->Instance->sFIFOMailBox[RxFifo].RDHR) >> CAN_RDH0R_DATA4_Pos);
 8003a7c:	68fb      	ldr	r3, [r7, #12]
 8003a7e:	681a      	ldr	r2, [r3, #0]
 8003a80:	68bb      	ldr	r3, [r7, #8]
 8003a82:	011b      	lsls	r3, r3, #4
 8003a84:	4413      	add	r3, r2
 8003a86:	f503 73de 	add.w	r3, r3, #444	@ 0x1bc
 8003a8a:	681a      	ldr	r2, [r3, #0]
 8003a8c:	683b      	ldr	r3, [r7, #0]
 8003a8e:	3304      	adds	r3, #4
 8003a90:	b2d2      	uxtb	r2, r2
 8003a92:	701a      	strb	r2, [r3, #0]
    aData[5] = (uint8_t)((CAN_RDH0R_DATA5 & hcan->Instance->sFIFOMailBox[RxFifo].RDHR) >> CAN_RDH0R_DATA5_Pos);
 8003a94:	68fb      	ldr	r3, [r7, #12]
 8003a96:	681a      	ldr	r2, [r3, #0]
 8003a98:	68bb      	ldr	r3, [r7, #8]
 8003a9a:	011b      	lsls	r3, r3, #4
 8003a9c:	4413      	add	r3, r2
 8003a9e:	f503 73de 	add.w	r3, r3, #444	@ 0x1bc
 8003aa2:	681b      	ldr	r3, [r3, #0]
 8003aa4:	0a1a      	lsrs	r2, r3, #8
 8003aa6:	683b      	ldr	r3, [r7, #0]
 8003aa8:	3305      	adds	r3, #5
 8003aaa:	b2d2      	uxtb	r2, r2
 8003aac:	701a      	strb	r2, [r3, #0]
    aData[6] = (uint8_t)((CAN_RDH0R_DATA6 & hcan->Instance->sFIFOMailBox[RxFifo].RDHR) >> CAN_RDH0R_DATA6_Pos);
 8003aae:	68fb      	ldr	r3, [r7, #12]
 8003ab0:	681a      	ldr	r2, [r3, #0]
 8003ab2:	68bb      	ldr	r3, [r7, #8]
 8003ab4:	011b      	lsls	r3, r3, #4
 8003ab6:	4413      	add	r3, r2
 8003ab8:	f503 73de 	add.w	r3, r3, #444	@ 0x1bc
 8003abc:	681b      	ldr	r3, [r3, #0]
 8003abe:	0c1a      	lsrs	r2, r3, #16
 8003ac0:	683b      	ldr	r3, [r7, #0]
 8003ac2:	3306      	adds	r3, #6
 8003ac4:	b2d2      	uxtb	r2, r2
 8003ac6:	701a      	strb	r2, [r3, #0]
    aData[7] = (uint8_t)((CAN_RDH0R_DATA7 & hcan->Instance->sFIFOMailBox[RxFifo].RDHR) >> CAN_RDH0R_DATA7_Pos);
 8003ac8:	68fb      	ldr	r3, [r7, #12]
 8003aca:	681a      	ldr	r2, [r3, #0]
 8003acc:	68bb      	ldr	r3, [r7, #8]
 8003ace:	011b      	lsls	r3, r3, #4
 8003ad0:	4413      	add	r3, r2
 8003ad2:	f503 73de 	add.w	r3, r3, #444	@ 0x1bc
 8003ad6:	681b      	ldr	r3, [r3, #0]
 8003ad8:	0e1a      	lsrs	r2, r3, #24
 8003ada:	683b      	ldr	r3, [r7, #0]
 8003adc:	3307      	adds	r3, #7
 8003ade:	b2d2      	uxtb	r2, r2
 8003ae0:	701a      	strb	r2, [r3, #0]

    /* Release the FIFO */
    if (RxFifo == CAN_RX_FIFO0) /* Rx element is assigned to Rx FIFO 0 */
 8003ae2:	68bb      	ldr	r3, [r7, #8]
 8003ae4:	2b00      	cmp	r3, #0
 8003ae6:	d108      	bne.n	8003afa <HAL_CAN_GetRxMessage+0x216>
    {
      /* Release RX FIFO 0 */
      SET_BIT(hcan->Instance->RF0R, CAN_RF0R_RFOM0);
 8003ae8:	68fb      	ldr	r3, [r7, #12]
 8003aea:	681b      	ldr	r3, [r3, #0]
 8003aec:	68da      	ldr	r2, [r3, #12]
 8003aee:	68fb      	ldr	r3, [r7, #12]
 8003af0:	681b      	ldr	r3, [r3, #0]
 8003af2:	f042 0220 	orr.w	r2, r2, #32
 8003af6:	60da      	str	r2, [r3, #12]
 8003af8:	e007      	b.n	8003b0a <HAL_CAN_GetRxMessage+0x226>
    }
    else /* Rx element is assigned to Rx FIFO 1 */
    {
      /* Release RX FIFO 1 */
      SET_BIT(hcan->Instance->RF1R, CAN_RF1R_RFOM1);
 8003afa:	68fb      	ldr	r3, [r7, #12]
 8003afc:	681b      	ldr	r3, [r3, #0]
 8003afe:	691a      	ldr	r2, [r3, #16]
 8003b00:	68fb      	ldr	r3, [r7, #12]
 8003b02:	681b      	ldr	r3, [r3, #0]
 8003b04:	f042 0220 	orr.w	r2, r2, #32
 8003b08:	611a      	str	r2, [r3, #16]
    }

    /* Return function status */
    return HAL_OK;
 8003b0a:	2300      	movs	r3, #0
 8003b0c:	e006      	b.n	8003b1c <HAL_CAN_GetRxMessage+0x238>
  }
  else
  {
    /* Update error code */
    hcan->ErrorCode |= HAL_CAN_ERROR_NOT_INITIALIZED;
 8003b0e:	68fb      	ldr	r3, [r7, #12]
 8003b10:	6a5b      	ldr	r3, [r3, #36]	@ 0x24
 8003b12:	f443 2280 	orr.w	r2, r3, #262144	@ 0x40000
 8003b16:	68fb      	ldr	r3, [r7, #12]
 8003b18:	625a      	str	r2, [r3, #36]	@ 0x24

    return HAL_ERROR;
 8003b1a:	2301      	movs	r3, #1
  }
}
 8003b1c:	4618      	mov	r0, r3
 8003b1e:	371c      	adds	r7, #28
 8003b20:	46bd      	mov	sp, r7
 8003b22:	f85d 7b04 	ldr.w	r7, [sp], #4
 8003b26:	4770      	bx	lr

08003b28 <HAL_CAN_ActivateNotification>:
  * @param  ActiveITs indicates which interrupts will be enabled.
  *         This parameter can be any combination of @arg CAN_Interrupts.
  * @retval HAL status
  */
HAL_StatusTypeDef HAL_CAN_ActivateNotification(CAN_HandleTypeDef *hcan, uint32_t ActiveITs)
{
 8003b28:	b480      	push	{r7}
 8003b2a:	b085      	sub	sp, #20
 8003b2c:	af00      	add	r7, sp, #0
 8003b2e:	6078      	str	r0, [r7, #4]
 8003b30:	6039      	str	r1, [r7, #0]
  HAL_CAN_StateTypeDef state = hcan->State;
 8003b32:	687b      	ldr	r3, [r7, #4]
 8003b34:	f893 3020 	ldrb.w	r3, [r3, #32]
 8003b38:	73fb      	strb	r3, [r7, #15]

  /* Check function parameters */
  assert_param(IS_CAN_IT(ActiveITs));

  if ((state == HAL_CAN_STATE_READY) ||
 8003b3a:	7bfb      	ldrb	r3, [r7, #15]
 8003b3c:	2b01      	cmp	r3, #1
 8003b3e:	d002      	beq.n	8003b46 <HAL_CAN_ActivateNotification+0x1e>
 8003b40:	7bfb      	ldrb	r3, [r7, #15]
 8003b42:	2b02      	cmp	r3, #2
 8003b44:	d109      	bne.n	8003b5a <HAL_CAN_ActivateNotification+0x32>
      (state == HAL_CAN_STATE_LISTENING))
  {
    /* Enable the selected interrupts */
    __HAL_CAN_ENABLE_IT(hcan, ActiveITs);
 8003b46:	687b      	ldr	r3, [r7, #4]
 8003b48:	681b      	ldr	r3, [r3, #0]
 8003b4a:	6959      	ldr	r1, [r3, #20]
 8003b4c:	687b      	ldr	r3, [r7, #4]
 8003b4e:	681b      	ldr	r3, [r3, #0]
 8003b50:	683a      	ldr	r2, [r7, #0]
 8003b52:	430a      	orrs	r2, r1
 8003b54:	615a      	str	r2, [r3, #20]

    /* Return function status */
    return HAL_OK;
 8003b56:	2300      	movs	r3, #0
 8003b58:	e006      	b.n	8003b68 <HAL_CAN_ActivateNotification+0x40>
  }
  else
  {
    /* Update error code */
    hcan->ErrorCode |= HAL_CAN_ERROR_NOT_INITIALIZED;
 8003b5a:	687b      	ldr	r3, [r7, #4]
 8003b5c:	6a5b      	ldr	r3, [r3, #36]	@ 0x24
 8003b5e:	f443 2280 	orr.w	r2, r3, #262144	@ 0x40000
 8003b62:	687b      	ldr	r3, [r7, #4]
 8003b64:	625a      	str	r2, [r3, #36]	@ 0x24

    return HAL_ERROR;
 8003b66:	2301      	movs	r3, #1
  }
}
 8003b68:	4618      	mov	r0, r3
 8003b6a:	3714      	adds	r7, #20
 8003b6c:	46bd      	mov	sp, r7
 8003b6e:	f85d 7b04 	ldr.w	r7, [sp], #4
 8003b72:	4770      	bx	lr

08003b74 <HAL_CAN_IRQHandler>:
  * @param  hcan pointer to a CAN_HandleTypeDef structure that contains
  *         the configuration information for the specified CAN.
  * @retval None
  */
void HAL_CAN_IRQHandler(CAN_HandleTypeDef *hcan)
{
 8003b74:	b580      	push	{r7, lr}
 8003b76:	b08a      	sub	sp, #40	@ 0x28
 8003b78:	af00      	add	r7, sp, #0
 8003b7a:	6078      	str	r0, [r7, #4]
  uint32_t errorcode = HAL_CAN_ERROR_NONE;
 8003b7c:	2300      	movs	r3, #0
 8003b7e:	627b      	str	r3, [r7, #36]	@ 0x24
  uint32_t interrupts = READ_REG(hcan->Instance->IER);
 8003b80:	687b      	ldr	r3, [r7, #4]
 8003b82:	681b      	ldr	r3, [r3, #0]
 8003b84:	695b      	ldr	r3, [r3, #20]
 8003b86:	623b      	str	r3, [r7, #32]
  uint32_t msrflags = READ_REG(hcan->Instance->MSR);
 8003b88:	687b      	ldr	r3, [r7, #4]
 8003b8a:	681b      	ldr	r3, [r3, #0]
 8003b8c:	685b      	ldr	r3, [r3, #4]
 8003b8e:	61fb      	str	r3, [r7, #28]
  uint32_t tsrflags = READ_REG(hcan->Instance->TSR);
 8003b90:	687b      	ldr	r3, [r7, #4]
 8003b92:	681b      	ldr	r3, [r3, #0]
 8003b94:	689b      	ldr	r3, [r3, #8]
 8003b96:	61bb      	str	r3, [r7, #24]
  uint32_t rf0rflags = READ_REG(hcan->Instance->RF0R);
 8003b98:	687b      	ldr	r3, [r7, #4]
 8003b9a:	681b      	ldr	r3, [r3, #0]
 8003b9c:	68db      	ldr	r3, [r3, #12]
 8003b9e:	617b      	str	r3, [r7, #20]
  uint32_t rf1rflags = READ_REG(hcan->Instance->RF1R);
 8003ba0:	687b      	ldr	r3, [r7, #4]
 8003ba2:	681b      	ldr	r3, [r3, #0]
 8003ba4:	691b      	ldr	r3, [r3, #16]
 8003ba6:	613b      	str	r3, [r7, #16]
  uint32_t esrflags = READ_REG(hcan->Instance->ESR);
 8003ba8:	687b      	ldr	r3, [r7, #4]
 8003baa:	681b      	ldr	r3, [r3, #0]
 8003bac:	699b      	ldr	r3, [r3, #24]
 8003bae:	60fb      	str	r3, [r7, #12]

  /* Transmit Mailbox empty interrupt management *****************************/
  if ((interrupts & CAN_IT_TX_MAILBOX_EMPTY) != 0U)
 8003bb0:	6a3b      	ldr	r3, [r7, #32]
 8003bb2:	f003 0301 	and.w	r3, r3, #1
 8003bb6:	2b00      	cmp	r3, #0
 8003bb8:	d07c      	beq.n	8003cb4 <HAL_CAN_IRQHandler+0x140>
  {
    /* Transmit Mailbox 0 management *****************************************/
    if ((tsrflags & CAN_TSR_RQCP0) != 0U)
 8003bba:	69bb      	ldr	r3, [r7, #24]
 8003bbc:	f003 0301 	and.w	r3, r3, #1
 8003bc0:	2b00      	cmp	r3, #0
 8003bc2:	d023      	beq.n	8003c0c <HAL_CAN_IRQHandler+0x98>
    {
      /* Clear the Transmission Complete flag (and TXOK0,ALST0,TERR0 bits) */
      __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_RQCP0);
 8003bc4:	687b      	ldr	r3, [r7, #4]
 8003bc6:	681b      	ldr	r3, [r3, #0]
 8003bc8:	2201      	movs	r2, #1
 8003bca:	609a      	str	r2, [r3, #8]

      if ((tsrflags & CAN_TSR_TXOK0) != 0U)
 8003bcc:	69bb      	ldr	r3, [r7, #24]
 8003bce:	f003 0302 	and.w	r3, r3, #2
 8003bd2:	2b00      	cmp	r3, #0
 8003bd4:	d003      	beq.n	8003bde <HAL_CAN_IRQHandler+0x6a>
#if USE_HAL_CAN_REGISTER_CALLBACKS == 1
        /* Call registered callback*/
        hcan->TxMailbox0CompleteCallback(hcan);
#else
        /* Call weak (surcharged) callback */
        HAL_CAN_TxMailbox0CompleteCallback(hcan);
 8003bd6:	6878      	ldr	r0, [r7, #4]
 8003bd8:	f000 f983 	bl	8003ee2 <HAL_CAN_TxMailbox0CompleteCallback>
 8003bdc:	e016      	b.n	8003c0c <HAL_CAN_IRQHandler+0x98>
#endif /* USE_HAL_CAN_REGISTER_CALLBACKS */
      }
      else
      {
        if ((tsrflags & CAN_TSR_ALST0) != 0U)
 8003bde:	69bb      	ldr	r3, [r7, #24]
 8003be0:	f003 0304 	and.w	r3, r3, #4
 8003be4:	2b00      	cmp	r3, #0
 8003be6:	d004      	beq.n	8003bf2 <HAL_CAN_IRQHandler+0x7e>
        {
          /* Update error code */
          errorcode |= HAL_CAN_ERROR_TX_ALST0;
 8003be8:	6a7b      	ldr	r3, [r7, #36]	@ 0x24
 8003bea:	f443 6300 	orr.w	r3, r3, #2048	@ 0x800
 8003bee:	627b      	str	r3, [r7, #36]	@ 0x24
 8003bf0:	e00c      	b.n	8003c0c <HAL_CAN_IRQHandler+0x98>
        }
        else if ((tsrflags & CAN_TSR_TERR0) != 0U)
 8003bf2:	69bb      	ldr	r3, [r7, #24]
 8003bf4:	f003 0308 	and.w	r3, r3, #8
 8003bf8:	2b00      	cmp	r3, #0
 8003bfa:	d004      	beq.n	8003c06 <HAL_CAN_IRQHandler+0x92>
        {
          /* Update error code */
          errorcode |= HAL_CAN_ERROR_TX_TERR0;
 8003bfc:	6a7b      	ldr	r3, [r7, #36]	@ 0x24
 8003bfe:	f443 5380 	orr.w	r3, r3, #4096	@ 0x1000
 8003c02:	627b      	str	r3, [r7, #36]	@ 0x24
 8003c04:	e002      	b.n	8003c0c <HAL_CAN_IRQHandler+0x98>
#if USE_HAL_CAN_REGISTER_CALLBACKS == 1
          /* Call registered callback*/
          hcan->TxMailbox0AbortCallback(hcan);
#else
          /* Call weak (surcharged) callback */
          HAL_CAN_TxMailbox0AbortCallback(hcan);
 8003c06:	6878      	ldr	r0, [r7, #4]
 8003c08:	f000 f989 	bl	8003f1e <HAL_CAN_TxMailbox0AbortCallback>
        }
      }
    }

    /* Transmit Mailbox 1 management *****************************************/
    if ((tsrflags & CAN_TSR_RQCP1) != 0U)
 8003c0c:	69bb      	ldr	r3, [r7, #24]
 8003c0e:	f403 7380 	and.w	r3, r3, #256	@ 0x100
 8003c12:	2b00      	cmp	r3, #0
 8003c14:	d024      	beq.n	8003c60 <HAL_CAN_IRQHandler+0xec>
    {
      /* Clear the Transmission Complete flag (and TXOK1,ALST1,TERR1 bits) */
      __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_RQCP1);
 8003c16:	687b      	ldr	r3, [r7, #4]
 8003c18:	681b      	ldr	r3, [r3, #0]
 8003c1a:	f44f 7280 	mov.w	r2, #256	@ 0x100
 8003c1e:	609a      	str	r2, [r3, #8]

      if ((tsrflags & CAN_TSR_TXOK1) != 0U)
 8003c20:	69bb      	ldr	r3, [r7, #24]
 8003c22:	f403 7300 	and.w	r3, r3, #512	@ 0x200
 8003c26:	2b00      	cmp	r3, #0
 8003c28:	d003      	beq.n	8003c32 <HAL_CAN_IRQHandler+0xbe>
#if USE_HAL_CAN_REGISTER_CALLBACKS == 1
        /* Call registered callback*/
        hcan->TxMailbox1CompleteCallback(hcan);
#else
        /* Call weak (surcharged) callback */
        HAL_CAN_TxMailbox1CompleteCallback(hcan);
 8003c2a:	6878      	ldr	r0, [r7, #4]
 8003c2c:	f000 f963 	bl	8003ef6 <HAL_CAN_TxMailbox1CompleteCallback>
 8003c30:	e016      	b.n	8003c60 <HAL_CAN_IRQHandler+0xec>
#endif /* USE_HAL_CAN_REGISTER_CALLBACKS */
      }
      else
      {
        if ((tsrflags & CAN_TSR_ALST1) != 0U)
 8003c32:	69bb      	ldr	r3, [r7, #24]
 8003c34:	f403 6380 	and.w	r3, r3, #1024	@ 0x400
 8003c38:	2b00      	cmp	r3, #0
 8003c3a:	d004      	beq.n	8003c46 <HAL_CAN_IRQHandler+0xd2>
        {
          /* Update error code */
          errorcode |= HAL_CAN_ERROR_TX_ALST1;
 8003c3c:	6a7b      	ldr	r3, [r7, #36]	@ 0x24
 8003c3e:	f443 5300 	orr.w	r3, r3, #8192	@ 0x2000
 8003c42:	627b      	str	r3, [r7, #36]	@ 0x24
 8003c44:	e00c      	b.n	8003c60 <HAL_CAN_IRQHandler+0xec>
        }
        else if ((tsrflags & CAN_TSR_TERR1) != 0U)
 8003c46:	69bb      	ldr	r3, [r7, #24]
 8003c48:	f403 6300 	and.w	r3, r3, #2048	@ 0x800
 8003c4c:	2b00      	cmp	r3, #0
 8003c4e:	d004      	beq.n	8003c5a <HAL_CAN_IRQHandler+0xe6>
        {
          /* Update error code */
          errorcode |= HAL_CAN_ERROR_TX_TERR1;
 8003c50:	6a7b      	ldr	r3, [r7, #36]	@ 0x24
 8003c52:	f443 4380 	orr.w	r3, r3, #16384	@ 0x4000
 8003c56:	627b      	str	r3, [r7, #36]	@ 0x24
 8003c58:	e002      	b.n	8003c60 <HAL_CAN_IRQHandler+0xec>
#if USE_HAL_CAN_REGISTER_CALLBACKS == 1
          /* Call registered callback*/
          hcan->TxMailbox1AbortCallback(hcan);
#else
          /* Call weak (surcharged) callback */
          HAL_CAN_TxMailbox1AbortCallback(hcan);
 8003c5a:	6878      	ldr	r0, [r7, #4]
 8003c5c:	f000 f969 	bl	8003f32 <HAL_CAN_TxMailbox1AbortCallback>
        }
      }
    }

    /* Transmit Mailbox 2 management *****************************************/
    if ((tsrflags & CAN_TSR_RQCP2) != 0U)
 8003c60:	69bb      	ldr	r3, [r7, #24]
 8003c62:	f403 3380 	and.w	r3, r3, #65536	@ 0x10000
 8003c66:	2b00      	cmp	r3, #0
 8003c68:	d024      	beq.n	8003cb4 <HAL_CAN_IRQHandler+0x140>
    {
      /* Clear the Transmission Complete flag (and TXOK2,ALST2,TERR2 bits) */
      __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_RQCP2);
 8003c6a:	687b      	ldr	r3, [r7, #4]
 8003c6c:	681b      	ldr	r3, [r3, #0]
 8003c6e:	f44f 3280 	mov.w	r2, #65536	@ 0x10000
 8003c72:	609a      	str	r2, [r3, #8]

      if ((tsrflags & CAN_TSR_TXOK2) != 0U)
 8003c74:	69bb      	ldr	r3, [r7, #24]
 8003c76:	f403 3300 	and.w	r3, r3, #131072	@ 0x20000
 8003c7a:	2b00      	cmp	r3, #0
 8003c7c:	d003      	beq.n	8003c86 <HAL_CAN_IRQHandler+0x112>
#if USE_HAL_CAN_REGISTER_CALLBACKS == 1
        /* Call registered callback*/
        hcan->TxMailbox2CompleteCallback(hcan);
#else
        /* Call weak (surcharged) callback */
        HAL_CAN_TxMailbox2CompleteCallback(hcan);
 8003c7e:	6878      	ldr	r0, [r7, #4]
 8003c80:	f000 f943 	bl	8003f0a <HAL_CAN_TxMailbox2CompleteCallback>
 8003c84:	e016      	b.n	8003cb4 <HAL_CAN_IRQHandler+0x140>
#endif /* USE_HAL_CAN_REGISTER_CALLBACKS */
      }
      else
      {
        if ((tsrflags & CAN_TSR_ALST2) != 0U)
 8003c86:	69bb      	ldr	r3, [r7, #24]
 8003c88:	f403 2380 	and.w	r3, r3, #262144	@ 0x40000
 8003c8c:	2b00      	cmp	r3, #0
 8003c8e:	d004      	beq.n	8003c9a <HAL_CAN_IRQHandler+0x126>
        {
          /* Update error code */
          errorcode |= HAL_CAN_ERROR_TX_ALST2;
 8003c90:	6a7b      	ldr	r3, [r7, #36]	@ 0x24
 8003c92:	f443 4300 	orr.w	r3, r3, #32768	@ 0x8000
 8003c96:	627b      	str	r3, [r7, #36]	@ 0x24
 8003c98:	e00c      	b.n	8003cb4 <HAL_CAN_IRQHandler+0x140>
        }
        else if ((tsrflags & CAN_TSR_TERR2) != 0U)
 8003c9a:	69bb      	ldr	r3, [r7, #24]
 8003c9c:	f403 2300 	and.w	r3, r3, #524288	@ 0x80000
 8003ca0:	2b00      	cmp	r3, #0
 8003ca2:	d004      	beq.n	8003cae <HAL_CAN_IRQHandler+0x13a>
        {
          /* Update error code */
          errorcode |= HAL_CAN_ERROR_TX_TERR2;
 8003ca4:	6a7b      	ldr	r3, [r7, #36]	@ 0x24
 8003ca6:	f443 3380 	orr.w	r3, r3, #65536	@ 0x10000
 8003caa:	627b      	str	r3, [r7, #36]	@ 0x24
 8003cac:	e002      	b.n	8003cb4 <HAL_CAN_IRQHandler+0x140>
#if USE_HAL_CAN_REGISTER_CALLBACKS == 1
          /* Call registered callback*/
          hcan->TxMailbox2AbortCallback(hcan);
#else
          /* Call weak (surcharged) callback */
          HAL_CAN_TxMailbox2AbortCallback(hcan);
 8003cae:	6878      	ldr	r0, [r7, #4]
 8003cb0:	f000 f949 	bl	8003f46 <HAL_CAN_TxMailbox2AbortCallback>
      }
    }
  }

  /* Receive FIFO 0 overrun interrupt management *****************************/
  if ((interrupts & CAN_IT_RX_FIFO0_OVERRUN) != 0U)
 8003cb4:	6a3b      	ldr	r3, [r7, #32]
 8003cb6:	f003 0308 	and.w	r3, r3, #8
 8003cba:	2b00      	cmp	r3, #0
 8003cbc:	d00c      	beq.n	8003cd8 <HAL_CAN_IRQHandler+0x164>
  {
    if ((rf0rflags & CAN_RF0R_FOVR0) != 0U)
 8003cbe:	697b      	ldr	r3, [r7, #20]
 8003cc0:	f003 0310 	and.w	r3, r3, #16
 8003cc4:	2b00      	cmp	r3, #0
 8003cc6:	d007      	beq.n	8003cd8 <HAL_CAN_IRQHandler+0x164>
    {
      /* Set CAN error code to Rx Fifo 0 overrun error */
      errorcode |= HAL_CAN_ERROR_RX_FOV0;
 8003cc8:	6a7b      	ldr	r3, [r7, #36]	@ 0x24
 8003cca:	f443 7300 	orr.w	r3, r3, #512	@ 0x200
 8003cce:	627b      	str	r3, [r7, #36]	@ 0x24

      /* Clear FIFO0 Overrun Flag */
      __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_FOV0);
 8003cd0:	687b      	ldr	r3, [r7, #4]
 8003cd2:	681b      	ldr	r3, [r3, #0]
 8003cd4:	2210      	movs	r2, #16
 8003cd6:	60da      	str	r2, [r3, #12]
    }
  }

  /* Receive FIFO 0 full interrupt management ********************************/
  if ((interrupts & CAN_IT_RX_FIFO0_FULL) != 0U)
 8003cd8:	6a3b      	ldr	r3, [r7, #32]
 8003cda:	f003 0304 	and.w	r3, r3, #4
 8003cde:	2b00      	cmp	r3, #0
 8003ce0:	d00b      	beq.n	8003cfa <HAL_CAN_IRQHandler+0x186>
  {
    if ((rf0rflags & CAN_RF0R_FULL0) != 0U)
 8003ce2:	697b      	ldr	r3, [r7, #20]
 8003ce4:	f003 0308 	and.w	r3, r3, #8
 8003ce8:	2b00      	cmp	r3, #0
 8003cea:	d006      	beq.n	8003cfa <HAL_CAN_IRQHandler+0x186>
    {
      /* Clear FIFO 0 full Flag */
      __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_FF0);
 8003cec:	687b      	ldr	r3, [r7, #4]
 8003cee:	681b      	ldr	r3, [r3, #0]
 8003cf0:	2208      	movs	r2, #8
 8003cf2:	60da      	str	r2, [r3, #12]
#if USE_HAL_CAN_REGISTER_CALLBACKS == 1
      /* Call registered callback*/
      hcan->RxFifo0FullCallback(hcan);
#else
      /* Call weak (surcharged) callback */
      HAL_CAN_RxFifo0FullCallback(hcan);
 8003cf4:	6878      	ldr	r0, [r7, #4]
 8003cf6:	f000 f930 	bl	8003f5a <HAL_CAN_RxFifo0FullCallback>
#endif /* USE_HAL_CAN_REGISTER_CALLBACKS */
    }
  }

  /* Receive FIFO 0 message pending interrupt management *********************/
  if ((interrupts & CAN_IT_RX_FIFO0_MSG_PENDING) != 0U)
 8003cfa:	6a3b      	ldr	r3, [r7, #32]
 8003cfc:	f003 0302 	and.w	r3, r3, #2
 8003d00:	2b00      	cmp	r3, #0
 8003d02:	d009      	beq.n	8003d18 <HAL_CAN_IRQHandler+0x1a4>
  {
    /* Check if message is still pending */
    if ((hcan->Instance->RF0R & CAN_RF0R_FMP0) != 0U)
 8003d04:	687b      	ldr	r3, [r7, #4]
 8003d06:	681b      	ldr	r3, [r3, #0]
 8003d08:	68db      	ldr	r3, [r3, #12]
 8003d0a:	f003 0303 	and.w	r3, r3, #3
 8003d0e:	2b00      	cmp	r3, #0
 8003d10:	d002      	beq.n	8003d18 <HAL_CAN_IRQHandler+0x1a4>
#if USE_HAL_CAN_REGISTER_CALLBACKS == 1
      /* Call registered callback*/
      hcan->RxFifo0MsgPendingCallback(hcan);
#else
      /* Call weak (surcharged) callback */
      HAL_CAN_RxFifo0MsgPendingCallback(hcan);
 8003d12:	6878      	ldr	r0, [r7, #4]
 8003d14:	f7fc fd2e 	bl	8000774 <HAL_CAN_RxFifo0MsgPendingCallback>
#endif /* USE_HAL_CAN_REGISTER_CALLBACKS */
    }
  }

  /* Receive FIFO 1 overrun interrupt management *****************************/
  if ((interrupts & CAN_IT_RX_FIFO1_OVERRUN) != 0U)
 8003d18:	6a3b      	ldr	r3, [r7, #32]
 8003d1a:	f003 0340 	and.w	r3, r3, #64	@ 0x40
 8003d1e:	2b00      	cmp	r3, #0
 8003d20:	d00c      	beq.n	8003d3c <HAL_CAN_IRQHandler+0x1c8>
  {
    if ((rf1rflags & CAN_RF1R_FOVR1) != 0U)
 8003d22:	693b      	ldr	r3, [r7, #16]
 8003d24:	f003 0310 	and.w	r3, r3, #16
 8003d28:	2b00      	cmp	r3, #0
 8003d2a:	d007      	beq.n	8003d3c <HAL_CAN_IRQHandler+0x1c8>
    {
      /* Set CAN error code to Rx Fifo 1 overrun error */
      errorcode |= HAL_CAN_ERROR_RX_FOV1;
 8003d2c:	6a7b      	ldr	r3, [r7, #36]	@ 0x24
 8003d2e:	f443 6380 	orr.w	r3, r3, #1024	@ 0x400
 8003d32:	627b      	str	r3, [r7, #36]	@ 0x24

      /* Clear FIFO1 Overrun Flag */
      __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_FOV1);
 8003d34:	687b      	ldr	r3, [r7, #4]
 8003d36:	681b      	ldr	r3, [r3, #0]
 8003d38:	2210      	movs	r2, #16
 8003d3a:	611a      	str	r2, [r3, #16]
    }
  }

  /* Receive FIFO 1 full interrupt management ********************************/
  if ((interrupts & CAN_IT_RX_FIFO1_FULL) != 0U)
 8003d3c:	6a3b      	ldr	r3, [r7, #32]
 8003d3e:	f003 0320 	and.w	r3, r3, #32
 8003d42:	2b00      	cmp	r3, #0
 8003d44:	d00b      	beq.n	8003d5e <HAL_CAN_IRQHandler+0x1ea>
  {
    if ((rf1rflags & CAN_RF1R_FULL1) != 0U)
 8003d46:	693b      	ldr	r3, [r7, #16]
 8003d48:	f003 0308 	and.w	r3, r3, #8
 8003d4c:	2b00      	cmp	r3, #0
 8003d4e:	d006      	beq.n	8003d5e <HAL_CAN_IRQHandler+0x1ea>
    {
      /* Clear FIFO 1 full Flag */
      __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_FF1);
 8003d50:	687b      	ldr	r3, [r7, #4]
 8003d52:	681b      	ldr	r3, [r3, #0]
 8003d54:	2208      	movs	r2, #8
 8003d56:	611a      	str	r2, [r3, #16]
#if USE_HAL_CAN_REGISTER_CALLBACKS == 1
      /* Call registered callback*/
      hcan->RxFifo1FullCallback(hcan);
#else
      /* Call weak (surcharged) callback */
      HAL_CAN_RxFifo1FullCallback(hcan);
 8003d58:	6878      	ldr	r0, [r7, #4]
 8003d5a:	f000 f912 	bl	8003f82 <HAL_CAN_RxFifo1FullCallback>
#endif /* USE_HAL_CAN_REGISTER_CALLBACKS */
    }
  }

  /* Receive FIFO 1 message pending interrupt management *********************/
  if ((interrupts & CAN_IT_RX_FIFO1_MSG_PENDING) != 0U)
 8003d5e:	6a3b      	ldr	r3, [r7, #32]
 8003d60:	f003 0310 	and.w	r3, r3, #16
 8003d64:	2b00      	cmp	r3, #0
 8003d66:	d009      	beq.n	8003d7c <HAL_CAN_IRQHandler+0x208>
  {
    /* Check if message is still pending */
    if ((hcan->Instance->RF1R & CAN_RF1R_FMP1) != 0U)
 8003d68:	687b      	ldr	r3, [r7, #4]
 8003d6a:	681b      	ldr	r3, [r3, #0]
 8003d6c:	691b      	ldr	r3, [r3, #16]
 8003d6e:	f003 0303 	and.w	r3, r3, #3
 8003d72:	2b00      	cmp	r3, #0
 8003d74:	d002      	beq.n	8003d7c <HAL_CAN_IRQHandler+0x208>
#if USE_HAL_CAN_REGISTER_CALLBACKS == 1
      /* Call registered callback*/
      hcan->RxFifo1MsgPendingCallback(hcan);
#else
      /* Call weak (surcharged) callback */
      HAL_CAN_RxFifo1MsgPendingCallback(hcan);
 8003d76:	6878      	ldr	r0, [r7, #4]
 8003d78:	f000 f8f9 	bl	8003f6e <HAL_CAN_RxFifo1MsgPendingCallback>
#endif /* USE_HAL_CAN_REGISTER_CALLBACKS */
    }
  }

  /* Sleep interrupt management *********************************************/
  if ((interrupts & CAN_IT_SLEEP_ACK) != 0U)
 8003d7c:	6a3b      	ldr	r3, [r7, #32]
 8003d7e:	f403 3300 	and.w	r3, r3, #131072	@ 0x20000
 8003d82:	2b00      	cmp	r3, #0
 8003d84:	d00b      	beq.n	8003d9e <HAL_CAN_IRQHandler+0x22a>
  {
    if ((msrflags & CAN_MSR_SLAKI) != 0U)
 8003d86:	69fb      	ldr	r3, [r7, #28]
 8003d88:	f003 0310 	and.w	r3, r3, #16
 8003d8c:	2b00      	cmp	r3, #0
 8003d8e:	d006      	beq.n	8003d9e <HAL_CAN_IRQHandler+0x22a>
    {
      /* Clear Sleep interrupt Flag */
      __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_SLAKI);
 8003d90:	687b      	ldr	r3, [r7, #4]
 8003d92:	681b      	ldr	r3, [r3, #0]
 8003d94:	2210      	movs	r2, #16
 8003d96:	605a      	str	r2, [r3, #4]
#if USE_HAL_CAN_REGISTER_CALLBACKS == 1
      /* Call registered callback*/
      hcan->SleepCallback(hcan);
#else
      /* Call weak (surcharged) callback */
      HAL_CAN_SleepCallback(hcan);
 8003d98:	6878      	ldr	r0, [r7, #4]
 8003d9a:	f000 f8fc 	bl	8003f96 <HAL_CAN_SleepCallback>
#endif /* USE_HAL_CAN_REGISTER_CALLBACKS */
    }
  }

  /* WakeUp interrupt management *********************************************/
  if ((interrupts & CAN_IT_WAKEUP) != 0U)
 8003d9e:	6a3b      	ldr	r3, [r7, #32]
 8003da0:	f403 3380 	and.w	r3, r3, #65536	@ 0x10000
 8003da4:	2b00      	cmp	r3, #0
 8003da6:	d00b      	beq.n	8003dc0 <HAL_CAN_IRQHandler+0x24c>
  {
    if ((msrflags & CAN_MSR_WKUI) != 0U)
 8003da8:	69fb      	ldr	r3, [r7, #28]
 8003daa:	f003 0308 	and.w	r3, r3, #8
 8003dae:	2b00      	cmp	r3, #0
 8003db0:	d006      	beq.n	8003dc0 <HAL_CAN_IRQHandler+0x24c>
    {
      /* Clear WakeUp Flag */
      __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_WKU);
 8003db2:	687b      	ldr	r3, [r7, #4]
 8003db4:	681b      	ldr	r3, [r3, #0]
 8003db6:	2208      	movs	r2, #8
 8003db8:	605a      	str	r2, [r3, #4]
#if USE_HAL_CAN_REGISTER_CALLBACKS == 1
      /* Call registered callback*/
      hcan->WakeUpFromRxMsgCallback(hcan);
#else
      /* Call weak (surcharged) callback */
      HAL_CAN_WakeUpFromRxMsgCallback(hcan);
 8003dba:	6878      	ldr	r0, [r7, #4]
 8003dbc:	f000 f8f5 	bl	8003faa <HAL_CAN_WakeUpFromRxMsgCallback>
#endif /* USE_HAL_CAN_REGISTER_CALLBACKS */
    }
  }

  /* Error interrupts management *********************************************/
  if ((interrupts & CAN_IT_ERROR) != 0U)
 8003dc0:	6a3b      	ldr	r3, [r7, #32]
 8003dc2:	f403 4300 	and.w	r3, r3, #32768	@ 0x8000
 8003dc6:	2b00      	cmp	r3, #0
 8003dc8:	d07b      	beq.n	8003ec2 <HAL_CAN_IRQHandler+0x34e>
  {
    if ((msrflags & CAN_MSR_ERRI) != 0U)
 8003dca:	69fb      	ldr	r3, [r7, #28]
 8003dcc:	f003 0304 	and.w	r3, r3, #4
 8003dd0:	2b00      	cmp	r3, #0
 8003dd2:	d072      	beq.n	8003eba <HAL_CAN_IRQHandler+0x346>
    {
      /* Check Error Warning Flag */
      if (((interrupts & CAN_IT_ERROR_WARNING) != 0U) &&
 8003dd4:	6a3b      	ldr	r3, [r7, #32]
 8003dd6:	f403 7380 	and.w	r3, r3, #256	@ 0x100
 8003dda:	2b00      	cmp	r3, #0
 8003ddc:	d008      	beq.n	8003df0 <HAL_CAN_IRQHandler+0x27c>
          ((esrflags & CAN_ESR_EWGF) != 0U))
 8003dde:	68fb      	ldr	r3, [r7, #12]
 8003de0:	f003 0301 	and.w	r3, r3, #1
      if (((interrupts & CAN_IT_ERROR_WARNING) != 0U) &&
 8003de4:	2b00      	cmp	r3, #0
 8003de6:	d003      	beq.n	8003df0 <HAL_CAN_IRQHandler+0x27c>
      {
        /* Set CAN error code to Error Warning */
        errorcode |= HAL_CAN_ERROR_EWG;
 8003de8:	6a7b      	ldr	r3, [r7, #36]	@ 0x24
 8003dea:	f043 0301 	orr.w	r3, r3, #1
 8003dee:	627b      	str	r3, [r7, #36]	@ 0x24

        /* No need for clear of Error Warning Flag as read-only */
      }

      /* Check Error Passive Flag */
      if (((interrupts & CAN_IT_ERROR_PASSIVE) != 0U) &&
 8003df0:	6a3b      	ldr	r3, [r7, #32]
 8003df2:	f403 7300 	and.w	r3, r3, #512	@ 0x200
 8003df6:	2b00      	cmp	r3, #0
 8003df8:	d008      	beq.n	8003e0c <HAL_CAN_IRQHandler+0x298>
          ((esrflags & CAN_ESR_EPVF) != 0U))
 8003dfa:	68fb      	ldr	r3, [r7, #12]
 8003dfc:	f003 0302 	and.w	r3, r3, #2
      if (((interrupts & CAN_IT_ERROR_PASSIVE) != 0U) &&
 8003e00:	2b00      	cmp	r3, #0
 8003e02:	d003      	beq.n	8003e0c <HAL_CAN_IRQHandler+0x298>
      {
        /* Set CAN error code to Error Passive */
        errorcode |= HAL_CAN_ERROR_EPV;
 8003e04:	6a7b      	ldr	r3, [r7, #36]	@ 0x24
 8003e06:	f043 0302 	orr.w	r3, r3, #2
 8003e0a:	627b      	str	r3, [r7, #36]	@ 0x24

        /* No need for clear of Error Passive Flag as read-only */
      }

      /* Check Bus-off Flag */
      if (((interrupts & CAN_IT_BUSOFF) != 0U) &&
 8003e0c:	6a3b      	ldr	r3, [r7, #32]
 8003e0e:	f403 6380 	and.w	r3, r3, #1024	@ 0x400
 8003e12:	2b00      	cmp	r3, #0
 8003e14:	d008      	beq.n	8003e28 <HAL_CAN_IRQHandler+0x2b4>
          ((esrflags & CAN_ESR_BOFF) != 0U))
 8003e16:	68fb      	ldr	r3, [r7, #12]
 8003e18:	f003 0304 	and.w	r3, r3, #4
      if (((interrupts & CAN_IT_BUSOFF) != 0U) &&
 8003e1c:	2b00      	cmp	r3, #0
 8003e1e:	d003      	beq.n	8003e28 <HAL_CAN_IRQHandler+0x2b4>
      {
        /* Set CAN error code to Bus-Off */
        errorcode |= HAL_CAN_ERROR_BOF;
 8003e20:	6a7b      	ldr	r3, [r7, #36]	@ 0x24
 8003e22:	f043 0304 	orr.w	r3, r3, #4
 8003e26:	627b      	str	r3, [r7, #36]	@ 0x24

        /* No need for clear of Error Bus-Off as read-only */
      }

      /* Check Last Error Code Flag */
      if (((interrupts & CAN_IT_LAST_ERROR_CODE) != 0U) &&
 8003e28:	6a3b      	ldr	r3, [r7, #32]
 8003e2a:	f403 6300 	and.w	r3, r3, #2048	@ 0x800
 8003e2e:	2b00      	cmp	r3, #0
 8003e30:	d043      	beq.n	8003eba <HAL_CAN_IRQHandler+0x346>
          ((esrflags & CAN_ESR_LEC) != 0U))
 8003e32:	68fb      	ldr	r3, [r7, #12]
 8003e34:	f003 0370 	and.w	r3, r3, #112	@ 0x70
      if (((interrupts & CAN_IT_LAST_ERROR_CODE) != 0U) &&
 8003e38:	2b00      	cmp	r3, #0
 8003e3a:	d03e      	beq.n	8003eba <HAL_CAN_IRQHandler+0x346>
      {
        switch (esrflags & CAN_ESR_LEC)
 8003e3c:	68fb      	ldr	r3, [r7, #12]
 8003e3e:	f003 0370 	and.w	r3, r3, #112	@ 0x70
 8003e42:	2b60      	cmp	r3, #96	@ 0x60
 8003e44:	d02b      	beq.n	8003e9e <HAL_CAN_IRQHandler+0x32a>
 8003e46:	2b60      	cmp	r3, #96	@ 0x60
 8003e48:	d82e      	bhi.n	8003ea8 <HAL_CAN_IRQHandler+0x334>
 8003e4a:	2b50      	cmp	r3, #80	@ 0x50
 8003e4c:	d022      	beq.n	8003e94 <HAL_CAN_IRQHandler+0x320>
 8003e4e:	2b50      	cmp	r3, #80	@ 0x50
 8003e50:	d82a      	bhi.n	8003ea8 <HAL_CAN_IRQHandler+0x334>
 8003e52:	2b40      	cmp	r3, #64	@ 0x40
 8003e54:	d019      	beq.n	8003e8a <HAL_CAN_IRQHandler+0x316>
 8003e56:	2b40      	cmp	r3, #64	@ 0x40
 8003e58:	d826      	bhi.n	8003ea8 <HAL_CAN_IRQHandler+0x334>
 8003e5a:	2b30      	cmp	r3, #48	@ 0x30
 8003e5c:	d010      	beq.n	8003e80 <HAL_CAN_IRQHandler+0x30c>
 8003e5e:	2b30      	cmp	r3, #48	@ 0x30
 8003e60:	d822      	bhi.n	8003ea8 <HAL_CAN_IRQHandler+0x334>
 8003e62:	2b10      	cmp	r3, #16
 8003e64:	d002      	beq.n	8003e6c <HAL_CAN_IRQHandler+0x2f8>
 8003e66:	2b20      	cmp	r3, #32
 8003e68:	d005      	beq.n	8003e76 <HAL_CAN_IRQHandler+0x302>
          case (CAN_ESR_LEC_2 | CAN_ESR_LEC_1):
            /* Set CAN error code to CRC error */
            errorcode |= HAL_CAN_ERROR_CRC;
            break;
          default:
            break;
 8003e6a:	e01d      	b.n	8003ea8 <HAL_CAN_IRQHandler+0x334>
            errorcode |= HAL_CAN_ERROR_STF;
 8003e6c:	6a7b      	ldr	r3, [r7, #36]	@ 0x24
 8003e6e:	f043 0308 	orr.w	r3, r3, #8
 8003e72:	627b      	str	r3, [r7, #36]	@ 0x24
            break;
 8003e74:	e019      	b.n	8003eaa <HAL_CAN_IRQHandler+0x336>
            errorcode |= HAL_CAN_ERROR_FOR;
 8003e76:	6a7b      	ldr	r3, [r7, #36]	@ 0x24
 8003e78:	f043 0310 	orr.w	r3, r3, #16
 8003e7c:	627b      	str	r3, [r7, #36]	@ 0x24
            break;
 8003e7e:	e014      	b.n	8003eaa <HAL_CAN_IRQHandler+0x336>
            errorcode |= HAL_CAN_ERROR_ACK;
 8003e80:	6a7b      	ldr	r3, [r7, #36]	@ 0x24
 8003e82:	f043 0320 	orr.w	r3, r3, #32
 8003e86:	627b      	str	r3, [r7, #36]	@ 0x24
            break;
 8003e88:	e00f      	b.n	8003eaa <HAL_CAN_IRQHandler+0x336>
            errorcode |= HAL_CAN_ERROR_BR;
 8003e8a:	6a7b      	ldr	r3, [r7, #36]	@ 0x24
 8003e8c:	f043 0340 	orr.w	r3, r3, #64	@ 0x40
 8003e90:	627b      	str	r3, [r7, #36]	@ 0x24
            break;
 8003e92:	e00a      	b.n	8003eaa <HAL_CAN_IRQHandler+0x336>
            errorcode |= HAL_CAN_ERROR_BD;
 8003e94:	6a7b      	ldr	r3, [r7, #36]	@ 0x24
 8003e96:	f043 0380 	orr.w	r3, r3, #128	@ 0x80
 8003e9a:	627b      	str	r3, [r7, #36]	@ 0x24
            break;
 8003e9c:	e005      	b.n	8003eaa <HAL_CAN_IRQHandler+0x336>
            errorcode |= HAL_CAN_ERROR_CRC;
 8003e9e:	6a7b      	ldr	r3, [r7, #36]	@ 0x24
 8003ea0:	f443 7380 	orr.w	r3, r3, #256	@ 0x100
 8003ea4:	627b      	str	r3, [r7, #36]	@ 0x24
            break;
 8003ea6:	e000      	b.n	8003eaa <HAL_CAN_IRQHandler+0x336>
            break;
 8003ea8:	bf00      	nop
        }

        /* Clear Last error code Flag */
        CLEAR_BIT(hcan->Instance->ESR, CAN_ESR_LEC);
 8003eaa:	687b      	ldr	r3, [r7, #4]
 8003eac:	681b      	ldr	r3, [r3, #0]
 8003eae:	699a      	ldr	r2, [r3, #24]
 8003eb0:	687b      	ldr	r3, [r7, #4]
 8003eb2:	681b      	ldr	r3, [r3, #0]
 8003eb4:	f022 0270 	bic.w	r2, r2, #112	@ 0x70
 8003eb8:	619a      	str	r2, [r3, #24]
      }
    }

    /* Clear ERRI Flag */
    __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_ERRI);
 8003eba:	687b      	ldr	r3, [r7, #4]
 8003ebc:	681b      	ldr	r3, [r3, #0]
 8003ebe:	2204      	movs	r2, #4
 8003ec0:	605a      	str	r2, [r3, #4]
  }

  /* Call the Error call Back in case of Errors */
  if (errorcode != HAL_CAN_ERROR_NONE)
 8003ec2:	6a7b      	ldr	r3, [r7, #36]	@ 0x24
 8003ec4:	2b00      	cmp	r3, #0
 8003ec6:	d008      	beq.n	8003eda <HAL_CAN_IRQHandler+0x366>
  {
    /* Update error code in handle */
    hcan->ErrorCode |= errorcode;
 8003ec8:	687b      	ldr	r3, [r7, #4]
 8003eca:	6a5a      	ldr	r2, [r3, #36]	@ 0x24
 8003ecc:	6a7b      	ldr	r3, [r7, #36]	@ 0x24
 8003ece:	431a      	orrs	r2, r3
 8003ed0:	687b      	ldr	r3, [r7, #4]
 8003ed2:	625a      	str	r2, [r3, #36]	@ 0x24
#if USE_HAL_CAN_REGISTER_CALLBACKS == 1
    /* Call registered callback*/
    hcan->ErrorCallback(hcan);
#else
    /* Call weak (surcharged) callback */
    HAL_CAN_ErrorCallback(hcan);
 8003ed4:	6878      	ldr	r0, [r7, #4]
 8003ed6:	f000 f872 	bl	8003fbe <HAL_CAN_ErrorCallback>
#endif /* USE_HAL_CAN_REGISTER_CALLBACKS */
  }
}
 8003eda:	bf00      	nop
 8003edc:	3728      	adds	r7, #40	@ 0x28
 8003ede:	46bd      	mov	sp, r7
 8003ee0:	bd80      	pop	{r7, pc}

08003ee2 <HAL_CAN_TxMailbox0CompleteCallback>:
  * @param  hcan pointer to a CAN_HandleTypeDef structure that contains
  *         the configuration information for the specified CAN.
  * @retval None
  */
__weak void HAL_CAN_TxMailbox0CompleteCallback(CAN_HandleTypeDef *hcan)
{
 8003ee2:	b480      	push	{r7}
 8003ee4:	b083      	sub	sp, #12
 8003ee6:	af00      	add	r7, sp, #0
 8003ee8:	6078      	str	r0, [r7, #4]

  /* NOTE : This function Should not be modified, when the callback is needed,
            the HAL_CAN_TxMailbox0CompleteCallback could be implemented in the
            user file
   */
}
 8003eea:	bf00      	nop
 8003eec:	370c      	adds	r7, #12
 8003eee:	46bd      	mov	sp, r7
 8003ef0:	f85d 7b04 	ldr.w	r7, [sp], #4
 8003ef4:	4770      	bx	lr

08003ef6 <HAL_CAN_TxMailbox1CompleteCallback>:
  * @param  hcan pointer to a CAN_HandleTypeDef structure that contains
  *         the configuration information for the specified CAN.
  * @retval None
  */
__weak void HAL_CAN_TxMailbox1CompleteCallback(CAN_HandleTypeDef *hcan)
{
 8003ef6:	b480      	push	{r7}
 8003ef8:	b083      	sub	sp, #12
 8003efa:	af00      	add	r7, sp, #0
 8003efc:	6078      	str	r0, [r7, #4]

  /* NOTE : This function Should not be modified, when the callback is needed,
            the HAL_CAN_TxMailbox1CompleteCallback could be implemented in the
            user file
   */
}
 8003efe:	bf00      	nop
 8003f00:	370c      	adds	r7, #12
 8003f02:	46bd      	mov	sp, r7
 8003f04:	f85d 7b04 	ldr.w	r7, [sp], #4
 8003f08:	4770      	bx	lr

08003f0a <HAL_CAN_TxMailbox2CompleteCallback>:
  * @param  hcan pointer to a CAN_HandleTypeDef structure that contains
  *         the configuration information for the specified CAN.
  * @retval None
  */
__weak void HAL_CAN_TxMailbox2CompleteCallback(CAN_HandleTypeDef *hcan)
{
 8003f0a:	b480      	push	{r7}
 8003f0c:	b083      	sub	sp, #12
 8003f0e:	af00      	add	r7, sp, #0
 8003f10:	6078      	str	r0, [r7, #4]

  /* NOTE : This function Should not be modified, when the callback is needed,
            the HAL_CAN_TxMailbox2CompleteCallback could be implemented in the
            user file
   */
}
 8003f12:	bf00      	nop
 8003f14:	370c      	adds	r7, #12
 8003f16:	46bd      	mov	sp, r7
 8003f18:	f85d 7b04 	ldr.w	r7, [sp], #4
 8003f1c:	4770      	bx	lr

08003f1e <HAL_CAN_TxMailbox0AbortCallback>:
  * @param  hcan pointer to an CAN_HandleTypeDef structure that contains
  *         the configuration information for the specified CAN.
  * @retval None
  */
__weak void HAL_CAN_TxMailbox0AbortCallback(CAN_HandleTypeDef *hcan)
{
 8003f1e:	b480      	push	{r7}
 8003f20:	b083      	sub	sp, #12
 8003f22:	af00      	add	r7, sp, #0
 8003f24:	6078      	str	r0, [r7, #4]

  /* NOTE : This function Should not be modified, when the callback is needed,
            the HAL_CAN_TxMailbox0AbortCallback could be implemented in the
            user file
   */
}
 8003f26:	bf00      	nop
 8003f28:	370c      	adds	r7, #12
 8003f2a:	46bd      	mov	sp, r7
 8003f2c:	f85d 7b04 	ldr.w	r7, [sp], #4
 8003f30:	4770      	bx	lr

08003f32 <HAL_CAN_TxMailbox1AbortCallback>:
  * @param  hcan pointer to an CAN_HandleTypeDef structure that contains
  *         the configuration information for the specified CAN.
  * @retval None
  */
__weak void HAL_CAN_TxMailbox1AbortCallback(CAN_HandleTypeDef *hcan)
{
 8003f32:	b480      	push	{r7}
 8003f34:	b083      	sub	sp, #12
 8003f36:	af00      	add	r7, sp, #0
 8003f38:	6078      	str	r0, [r7, #4]

  /* NOTE : This function Should not be modified, when the callback is needed,
            the HAL_CAN_TxMailbox1AbortCallback could be implemented in the
            user file
   */
}
 8003f3a:	bf00      	nop
 8003f3c:	370c      	adds	r7, #12
 8003f3e:	46bd      	mov	sp, r7
 8003f40:	f85d 7b04 	ldr.w	r7, [sp], #4
 8003f44:	4770      	bx	lr

08003f46 <HAL_CAN_TxMailbox2AbortCallback>:
  * @param  hcan pointer to an CAN_HandleTypeDef structure that contains
  *         the configuration information for the specified CAN.
  * @retval None
  */
__weak void HAL_CAN_TxMailbox2AbortCallback(CAN_HandleTypeDef *hcan)
{
 8003f46:	b480      	push	{r7}
 8003f48:	b083      	sub	sp, #12
 8003f4a:	af00      	add	r7, sp, #0
 8003f4c:	6078      	str	r0, [r7, #4]

  /* NOTE : This function Should not be modified, when the callback is needed,
            the HAL_CAN_TxMailbox2AbortCallback could be implemented in the
            user file
   */
}
 8003f4e:	bf00      	nop
 8003f50:	370c      	adds	r7, #12
 8003f52:	46bd      	mov	sp, r7
 8003f54:	f85d 7b04 	ldr.w	r7, [sp], #4
 8003f58:	4770      	bx	lr

08003f5a <HAL_CAN_RxFifo0FullCallback>:
  * @param  hcan pointer to a CAN_HandleTypeDef structure that contains
  *         the configuration information for the specified CAN.
  * @retval None
  */
__weak void HAL_CAN_RxFifo0FullCallback(CAN_HandleTypeDef *hcan)
{
 8003f5a:	b480      	push	{r7}
 8003f5c:	b083      	sub	sp, #12
 8003f5e:	af00      	add	r7, sp, #0
 8003f60:	6078      	str	r0, [r7, #4]

  /* NOTE : This function Should not be modified, when the callback is needed,
            the HAL_CAN_RxFifo0FullCallback could be implemented in the user
            file
   */
}
 8003f62:	bf00      	nop
 8003f64:	370c      	adds	r7, #12
 8003f66:	46bd      	mov	sp, r7
 8003f68:	f85d 7b04 	ldr.w	r7, [sp], #4
 8003f6c:	4770      	bx	lr

08003f6e <HAL_CAN_RxFifo1MsgPendingCallback>:
  * @param  hcan pointer to a CAN_HandleTypeDef structure that contains
  *         the configuration information for the specified CAN.
  * @retval None
  */
__weak void HAL_CAN_RxFifo1MsgPendingCallback(CAN_HandleTypeDef *hcan)
{
 8003f6e:	b480      	push	{r7}
 8003f70:	b083      	sub	sp, #12
 8003f72:	af00      	add	r7, sp, #0
 8003f74:	6078      	str	r0, [r7, #4]

  /* NOTE : This function Should not be modified, when the callback is needed,
            the HAL_CAN_RxFifo1MsgPendingCallback could be implemented in the
            user file
   */
}
 8003f76:	bf00      	nop
 8003f78:	370c      	adds	r7, #12
 8003f7a:	46bd      	mov	sp, r7
 8003f7c:	f85d 7b04 	ldr.w	r7, [sp], #4
 8003f80:	4770      	bx	lr

08003f82 <HAL_CAN_RxFifo1FullCallback>:
  * @param  hcan pointer to a CAN_HandleTypeDef structure that contains
  *         the configuration information for the specified CAN.
  * @retval None
  */
__weak void HAL_CAN_RxFifo1FullCallback(CAN_HandleTypeDef *hcan)
{
 8003f82:	b480      	push	{r7}
 8003f84:	b083      	sub	sp, #12
 8003f86:	af00      	add	r7, sp, #0
 8003f88:	6078      	str	r0, [r7, #4]

  /* NOTE : This function Should not be modified, when the callback is needed,
            the HAL_CAN_RxFifo1FullCallback could be implemented in the user
            file
   */
}
 8003f8a:	bf00      	nop
 8003f8c:	370c      	adds	r7, #12
 8003f8e:	46bd      	mov	sp, r7
 8003f90:	f85d 7b04 	ldr.w	r7, [sp], #4
 8003f94:	4770      	bx	lr

08003f96 <HAL_CAN_SleepCallback>:
  * @param  hcan pointer to a CAN_HandleTypeDef structure that contains
  *         the configuration information for the specified CAN.
  * @retval None
  */
__weak void HAL_CAN_SleepCallback(CAN_HandleTypeDef *hcan)
{
 8003f96:	b480      	push	{r7}
 8003f98:	b083      	sub	sp, #12
 8003f9a:	af00      	add	r7, sp, #0
 8003f9c:	6078      	str	r0, [r7, #4]
  UNUSED(hcan);

  /* NOTE : This function Should not be modified, when the callback is needed,
            the HAL_CAN_SleepCallback could be implemented in the user file
   */
}
 8003f9e:	bf00      	nop
 8003fa0:	370c      	adds	r7, #12
 8003fa2:	46bd      	mov	sp, r7
 8003fa4:	f85d 7b04 	ldr.w	r7, [sp], #4
 8003fa8:	4770      	bx	lr

08003faa <HAL_CAN_WakeUpFromRxMsgCallback>:
  * @param  hcan pointer to a CAN_HandleTypeDef structure that contains
  *         the configuration information for the specified CAN.
  * @retval None
  */
__weak void HAL_CAN_WakeUpFromRxMsgCallback(CAN_HandleTypeDef *hcan)
{
 8003faa:	b480      	push	{r7}
 8003fac:	b083      	sub	sp, #12
 8003fae:	af00      	add	r7, sp, #0
 8003fb0:	6078      	str	r0, [r7, #4]

  /* NOTE : This function Should not be modified, when the callback is needed,
            the HAL_CAN_WakeUpFromRxMsgCallback could be implemented in the
            user file
   */
}
 8003fb2:	bf00      	nop
 8003fb4:	370c      	adds	r7, #12
 8003fb6:	46bd      	mov	sp, r7
 8003fb8:	f85d 7b04 	ldr.w	r7, [sp], #4
 8003fbc:	4770      	bx	lr

08003fbe <HAL_CAN_ErrorCallback>:
  * @param  hcan pointer to a CAN_HandleTypeDef structure that contains
  *         the configuration information for the specified CAN.
  * @retval None
  */
__weak void HAL_CAN_ErrorCallback(CAN_HandleTypeDef *hcan)
{
 8003fbe:	b480      	push	{r7}
 8003fc0:	b083      	sub	sp, #12
 8003fc2:	af00      	add	r7, sp, #0
 8003fc4:	6078      	str	r0, [r7, #4]
  UNUSED(hcan);

  /* NOTE : This function Should not be modified, when the callback is needed,
            the HAL_CAN_ErrorCallback could be implemented in the user file
   */
}
 8003fc6:	bf00      	nop
 8003fc8:	370c      	adds	r7, #12
 8003fca:	46bd      	mov	sp, r7
 8003fcc:	f85d 7b04 	ldr.w	r7, [sp], #4
 8003fd0:	4770      	bx	lr
	...

08003fd4 <__NVIC_SetPriorityGrouping>:
           In case of a conflict between priority grouping and available
           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
  \param [in]      PriorityGroup  Priority grouping field.
 */
__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
{
 8003fd4:	b480      	push	{r7}
 8003fd6:	b085      	sub	sp, #20
 8003fd8:	af00      	add	r7, sp, #0
 8003fda:	6078      	str	r0, [r7, #4]
  uint32_t reg_value;
  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);             /* only values 0..7 are used          */
 8003fdc:	687b      	ldr	r3, [r7, #4]
 8003fde:	f003 0307 	and.w	r3, r3, #7
 8003fe2:	60fb      	str	r3, [r7, #12]

  reg_value  =  SCB->AIRCR;                                                   /* read old register configuration    */
 8003fe4:	4b0c      	ldr	r3, [pc, #48]	@ (8004018 <__NVIC_SetPriorityGrouping+0x44>)
 8003fe6:	68db      	ldr	r3, [r3, #12]
 8003fe8:	60bb      	str	r3, [r7, #8]
  reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change               */
 8003fea:	68ba      	ldr	r2, [r7, #8]
 8003fec:	f64f 03ff 	movw	r3, #63743	@ 0xf8ff
 8003ff0:	4013      	ands	r3, r2
 8003ff2:	60bb      	str	r3, [r7, #8]
  reg_value  =  (reg_value                                   |
                ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
                (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos)  );              /* Insert write key and priority group */
 8003ff4:	68fb      	ldr	r3, [r7, #12]
 8003ff6:	021a      	lsls	r2, r3, #8
                ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
 8003ff8:	68bb      	ldr	r3, [r7, #8]
 8003ffa:	4313      	orrs	r3, r2
  reg_value  =  (reg_value                                   |
 8003ffc:	f043 63bf 	orr.w	r3, r3, #100139008	@ 0x5f80000
 8004000:	f443 3300 	orr.w	r3, r3, #131072	@ 0x20000
 8004004:	60bb      	str	r3, [r7, #8]
  SCB->AIRCR =  reg_value;
 8004006:	4a04      	ldr	r2, [pc, #16]	@ (8004018 <__NVIC_SetPriorityGrouping+0x44>)
 8004008:	68bb      	ldr	r3, [r7, #8]
 800400a:	60d3      	str	r3, [r2, #12]
}
 800400c:	bf00      	nop
 800400e:	3714      	adds	r7, #20
 8004010:	46bd      	mov	sp, r7
 8004012:	f85d 7b04 	ldr.w	r7, [sp], #4
 8004016:	4770      	bx	lr
 8004018:	e000ed00 	.word	0xe000ed00

0800401c <__NVIC_GetPriorityGrouping>:
  \brief   Get Priority Grouping
  \details Reads the priority grouping field from the NVIC Interrupt Controller.
  \return                Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
 */
__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
{
 800401c:	b480      	push	{r7}
 800401e:	af00      	add	r7, sp, #0
  return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
 8004020:	4b04      	ldr	r3, [pc, #16]	@ (8004034 <__NVIC_GetPriorityGrouping+0x18>)
 8004022:	68db      	ldr	r3, [r3, #12]
 8004024:	0a1b      	lsrs	r3, r3, #8
 8004026:	f003 0307 	and.w	r3, r3, #7
}
 800402a:	4618      	mov	r0, r3
 800402c:	46bd      	mov	sp, r7
 800402e:	f85d 7b04 	ldr.w	r7, [sp], #4
 8004032:	4770      	bx	lr
 8004034:	e000ed00 	.word	0xe000ed00

08004038 <__NVIC_EnableIRQ>:
  \details Enables a device specific interrupt in the NVIC interrupt controller.
  \param [in]      IRQn  Device specific interrupt number.
  \note    IRQn must not be negative.
 */
__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
{
 8004038:	b480      	push	{r7}
 800403a:	b083      	sub	sp, #12
 800403c:	af00      	add	r7, sp, #0
 800403e:	4603      	mov	r3, r0
 8004040:	71fb      	strb	r3, [r7, #7]
  if ((int32_t)(IRQn) >= 0)
 8004042:	f997 3007 	ldrsb.w	r3, [r7, #7]
 8004046:	2b00      	cmp	r3, #0
 8004048:	db0b      	blt.n	8004062 <__NVIC_EnableIRQ+0x2a>
  {
    __COMPILER_BARRIER();
    NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
 800404a:	79fb      	ldrb	r3, [r7, #7]
 800404c:	f003 021f 	and.w	r2, r3, #31
 8004050:	4907      	ldr	r1, [pc, #28]	@ (8004070 <__NVIC_EnableIRQ+0x38>)
 8004052:	f997 3007 	ldrsb.w	r3, [r7, #7]
 8004056:	095b      	lsrs	r3, r3, #5
 8004058:	2001      	movs	r0, #1
 800405a:	fa00 f202 	lsl.w	r2, r0, r2
 800405e:	f841 2023 	str.w	r2, [r1, r3, lsl #2]
    __COMPILER_BARRIER();
  }
}
 8004062:	bf00      	nop
 8004064:	370c      	adds	r7, #12
 8004066:	46bd      	mov	sp, r7
 8004068:	f85d 7b04 	ldr.w	r7, [sp], #4
 800406c:	4770      	bx	lr
 800406e:	bf00      	nop
 8004070:	e000e100 	.word	0xe000e100

08004074 <__NVIC_DisableIRQ>:
  \details Disables a device specific interrupt in the NVIC interrupt controller.
  \param [in]      IRQn  Device specific interrupt number.
  \note    IRQn must not be negative.
 */
__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
{
 8004074:	b480      	push	{r7}
 8004076:	b083      	sub	sp, #12
 8004078:	af00      	add	r7, sp, #0
 800407a:	4603      	mov	r3, r0
 800407c:	71fb      	strb	r3, [r7, #7]
  if ((int32_t)(IRQn) >= 0)
 800407e:	f997 3007 	ldrsb.w	r3, [r7, #7]
 8004082:	2b00      	cmp	r3, #0
 8004084:	db12      	blt.n	80040ac <__NVIC_DisableIRQ+0x38>
  {
    NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
 8004086:	79fb      	ldrb	r3, [r7, #7]
 8004088:	f003 021f 	and.w	r2, r3, #31
 800408c:	490a      	ldr	r1, [pc, #40]	@ (80040b8 <__NVIC_DisableIRQ+0x44>)
 800408e:	f997 3007 	ldrsb.w	r3, [r7, #7]
 8004092:	095b      	lsrs	r3, r3, #5
 8004094:	2001      	movs	r0, #1
 8004096:	fa00 f202 	lsl.w	r2, r0, r2
 800409a:	3320      	adds	r3, #32
 800409c:	f841 2023 	str.w	r2, [r1, r3, lsl #2]
  __ASM volatile ("dsb 0xF":::"memory");
 80040a0:	f3bf 8f4f 	dsb	sy
}
 80040a4:	bf00      	nop
  __ASM volatile ("isb 0xF":::"memory");
 80040a6:	f3bf 8f6f 	isb	sy
}
 80040aa:	bf00      	nop
    __DSB();
    __ISB();
  }
}
 80040ac:	bf00      	nop
 80040ae:	370c      	adds	r7, #12
 80040b0:	46bd      	mov	sp, r7
 80040b2:	f85d 7b04 	ldr.w	r7, [sp], #4
 80040b6:	4770      	bx	lr
 80040b8:	e000e100 	.word	0xe000e100

080040bc <__NVIC_SetPriority>:
  \param [in]      IRQn  Interrupt number.
  \param [in]  priority  Priority to set.
  \note    The priority cannot be set for every processor exception.
 */
__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
{
 80040bc:	b480      	push	{r7}
 80040be:	b083      	sub	sp, #12
 80040c0:	af00      	add	r7, sp, #0
 80040c2:	4603      	mov	r3, r0
 80040c4:	6039      	str	r1, [r7, #0]
 80040c6:	71fb      	strb	r3, [r7, #7]
  if ((int32_t)(IRQn) >= 0)
 80040c8:	f997 3007 	ldrsb.w	r3, [r7, #7]
 80040cc:	2b00      	cmp	r3, #0
 80040ce:	db0a      	blt.n	80040e6 <__NVIC_SetPriority+0x2a>
  {
    NVIC->IP[((uint32_t)IRQn)]               = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
 80040d0:	683b      	ldr	r3, [r7, #0]
 80040d2:	b2da      	uxtb	r2, r3
 80040d4:	490c      	ldr	r1, [pc, #48]	@ (8004108 <__NVIC_SetPriority+0x4c>)
 80040d6:	f997 3007 	ldrsb.w	r3, [r7, #7]
 80040da:	0112      	lsls	r2, r2, #4
 80040dc:	b2d2      	uxtb	r2, r2
 80040de:	440b      	add	r3, r1
 80040e0:	f883 2300 	strb.w	r2, [r3, #768]	@ 0x300
  }
  else
  {
    SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
  }
}
 80040e4:	e00a      	b.n	80040fc <__NVIC_SetPriority+0x40>
    SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
 80040e6:	683b      	ldr	r3, [r7, #0]
 80040e8:	b2da      	uxtb	r2, r3
 80040ea:	4908      	ldr	r1, [pc, #32]	@ (800410c <__NVIC_SetPriority+0x50>)
 80040ec:	79fb      	ldrb	r3, [r7, #7]
 80040ee:	f003 030f 	and.w	r3, r3, #15
 80040f2:	3b04      	subs	r3, #4
 80040f4:	0112      	lsls	r2, r2, #4
 80040f6:	b2d2      	uxtb	r2, r2
 80040f8:	440b      	add	r3, r1
 80040fa:	761a      	strb	r2, [r3, #24]
}
 80040fc:	bf00      	nop
 80040fe:	370c      	adds	r7, #12
 8004100:	46bd      	mov	sp, r7
 8004102:	f85d 7b04 	ldr.w	r7, [sp], #4
 8004106:	4770      	bx	lr
 8004108:	e000e100 	.word	0xe000e100
 800410c:	e000ed00 	.word	0xe000ed00

08004110 <NVIC_EncodePriority>:
  \param [in]   PreemptPriority  Preemptive priority value (starting from 0).
  \param [in]       SubPriority  Subpriority value (starting from 0).
  \return                        Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
 */
__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
{
 8004110:	b480      	push	{r7}
 8004112:	b089      	sub	sp, #36	@ 0x24
 8004114:	af00      	add	r7, sp, #0
 8004116:	60f8      	str	r0, [r7, #12]
 8004118:	60b9      	str	r1, [r7, #8]
 800411a:	607a      	str	r2, [r7, #4]
  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
 800411c:	68fb      	ldr	r3, [r7, #12]
 800411e:	f003 0307 	and.w	r3, r3, #7
 8004122:	61fb      	str	r3, [r7, #28]
  uint32_t PreemptPriorityBits;
  uint32_t SubPriorityBits;

  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
 8004124:	69fb      	ldr	r3, [r7, #28]
 8004126:	f1c3 0307 	rsb	r3, r3, #7
 800412a:	2b04      	cmp	r3, #4
 800412c:	bf28      	it	cs
 800412e:	2304      	movcs	r3, #4
 8004130:	61bb      	str	r3, [r7, #24]
  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
 8004132:	69fb      	ldr	r3, [r7, #28]
 8004134:	3304      	adds	r3, #4
 8004136:	2b06      	cmp	r3, #6
 8004138:	d902      	bls.n	8004140 <NVIC_EncodePriority+0x30>
 800413a:	69fb      	ldr	r3, [r7, #28]
 800413c:	3b03      	subs	r3, #3
 800413e:	e000      	b.n	8004142 <NVIC_EncodePriority+0x32>
 8004140:	2300      	movs	r3, #0
 8004142:	617b      	str	r3, [r7, #20]

  return (
           ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
 8004144:	f04f 32ff 	mov.w	r2, #4294967295
 8004148:	69bb      	ldr	r3, [r7, #24]
 800414a:	fa02 f303 	lsl.w	r3, r2, r3
 800414e:	43da      	mvns	r2, r3
 8004150:	68bb      	ldr	r3, [r7, #8]
 8004152:	401a      	ands	r2, r3
 8004154:	697b      	ldr	r3, [r7, #20]
 8004156:	409a      	lsls	r2, r3
           ((SubPriority     & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL)))
 8004158:	f04f 31ff 	mov.w	r1, #4294967295
 800415c:	697b      	ldr	r3, [r7, #20]
 800415e:	fa01 f303 	lsl.w	r3, r1, r3
 8004162:	43d9      	mvns	r1, r3
 8004164:	687b      	ldr	r3, [r7, #4]
 8004166:	400b      	ands	r3, r1
           ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
 8004168:	4313      	orrs	r3, r2
         );
}
 800416a:	4618      	mov	r0, r3
 800416c:	3724      	adds	r7, #36	@ 0x24
 800416e:	46bd      	mov	sp, r7
 8004170:	f85d 7b04 	ldr.w	r7, [sp], #4
 8004174:	4770      	bx	lr
	...

08004178 <SysTick_Config>:
  \note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
           function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
           must contain a vendor-specific implementation of this function.
 */
__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
{
 8004178:	b580      	push	{r7, lr}
 800417a:	b082      	sub	sp, #8
 800417c:	af00      	add	r7, sp, #0
 800417e:	6078      	str	r0, [r7, #4]
  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
 8004180:	687b      	ldr	r3, [r7, #4]
 8004182:	3b01      	subs	r3, #1
 8004184:	f1b3 7f80 	cmp.w	r3, #16777216	@ 0x1000000
 8004188:	d301      	bcc.n	800418e <SysTick_Config+0x16>
  {
    return (1UL);                                                   /* Reload value impossible */
 800418a:	2301      	movs	r3, #1
 800418c:	e00f      	b.n	80041ae <SysTick_Config+0x36>
  }

  SysTick->LOAD  = (uint32_t)(ticks - 1UL);                         /* set reload register */
 800418e:	4a0a      	ldr	r2, [pc, #40]	@ (80041b8 <SysTick_Config+0x40>)
 8004190:	687b      	ldr	r3, [r7, #4]
 8004192:	3b01      	subs	r3, #1
 8004194:	6053      	str	r3, [r2, #4]
  NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
 8004196:	210f      	movs	r1, #15
 8004198:	f04f 30ff 	mov.w	r0, #4294967295
 800419c:	f7ff ff8e 	bl	80040bc <__NVIC_SetPriority>
  SysTick->VAL   = 0UL;                                             /* Load the SysTick Counter Value */
 80041a0:	4b05      	ldr	r3, [pc, #20]	@ (80041b8 <SysTick_Config+0x40>)
 80041a2:	2200      	movs	r2, #0
 80041a4:	609a      	str	r2, [r3, #8]
  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
 80041a6:	4b04      	ldr	r3, [pc, #16]	@ (80041b8 <SysTick_Config+0x40>)
 80041a8:	2207      	movs	r2, #7
 80041aa:	601a      	str	r2, [r3, #0]
                   SysTick_CTRL_TICKINT_Msk   |
                   SysTick_CTRL_ENABLE_Msk;                         /* Enable SysTick IRQ and SysTick Timer */
  return (0UL);                                                     /* Function successful */
 80041ac:	2300      	movs	r3, #0
}
 80041ae:	4618      	mov	r0, r3
 80041b0:	3708      	adds	r7, #8
 80041b2:	46bd      	mov	sp, r7
 80041b4:	bd80      	pop	{r7, pc}
 80041b6:	bf00      	nop
 80041b8:	e000e010 	.word	0xe000e010

080041bc <HAL_NVIC_SetPriorityGrouping>:
  * @note   When the NVIC_PriorityGroup_0 is selected, IRQ preemption is no more possible. 
  *         The pending IRQ priority will be managed only by the subpriority. 
  * @retval None
  */
void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
{
 80041bc:	b580      	push	{r7, lr}
 80041be:	b082      	sub	sp, #8
 80041c0:	af00      	add	r7, sp, #0
 80041c2:	6078      	str	r0, [r7, #4]
  /* Check the parameters */
  assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup));
  
  /* Set the PRIGROUP[10:8] bits according to the PriorityGroup parameter value */
  NVIC_SetPriorityGrouping(PriorityGroup);
 80041c4:	6878      	ldr	r0, [r7, #4]
 80041c6:	f7ff ff05 	bl	8003fd4 <__NVIC_SetPriorityGrouping>
}
 80041ca:	bf00      	nop
 80041cc:	3708      	adds	r7, #8
 80041ce:	46bd      	mov	sp, r7
 80041d0:	bd80      	pop	{r7, pc}

080041d2 <HAL_NVIC_SetPriority>:
  *         This parameter can be a value between 0 and 15
  *         A lower priority value indicates a higher priority.          
  * @retval None
  */
void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority)
{ 
 80041d2:	b580      	push	{r7, lr}
 80041d4:	b086      	sub	sp, #24
 80041d6:	af00      	add	r7, sp, #0
 80041d8:	4603      	mov	r3, r0
 80041da:	60b9      	str	r1, [r7, #8]
 80041dc:	607a      	str	r2, [r7, #4]
 80041de:	73fb      	strb	r3, [r7, #15]
  uint32_t prioritygroup = 0x00U;
 80041e0:	2300      	movs	r3, #0
 80041e2:	617b      	str	r3, [r7, #20]
  
  /* Check the parameters */
  assert_param(IS_NVIC_SUB_PRIORITY(SubPriority));
  assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority));
  
  prioritygroup = NVIC_GetPriorityGrouping();
 80041e4:	f7ff ff1a 	bl	800401c <__NVIC_GetPriorityGrouping>
 80041e8:	6178      	str	r0, [r7, #20]
  
  NVIC_SetPriority(IRQn, NVIC_EncodePriority(prioritygroup, PreemptPriority, SubPriority));
 80041ea:	687a      	ldr	r2, [r7, #4]
 80041ec:	68b9      	ldr	r1, [r7, #8]
 80041ee:	6978      	ldr	r0, [r7, #20]
 80041f0:	f7ff ff8e 	bl	8004110 <NVIC_EncodePriority>
 80041f4:	4602      	mov	r2, r0
 80041f6:	f997 300f 	ldrsb.w	r3, [r7, #15]
 80041fa:	4611      	mov	r1, r2
 80041fc:	4618      	mov	r0, r3
 80041fe:	f7ff ff5d 	bl	80040bc <__NVIC_SetPriority>
}
 8004202:	bf00      	nop
 8004204:	3718      	adds	r7, #24
 8004206:	46bd      	mov	sp, r7
 8004208:	bd80      	pop	{r7, pc}

0800420a <HAL_NVIC_EnableIRQ>:
  *         This parameter can be an enumerator of IRQn_Type enumeration
  *         (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f4xxxx.h))
  * @retval None
  */
void HAL_NVIC_EnableIRQ(IRQn_Type IRQn)
{
 800420a:	b580      	push	{r7, lr}
 800420c:	b082      	sub	sp, #8
 800420e:	af00      	add	r7, sp, #0
 8004210:	4603      	mov	r3, r0
 8004212:	71fb      	strb	r3, [r7, #7]
  /* Check the parameters */
  assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
  
  /* Enable interrupt */
  NVIC_EnableIRQ(IRQn);
 8004214:	f997 3007 	ldrsb.w	r3, [r7, #7]
 8004218:	4618      	mov	r0, r3
 800421a:	f7ff ff0d 	bl	8004038 <__NVIC_EnableIRQ>
}
 800421e:	bf00      	nop
 8004220:	3708      	adds	r7, #8
 8004222:	46bd      	mov	sp, r7
 8004224:	bd80      	pop	{r7, pc}

08004226 <HAL_NVIC_DisableIRQ>:
  *         This parameter can be an enumerator of IRQn_Type enumeration
  *         (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f4xxxx.h))
  * @retval None
  */
void HAL_NVIC_DisableIRQ(IRQn_Type IRQn)
{
 8004226:	b580      	push	{r7, lr}
 8004228:	b082      	sub	sp, #8
 800422a:	af00      	add	r7, sp, #0
 800422c:	4603      	mov	r3, r0
 800422e:	71fb      	strb	r3, [r7, #7]
  /* Check the parameters */
  assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
  
  /* Disable interrupt */
  NVIC_DisableIRQ(IRQn);
 8004230:	f997 3007 	ldrsb.w	r3, [r7, #7]
 8004234:	4618      	mov	r0, r3
 8004236:	f7ff ff1d 	bl	8004074 <__NVIC_DisableIRQ>
}
 800423a:	bf00      	nop
 800423c:	3708      	adds	r7, #8
 800423e:	46bd      	mov	sp, r7
 8004240:	bd80      	pop	{r7, pc}

08004242 <HAL_SYSTICK_Config>:
  * @param  TicksNumb Specifies the ticks Number of ticks between two interrupts.
  * @retval status:  - 0  Function succeeded.
  *                  - 1  Function failed.
  */
uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb)
{
 8004242:	b580      	push	{r7, lr}
 8004244:	b082      	sub	sp, #8
 8004246:	af00      	add	r7, sp, #0
 8004248:	6078      	str	r0, [r7, #4]
   return SysTick_Config(TicksNumb);
 800424a:	6878      	ldr	r0, [r7, #4]
 800424c:	f7ff ff94 	bl	8004178 <SysTick_Config>
 8004250:	4603      	mov	r3, r0
}
 8004252:	4618      	mov	r0, r3
 8004254:	3708      	adds	r7, #8
 8004256:	46bd      	mov	sp, r7
 8004258:	bd80      	pop	{r7, pc}
	...

0800425c <HAL_GPIO_Init>:
  * @param  GPIO_Init pointer to a GPIO_InitTypeDef structure that contains
  *         the configuration information for the specified GPIO peripheral.
  * @retval None
  */
void HAL_GPIO_Init(GPIO_TypeDef  *GPIOx, GPIO_InitTypeDef *GPIO_Init)
{
 800425c:	b480      	push	{r7}
 800425e:	b089      	sub	sp, #36	@ 0x24
 8004260:	af00      	add	r7, sp, #0
 8004262:	6078      	str	r0, [r7, #4]
 8004264:	6039      	str	r1, [r7, #0]
  uint32_t position;
  uint32_t ioposition = 0x00U;
 8004266:	2300      	movs	r3, #0
 8004268:	617b      	str	r3, [r7, #20]
  uint32_t iocurrent = 0x00U;
 800426a:	2300      	movs	r3, #0
 800426c:	613b      	str	r3, [r7, #16]
  uint32_t temp = 0x00U;
 800426e:	2300      	movs	r3, #0
 8004270:	61bb      	str	r3, [r7, #24]
  assert_param(IS_GPIO_ALL_INSTANCE(GPIOx));
  assert_param(IS_GPIO_PIN(GPIO_Init->Pin));
  assert_param(IS_GPIO_MODE(GPIO_Init->Mode));

  /* Configure the port pins */
  for(position = 0U; position < GPIO_NUMBER; position++)
 8004272:	2300      	movs	r3, #0
 8004274:	61fb      	str	r3, [r7, #28]
 8004276:	e16b      	b.n	8004550 <HAL_GPIO_Init+0x2f4>
  {
    /* Get the IO position */
    ioposition = 0x01U << position;
 8004278:	2201      	movs	r2, #1
 800427a:	69fb      	ldr	r3, [r7, #28]
 800427c:	fa02 f303 	lsl.w	r3, r2, r3
 8004280:	617b      	str	r3, [r7, #20]
    /* Get the current IO position */
    iocurrent = (uint32_t)(GPIO_Init->Pin) & ioposition;
 8004282:	683b      	ldr	r3, [r7, #0]
 8004284:	681b      	ldr	r3, [r3, #0]
 8004286:	697a      	ldr	r2, [r7, #20]
 8004288:	4013      	ands	r3, r2
 800428a:	613b      	str	r3, [r7, #16]

    if(iocurrent == ioposition)
 800428c:	693a      	ldr	r2, [r7, #16]
 800428e:	697b      	ldr	r3, [r7, #20]
 8004290:	429a      	cmp	r2, r3
 8004292:	f040 815a 	bne.w	800454a <HAL_GPIO_Init+0x2ee>
    {
      /*--------------------- GPIO Mode Configuration ------------------------*/
      /* In case of Output or Alternate function mode selection */
      if(((GPIO_Init->Mode & GPIO_MODE) == MODE_OUTPUT) || \
 8004296:	683b      	ldr	r3, [r7, #0]
 8004298:	685b      	ldr	r3, [r3, #4]
 800429a:	f003 0303 	and.w	r3, r3, #3
 800429e:	2b01      	cmp	r3, #1
 80042a0:	d005      	beq.n	80042ae <HAL_GPIO_Init+0x52>
          (GPIO_Init->Mode & GPIO_MODE) == MODE_AF)
 80042a2:	683b      	ldr	r3, [r7, #0]
 80042a4:	685b      	ldr	r3, [r3, #4]
 80042a6:	f003 0303 	and.w	r3, r3, #3
      if(((GPIO_Init->Mode & GPIO_MODE) == MODE_OUTPUT) || \
 80042aa:	2b02      	cmp	r3, #2
 80042ac:	d130      	bne.n	8004310 <HAL_GPIO_Init+0xb4>
      {
        /* Check the Speed parameter */
        assert_param(IS_GPIO_SPEED(GPIO_Init->Speed));
        /* Configure the IO Speed */
        temp = GPIOx->OSPEEDR; 
 80042ae:	687b      	ldr	r3, [r7, #4]
 80042b0:	689b      	ldr	r3, [r3, #8]
 80042b2:	61bb      	str	r3, [r7, #24]
        temp &= ~(GPIO_OSPEEDER_OSPEEDR0 << (position * 2U));
 80042b4:	69fb      	ldr	r3, [r7, #28]
 80042b6:	005b      	lsls	r3, r3, #1
 80042b8:	2203      	movs	r2, #3
 80042ba:	fa02 f303 	lsl.w	r3, r2, r3
 80042be:	43db      	mvns	r3, r3
 80042c0:	69ba      	ldr	r2, [r7, #24]
 80042c2:	4013      	ands	r3, r2
 80042c4:	61bb      	str	r3, [r7, #24]
        temp |= (GPIO_Init->Speed << (position * 2U));
 80042c6:	683b      	ldr	r3, [r7, #0]
 80042c8:	68da      	ldr	r2, [r3, #12]
 80042ca:	69fb      	ldr	r3, [r7, #28]
 80042cc:	005b      	lsls	r3, r3, #1
 80042ce:	fa02 f303 	lsl.w	r3, r2, r3
 80042d2:	69ba      	ldr	r2, [r7, #24]
 80042d4:	4313      	orrs	r3, r2
 80042d6:	61bb      	str	r3, [r7, #24]
        GPIOx->OSPEEDR = temp;
 80042d8:	687b      	ldr	r3, [r7, #4]
 80042da:	69ba      	ldr	r2, [r7, #24]
 80042dc:	609a      	str	r2, [r3, #8]

        /* Configure the IO Output Type */
        temp = GPIOx->OTYPER;
 80042de:	687b      	ldr	r3, [r7, #4]
 80042e0:	685b      	ldr	r3, [r3, #4]
 80042e2:	61bb      	str	r3, [r7, #24]
        temp &= ~(GPIO_OTYPER_OT_0 << position) ;
 80042e4:	2201      	movs	r2, #1
 80042e6:	69fb      	ldr	r3, [r7, #28]
 80042e8:	fa02 f303 	lsl.w	r3, r2, r3
 80042ec:	43db      	mvns	r3, r3
 80042ee:	69ba      	ldr	r2, [r7, #24]
 80042f0:	4013      	ands	r3, r2
 80042f2:	61bb      	str	r3, [r7, #24]
        temp |= (((GPIO_Init->Mode & OUTPUT_TYPE) >> OUTPUT_TYPE_Pos) << position);
 80042f4:	683b      	ldr	r3, [r7, #0]
 80042f6:	685b      	ldr	r3, [r3, #4]
 80042f8:	091b      	lsrs	r3, r3, #4
 80042fa:	f003 0201 	and.w	r2, r3, #1
 80042fe:	69fb      	ldr	r3, [r7, #28]
 8004300:	fa02 f303 	lsl.w	r3, r2, r3
 8004304:	69ba      	ldr	r2, [r7, #24]
 8004306:	4313      	orrs	r3, r2
 8004308:	61bb      	str	r3, [r7, #24]
        GPIOx->OTYPER = temp;
 800430a:	687b      	ldr	r3, [r7, #4]
 800430c:	69ba      	ldr	r2, [r7, #24]
 800430e:	605a      	str	r2, [r3, #4]
       }

      if((GPIO_Init->Mode & GPIO_MODE) != MODE_ANALOG)
 8004310:	683b      	ldr	r3, [r7, #0]
 8004312:	685b      	ldr	r3, [r3, #4]
 8004314:	f003 0303 	and.w	r3, r3, #3
 8004318:	2b03      	cmp	r3, #3
 800431a:	d017      	beq.n	800434c <HAL_GPIO_Init+0xf0>
      {
        /* Check the parameters */
        assert_param(IS_GPIO_PULL(GPIO_Init->Pull));
        
        /* Activate the Pull-up or Pull down resistor for the current IO */
        temp = GPIOx->PUPDR;
 800431c:	687b      	ldr	r3, [r7, #4]
 800431e:	68db      	ldr	r3, [r3, #12]
 8004320:	61bb      	str	r3, [r7, #24]
        temp &= ~(GPIO_PUPDR_PUPDR0 << (position * 2U));
 8004322:	69fb      	ldr	r3, [r7, #28]
 8004324:	005b      	lsls	r3, r3, #1
 8004326:	2203      	movs	r2, #3
 8004328:	fa02 f303 	lsl.w	r3, r2, r3
 800432c:	43db      	mvns	r3, r3
 800432e:	69ba      	ldr	r2, [r7, #24]
 8004330:	4013      	ands	r3, r2
 8004332:	61bb      	str	r3, [r7, #24]
        temp |= ((GPIO_Init->Pull) << (position * 2U));
 8004334:	683b      	ldr	r3, [r7, #0]
 8004336:	689a      	ldr	r2, [r3, #8]
 8004338:	69fb      	ldr	r3, [r7, #28]
 800433a:	005b      	lsls	r3, r3, #1
 800433c:	fa02 f303 	lsl.w	r3, r2, r3
 8004340:	69ba      	ldr	r2, [r7, #24]
 8004342:	4313      	orrs	r3, r2
 8004344:	61bb      	str	r3, [r7, #24]
        GPIOx->PUPDR = temp;
 8004346:	687b      	ldr	r3, [r7, #4]
 8004348:	69ba      	ldr	r2, [r7, #24]
 800434a:	60da      	str	r2, [r3, #12]
      }

      /* In case of Alternate function mode selection */
      if((GPIO_Init->Mode & GPIO_MODE) == MODE_AF)
 800434c:	683b      	ldr	r3, [r7, #0]
 800434e:	685b      	ldr	r3, [r3, #4]
 8004350:	f003 0303 	and.w	r3, r3, #3
 8004354:	2b02      	cmp	r3, #2
 8004356:	d123      	bne.n	80043a0 <HAL_GPIO_Init+0x144>
      {
        /* Check the Alternate function parameter */
        assert_param(IS_GPIO_AF(GPIO_Init->Alternate));
        /* Configure Alternate function mapped with the current IO */
        temp = GPIOx->AFR[position >> 3U];
 8004358:	69fb      	ldr	r3, [r7, #28]
 800435a:	08da      	lsrs	r2, r3, #3
 800435c:	687b      	ldr	r3, [r7, #4]
 800435e:	3208      	adds	r2, #8
 8004360:	f853 3022 	ldr.w	r3, [r3, r2, lsl #2]
 8004364:	61bb      	str	r3, [r7, #24]
        temp &= ~(0xFU << ((uint32_t)(position & 0x07U) * 4U)) ;
 8004366:	69fb      	ldr	r3, [r7, #28]
 8004368:	f003 0307 	and.w	r3, r3, #7
 800436c:	009b      	lsls	r3, r3, #2
 800436e:	220f      	movs	r2, #15
 8004370:	fa02 f303 	lsl.w	r3, r2, r3
 8004374:	43db      	mvns	r3, r3
 8004376:	69ba      	ldr	r2, [r7, #24]
 8004378:	4013      	ands	r3, r2
 800437a:	61bb      	str	r3, [r7, #24]
        temp |= ((uint32_t)(GPIO_Init->Alternate) << (((uint32_t)position & 0x07U) * 4U));
 800437c:	683b      	ldr	r3, [r7, #0]
 800437e:	691a      	ldr	r2, [r3, #16]
 8004380:	69fb      	ldr	r3, [r7, #28]
 8004382:	f003 0307 	and.w	r3, r3, #7
 8004386:	009b      	lsls	r3, r3, #2
 8004388:	fa02 f303 	lsl.w	r3, r2, r3
 800438c:	69ba      	ldr	r2, [r7, #24]
 800438e:	4313      	orrs	r3, r2
 8004390:	61bb      	str	r3, [r7, #24]
        GPIOx->AFR[position >> 3U] = temp;
 8004392:	69fb      	ldr	r3, [r7, #28]
 8004394:	08da      	lsrs	r2, r3, #3
 8004396:	687b      	ldr	r3, [r7, #4]
 8004398:	3208      	adds	r2, #8
 800439a:	69b9      	ldr	r1, [r7, #24]
 800439c:	f843 1022 	str.w	r1, [r3, r2, lsl #2]
      }

      /* Configure IO Direction mode (Input, Output, Alternate or Analog) */
      temp = GPIOx->MODER;
 80043a0:	687b      	ldr	r3, [r7, #4]
 80043a2:	681b      	ldr	r3, [r3, #0]
 80043a4:	61bb      	str	r3, [r7, #24]
      temp &= ~(GPIO_MODER_MODER0 << (position * 2U));
 80043a6:	69fb      	ldr	r3, [r7, #28]
 80043a8:	005b      	lsls	r3, r3, #1
 80043aa:	2203      	movs	r2, #3
 80043ac:	fa02 f303 	lsl.w	r3, r2, r3
 80043b0:	43db      	mvns	r3, r3
 80043b2:	69ba      	ldr	r2, [r7, #24]
 80043b4:	4013      	ands	r3, r2
 80043b6:	61bb      	str	r3, [r7, #24]
      temp |= ((GPIO_Init->Mode & GPIO_MODE) << (position * 2U));
 80043b8:	683b      	ldr	r3, [r7, #0]
 80043ba:	685b      	ldr	r3, [r3, #4]
 80043bc:	f003 0203 	and.w	r2, r3, #3
 80043c0:	69fb      	ldr	r3, [r7, #28]
 80043c2:	005b      	lsls	r3, r3, #1
 80043c4:	fa02 f303 	lsl.w	r3, r2, r3
 80043c8:	69ba      	ldr	r2, [r7, #24]
 80043ca:	4313      	orrs	r3, r2
 80043cc:	61bb      	str	r3, [r7, #24]
      GPIOx->MODER = temp;
 80043ce:	687b      	ldr	r3, [r7, #4]
 80043d0:	69ba      	ldr	r2, [r7, #24]
 80043d2:	601a      	str	r2, [r3, #0]

      /*--------------------- EXTI Mode Configuration ------------------------*/
      /* Configure the External Interrupt or event for the current IO */
      if((GPIO_Init->Mode & EXTI_MODE) != 0x00U)
 80043d4:	683b      	ldr	r3, [r7, #0]
 80043d6:	685b      	ldr	r3, [r3, #4]
 80043d8:	f403 3340 	and.w	r3, r3, #196608	@ 0x30000
 80043dc:	2b00      	cmp	r3, #0
 80043de:	f000 80b4 	beq.w	800454a <HAL_GPIO_Init+0x2ee>
      {
        /* Enable SYSCFG Clock */
        __HAL_RCC_SYSCFG_CLK_ENABLE();
 80043e2:	2300      	movs	r3, #0
 80043e4:	60fb      	str	r3, [r7, #12]
 80043e6:	4b60      	ldr	r3, [pc, #384]	@ (8004568 <HAL_GPIO_Init+0x30c>)
 80043e8:	6c5b      	ldr	r3, [r3, #68]	@ 0x44
 80043ea:	4a5f      	ldr	r2, [pc, #380]	@ (8004568 <HAL_GPIO_Init+0x30c>)
 80043ec:	f443 4380 	orr.w	r3, r3, #16384	@ 0x4000
 80043f0:	6453      	str	r3, [r2, #68]	@ 0x44
 80043f2:	4b5d      	ldr	r3, [pc, #372]	@ (8004568 <HAL_GPIO_Init+0x30c>)
 80043f4:	6c5b      	ldr	r3, [r3, #68]	@ 0x44
 80043f6:	f403 4380 	and.w	r3, r3, #16384	@ 0x4000
 80043fa:	60fb      	str	r3, [r7, #12]
 80043fc:	68fb      	ldr	r3, [r7, #12]

        temp = SYSCFG->EXTICR[position >> 2U];
 80043fe:	4a5b      	ldr	r2, [pc, #364]	@ (800456c <HAL_GPIO_Init+0x310>)
 8004400:	69fb      	ldr	r3, [r7, #28]
 8004402:	089b      	lsrs	r3, r3, #2
 8004404:	3302      	adds	r3, #2
 8004406:	f852 3023 	ldr.w	r3, [r2, r3, lsl #2]
 800440a:	61bb      	str	r3, [r7, #24]
        temp &= ~(0x0FU << (4U * (position & 0x03U)));
 800440c:	69fb      	ldr	r3, [r7, #28]
 800440e:	f003 0303 	and.w	r3, r3, #3
 8004412:	009b      	lsls	r3, r3, #2
 8004414:	220f      	movs	r2, #15
 8004416:	fa02 f303 	lsl.w	r3, r2, r3
 800441a:	43db      	mvns	r3, r3
 800441c:	69ba      	ldr	r2, [r7, #24]
 800441e:	4013      	ands	r3, r2
 8004420:	61bb      	str	r3, [r7, #24]
        temp |= ((uint32_t)(GPIO_GET_INDEX(GPIOx)) << (4U * (position & 0x03U)));
 8004422:	687b      	ldr	r3, [r7, #4]
 8004424:	4a52      	ldr	r2, [pc, #328]	@ (8004570 <HAL_GPIO_Init+0x314>)
 8004426:	4293      	cmp	r3, r2
 8004428:	d02b      	beq.n	8004482 <HAL_GPIO_Init+0x226>
 800442a:	687b      	ldr	r3, [r7, #4]
 800442c:	4a51      	ldr	r2, [pc, #324]	@ (8004574 <HAL_GPIO_Init+0x318>)
 800442e:	4293      	cmp	r3, r2
 8004430:	d025      	beq.n	800447e <HAL_GPIO_Init+0x222>
 8004432:	687b      	ldr	r3, [r7, #4]
 8004434:	4a50      	ldr	r2, [pc, #320]	@ (8004578 <HAL_GPIO_Init+0x31c>)
 8004436:	4293      	cmp	r3, r2
 8004438:	d01f      	beq.n	800447a <HAL_GPIO_Init+0x21e>
 800443a:	687b      	ldr	r3, [r7, #4]
 800443c:	4a4f      	ldr	r2, [pc, #316]	@ (800457c <HAL_GPIO_Init+0x320>)
 800443e:	4293      	cmp	r3, r2
 8004440:	d019      	beq.n	8004476 <HAL_GPIO_Init+0x21a>
 8004442:	687b      	ldr	r3, [r7, #4]
 8004444:	4a4e      	ldr	r2, [pc, #312]	@ (8004580 <HAL_GPIO_Init+0x324>)
 8004446:	4293      	cmp	r3, r2
 8004448:	d013      	beq.n	8004472 <HAL_GPIO_Init+0x216>
 800444a:	687b      	ldr	r3, [r7, #4]
 800444c:	4a4d      	ldr	r2, [pc, #308]	@ (8004584 <HAL_GPIO_Init+0x328>)
 800444e:	4293      	cmp	r3, r2
 8004450:	d00d      	beq.n	800446e <HAL_GPIO_Init+0x212>
 8004452:	687b      	ldr	r3, [r7, #4]
 8004454:	4a4c      	ldr	r2, [pc, #304]	@ (8004588 <HAL_GPIO_Init+0x32c>)
 8004456:	4293      	cmp	r3, r2
 8004458:	d007      	beq.n	800446a <HAL_GPIO_Init+0x20e>
 800445a:	687b      	ldr	r3, [r7, #4]
 800445c:	4a4b      	ldr	r2, [pc, #300]	@ (800458c <HAL_GPIO_Init+0x330>)
 800445e:	4293      	cmp	r3, r2
 8004460:	d101      	bne.n	8004466 <HAL_GPIO_Init+0x20a>
 8004462:	2307      	movs	r3, #7
 8004464:	e00e      	b.n	8004484 <HAL_GPIO_Init+0x228>
 8004466:	2308      	movs	r3, #8
 8004468:	e00c      	b.n	8004484 <HAL_GPIO_Init+0x228>
 800446a:	2306      	movs	r3, #6
 800446c:	e00a      	b.n	8004484 <HAL_GPIO_Init+0x228>
 800446e:	2305      	movs	r3, #5
 8004470:	e008      	b.n	8004484 <HAL_GPIO_Init+0x228>
 8004472:	2304      	movs	r3, #4
 8004474:	e006      	b.n	8004484 <HAL_GPIO_Init+0x228>
 8004476:	2303      	movs	r3, #3
 8004478:	e004      	b.n	8004484 <HAL_GPIO_Init+0x228>
 800447a:	2302      	movs	r3, #2
 800447c:	e002      	b.n	8004484 <HAL_GPIO_Init+0x228>
 800447e:	2301      	movs	r3, #1
 8004480:	e000      	b.n	8004484 <HAL_GPIO_Init+0x228>
 8004482:	2300      	movs	r3, #0
 8004484:	69fa      	ldr	r2, [r7, #28]
 8004486:	f002 0203 	and.w	r2, r2, #3
 800448a:	0092      	lsls	r2, r2, #2
 800448c:	4093      	lsls	r3, r2
 800448e:	69ba      	ldr	r2, [r7, #24]
 8004490:	4313      	orrs	r3, r2
 8004492:	61bb      	str	r3, [r7, #24]
        SYSCFG->EXTICR[position >> 2U] = temp;
 8004494:	4935      	ldr	r1, [pc, #212]	@ (800456c <HAL_GPIO_Init+0x310>)
 8004496:	69fb      	ldr	r3, [r7, #28]
 8004498:	089b      	lsrs	r3, r3, #2
 800449a:	3302      	adds	r3, #2
 800449c:	69ba      	ldr	r2, [r7, #24]
 800449e:	f841 2023 	str.w	r2, [r1, r3, lsl #2]

        /* Clear Rising Falling edge configuration */
        temp = EXTI->RTSR;
 80044a2:	4b3b      	ldr	r3, [pc, #236]	@ (8004590 <HAL_GPIO_Init+0x334>)
 80044a4:	689b      	ldr	r3, [r3, #8]
 80044a6:	61bb      	str	r3, [r7, #24]
        temp &= ~((uint32_t)iocurrent);
 80044a8:	693b      	ldr	r3, [r7, #16]
 80044aa:	43db      	mvns	r3, r3
 80044ac:	69ba      	ldr	r2, [r7, #24]
 80044ae:	4013      	ands	r3, r2
 80044b0:	61bb      	str	r3, [r7, #24]
        if((GPIO_Init->Mode & TRIGGER_RISING) != 0x00U)
 80044b2:	683b      	ldr	r3, [r7, #0]
 80044b4:	685b      	ldr	r3, [r3, #4]
 80044b6:	f403 1380 	and.w	r3, r3, #1048576	@ 0x100000
 80044ba:	2b00      	cmp	r3, #0
 80044bc:	d003      	beq.n	80044c6 <HAL_GPIO_Init+0x26a>
        {
          temp |= iocurrent;
 80044be:	69ba      	ldr	r2, [r7, #24]
 80044c0:	693b      	ldr	r3, [r7, #16]
 80044c2:	4313      	orrs	r3, r2
 80044c4:	61bb      	str	r3, [r7, #24]
        }
        EXTI->RTSR = temp;
 80044c6:	4a32      	ldr	r2, [pc, #200]	@ (8004590 <HAL_GPIO_Init+0x334>)
 80044c8:	69bb      	ldr	r3, [r7, #24]
 80044ca:	6093      	str	r3, [r2, #8]

        temp = EXTI->FTSR;
 80044cc:	4b30      	ldr	r3, [pc, #192]	@ (8004590 <HAL_GPIO_Init+0x334>)
 80044ce:	68db      	ldr	r3, [r3, #12]
 80044d0:	61bb      	str	r3, [r7, #24]
        temp &= ~((uint32_t)iocurrent);
 80044d2:	693b      	ldr	r3, [r7, #16]
 80044d4:	43db      	mvns	r3, r3
 80044d6:	69ba      	ldr	r2, [r7, #24]
 80044d8:	4013      	ands	r3, r2
 80044da:	61bb      	str	r3, [r7, #24]
        if((GPIO_Init->Mode & TRIGGER_FALLING) != 0x00U)
 80044dc:	683b      	ldr	r3, [r7, #0]
 80044de:	685b      	ldr	r3, [r3, #4]
 80044e0:	f403 1300 	and.w	r3, r3, #2097152	@ 0x200000
 80044e4:	2b00      	cmp	r3, #0
 80044e6:	d003      	beq.n	80044f0 <HAL_GPIO_Init+0x294>
        {
          temp |= iocurrent;
 80044e8:	69ba      	ldr	r2, [r7, #24]
 80044ea:	693b      	ldr	r3, [r7, #16]
 80044ec:	4313      	orrs	r3, r2
 80044ee:	61bb      	str	r3, [r7, #24]
        }
        EXTI->FTSR = temp;
 80044f0:	4a27      	ldr	r2, [pc, #156]	@ (8004590 <HAL_GPIO_Init+0x334>)
 80044f2:	69bb      	ldr	r3, [r7, #24]
 80044f4:	60d3      	str	r3, [r2, #12]

        temp = EXTI->EMR;
 80044f6:	4b26      	ldr	r3, [pc, #152]	@ (8004590 <HAL_GPIO_Init+0x334>)
 80044f8:	685b      	ldr	r3, [r3, #4]
 80044fa:	61bb      	str	r3, [r7, #24]
        temp &= ~((uint32_t)iocurrent);
 80044fc:	693b      	ldr	r3, [r7, #16]
 80044fe:	43db      	mvns	r3, r3
 8004500:	69ba      	ldr	r2, [r7, #24]
 8004502:	4013      	ands	r3, r2
 8004504:	61bb      	str	r3, [r7, #24]
        if((GPIO_Init->Mode & EXTI_EVT) != 0x00U)
 8004506:	683b      	ldr	r3, [r7, #0]
 8004508:	685b      	ldr	r3, [r3, #4]
 800450a:	f403 3300 	and.w	r3, r3, #131072	@ 0x20000
 800450e:	2b00      	cmp	r3, #0
 8004510:	d003      	beq.n	800451a <HAL_GPIO_Init+0x2be>
        {
          temp |= iocurrent;
 8004512:	69ba      	ldr	r2, [r7, #24]
 8004514:	693b      	ldr	r3, [r7, #16]
 8004516:	4313      	orrs	r3, r2
 8004518:	61bb      	str	r3, [r7, #24]
        }
        EXTI->EMR = temp;
 800451a:	4a1d      	ldr	r2, [pc, #116]	@ (8004590 <HAL_GPIO_Init+0x334>)
 800451c:	69bb      	ldr	r3, [r7, #24]
 800451e:	6053      	str	r3, [r2, #4]

        /* Clear EXTI line configuration */
        temp = EXTI->IMR;
 8004520:	4b1b      	ldr	r3, [pc, #108]	@ (8004590 <HAL_GPIO_Init+0x334>)
 8004522:	681b      	ldr	r3, [r3, #0]
 8004524:	61bb      	str	r3, [r7, #24]
        temp &= ~((uint32_t)iocurrent);
 8004526:	693b      	ldr	r3, [r7, #16]
 8004528:	43db      	mvns	r3, r3
 800452a:	69ba      	ldr	r2, [r7, #24]
 800452c:	4013      	ands	r3, r2
 800452e:	61bb      	str	r3, [r7, #24]
        if((GPIO_Init->Mode & EXTI_IT) != 0x00U)
 8004530:	683b      	ldr	r3, [r7, #0]
 8004532:	685b      	ldr	r3, [r3, #4]
 8004534:	f403 3380 	and.w	r3, r3, #65536	@ 0x10000
 8004538:	2b00      	cmp	r3, #0
 800453a:	d003      	beq.n	8004544 <HAL_GPIO_Init+0x2e8>
        {
          temp |= iocurrent;
 800453c:	69ba      	ldr	r2, [r7, #24]
 800453e:	693b      	ldr	r3, [r7, #16]
 8004540:	4313      	orrs	r3, r2
 8004542:	61bb      	str	r3, [r7, #24]
        }
        EXTI->IMR = temp;
 8004544:	4a12      	ldr	r2, [pc, #72]	@ (8004590 <HAL_GPIO_Init+0x334>)
 8004546:	69bb      	ldr	r3, [r7, #24]
 8004548:	6013      	str	r3, [r2, #0]
  for(position = 0U; position < GPIO_NUMBER; position++)
 800454a:	69fb      	ldr	r3, [r7, #28]
 800454c:	3301      	adds	r3, #1
 800454e:	61fb      	str	r3, [r7, #28]
 8004550:	69fb      	ldr	r3, [r7, #28]
 8004552:	2b0f      	cmp	r3, #15
 8004554:	f67f ae90 	bls.w	8004278 <HAL_GPIO_Init+0x1c>
      }
    }
  }
}
 8004558:	bf00      	nop
 800455a:	bf00      	nop
 800455c:	3724      	adds	r7, #36	@ 0x24
 800455e:	46bd      	mov	sp, r7
 8004560:	f85d 7b04 	ldr.w	r7, [sp], #4
 8004564:	4770      	bx	lr
 8004566:	bf00      	nop
 8004568:	40023800 	.word	0x40023800
 800456c:	40013800 	.word	0x40013800
 8004570:	40020000 	.word	0x40020000
 8004574:	40020400 	.word	0x40020400
 8004578:	40020800 	.word	0x40020800
 800457c:	40020c00 	.word	0x40020c00
 8004580:	40021000 	.word	0x40021000
 8004584:	40021400 	.word	0x40021400
 8004588:	40021800 	.word	0x40021800
 800458c:	40021c00 	.word	0x40021c00
 8004590:	40013c00 	.word	0x40013c00

08004594 <HAL_GPIO_DeInit>:
  * @param  GPIO_Pin specifies the port bit to be written.
  *          This parameter can be one of GPIO_PIN_x where x can be (0..15).
  * @retval None
  */
void HAL_GPIO_DeInit(GPIO_TypeDef  *GPIOx, uint32_t GPIO_Pin)
{
 8004594:	b480      	push	{r7}
 8004596:	b087      	sub	sp, #28
 8004598:	af00      	add	r7, sp, #0
 800459a:	6078      	str	r0, [r7, #4]
 800459c:	6039      	str	r1, [r7, #0]
  uint32_t position;
  uint32_t ioposition = 0x00U;
 800459e:	2300      	movs	r3, #0
 80045a0:	613b      	str	r3, [r7, #16]
  uint32_t iocurrent = 0x00U;
 80045a2:	2300      	movs	r3, #0
 80045a4:	60fb      	str	r3, [r7, #12]
  uint32_t tmp = 0x00U;
 80045a6:	2300      	movs	r3, #0
 80045a8:	60bb      	str	r3, [r7, #8]

  /* Check the parameters */
  assert_param(IS_GPIO_ALL_INSTANCE(GPIOx));
  
  /* Configure the port pins */
  for(position = 0U; position < GPIO_NUMBER; position++)
 80045aa:	2300      	movs	r3, #0
 80045ac:	617b      	str	r3, [r7, #20]
 80045ae:	e0cd      	b.n	800474c <HAL_GPIO_DeInit+0x1b8>
  {
    /* Get the IO position */
    ioposition = 0x01U << position;
 80045b0:	2201      	movs	r2, #1
 80045b2:	697b      	ldr	r3, [r7, #20]
 80045b4:	fa02 f303 	lsl.w	r3, r2, r3
 80045b8:	613b      	str	r3, [r7, #16]
    /* Get the current IO position */
    iocurrent = (GPIO_Pin) & ioposition;
 80045ba:	683a      	ldr	r2, [r7, #0]
 80045bc:	693b      	ldr	r3, [r7, #16]
 80045be:	4013      	ands	r3, r2
 80045c0:	60fb      	str	r3, [r7, #12]

    if(iocurrent == ioposition)
 80045c2:	68fa      	ldr	r2, [r7, #12]
 80045c4:	693b      	ldr	r3, [r7, #16]
 80045c6:	429a      	cmp	r2, r3
 80045c8:	f040 80bd 	bne.w	8004746 <HAL_GPIO_DeInit+0x1b2>
    {
      /*------------------------- EXTI Mode Configuration --------------------*/
      tmp = SYSCFG->EXTICR[position >> 2U];
 80045cc:	4a65      	ldr	r2, [pc, #404]	@ (8004764 <HAL_GPIO_DeInit+0x1d0>)
 80045ce:	697b      	ldr	r3, [r7, #20]
 80045d0:	089b      	lsrs	r3, r3, #2
 80045d2:	3302      	adds	r3, #2
 80045d4:	f852 3023 	ldr.w	r3, [r2, r3, lsl #2]
 80045d8:	60bb      	str	r3, [r7, #8]
      tmp &= (0x0FU << (4U * (position & 0x03U)));
 80045da:	697b      	ldr	r3, [r7, #20]
 80045dc:	f003 0303 	and.w	r3, r3, #3
 80045e0:	009b      	lsls	r3, r3, #2
 80045e2:	220f      	movs	r2, #15
 80045e4:	fa02 f303 	lsl.w	r3, r2, r3
 80045e8:	68ba      	ldr	r2, [r7, #8]
 80045ea:	4013      	ands	r3, r2
 80045ec:	60bb      	str	r3, [r7, #8]
      if(tmp == ((uint32_t)(GPIO_GET_INDEX(GPIOx)) << (4U * (position & 0x03U))))
 80045ee:	687b      	ldr	r3, [r7, #4]
 80045f0:	4a5d      	ldr	r2, [pc, #372]	@ (8004768 <HAL_GPIO_DeInit+0x1d4>)
 80045f2:	4293      	cmp	r3, r2
 80045f4:	d02b      	beq.n	800464e <HAL_GPIO_DeInit+0xba>
 80045f6:	687b      	ldr	r3, [r7, #4]
 80045f8:	4a5c      	ldr	r2, [pc, #368]	@ (800476c <HAL_GPIO_DeInit+0x1d8>)
 80045fa:	4293      	cmp	r3, r2
 80045fc:	d025      	beq.n	800464a <HAL_GPIO_DeInit+0xb6>
 80045fe:	687b      	ldr	r3, [r7, #4]
 8004600:	4a5b      	ldr	r2, [pc, #364]	@ (8004770 <HAL_GPIO_DeInit+0x1dc>)
 8004602:	4293      	cmp	r3, r2
 8004604:	d01f      	beq.n	8004646 <HAL_GPIO_DeInit+0xb2>
 8004606:	687b      	ldr	r3, [r7, #4]
 8004608:	4a5a      	ldr	r2, [pc, #360]	@ (8004774 <HAL_GPIO_DeInit+0x1e0>)
 800460a:	4293      	cmp	r3, r2
 800460c:	d019      	beq.n	8004642 <HAL_GPIO_DeInit+0xae>
 800460e:	687b      	ldr	r3, [r7, #4]
 8004610:	4a59      	ldr	r2, [pc, #356]	@ (8004778 <HAL_GPIO_DeInit+0x1e4>)
 8004612:	4293      	cmp	r3, r2
 8004614:	d013      	beq.n	800463e <HAL_GPIO_DeInit+0xaa>
 8004616:	687b      	ldr	r3, [r7, #4]
 8004618:	4a58      	ldr	r2, [pc, #352]	@ (800477c <HAL_GPIO_DeInit+0x1e8>)
 800461a:	4293      	cmp	r3, r2
 800461c:	d00d      	beq.n	800463a <HAL_GPIO_DeInit+0xa6>
 800461e:	687b      	ldr	r3, [r7, #4]
 8004620:	4a57      	ldr	r2, [pc, #348]	@ (8004780 <HAL_GPIO_DeInit+0x1ec>)
 8004622:	4293      	cmp	r3, r2
 8004624:	d007      	beq.n	8004636 <HAL_GPIO_DeInit+0xa2>
 8004626:	687b      	ldr	r3, [r7, #4]
 8004628:	4a56      	ldr	r2, [pc, #344]	@ (8004784 <HAL_GPIO_DeInit+0x1f0>)
 800462a:	4293      	cmp	r3, r2
 800462c:	d101      	bne.n	8004632 <HAL_GPIO_DeInit+0x9e>
 800462e:	2307      	movs	r3, #7
 8004630:	e00e      	b.n	8004650 <HAL_GPIO_DeInit+0xbc>
 8004632:	2308      	movs	r3, #8
 8004634:	e00c      	b.n	8004650 <HAL_GPIO_DeInit+0xbc>
 8004636:	2306      	movs	r3, #6
 8004638:	e00a      	b.n	8004650 <HAL_GPIO_DeInit+0xbc>
 800463a:	2305      	movs	r3, #5
 800463c:	e008      	b.n	8004650 <HAL_GPIO_DeInit+0xbc>
 800463e:	2304      	movs	r3, #4
 8004640:	e006      	b.n	8004650 <HAL_GPIO_DeInit+0xbc>
 8004642:	2303      	movs	r3, #3
 8004644:	e004      	b.n	8004650 <HAL_GPIO_DeInit+0xbc>
 8004646:	2302      	movs	r3, #2
 8004648:	e002      	b.n	8004650 <HAL_GPIO_DeInit+0xbc>
 800464a:	2301      	movs	r3, #1
 800464c:	e000      	b.n	8004650 <HAL_GPIO_DeInit+0xbc>
 800464e:	2300      	movs	r3, #0
 8004650:	697a      	ldr	r2, [r7, #20]
 8004652:	f002 0203 	and.w	r2, r2, #3
 8004656:	0092      	lsls	r2, r2, #2
 8004658:	4093      	lsls	r3, r2
 800465a:	68ba      	ldr	r2, [r7, #8]
 800465c:	429a      	cmp	r2, r3
 800465e:	d132      	bne.n	80046c6 <HAL_GPIO_DeInit+0x132>
      {
        /* Clear EXTI line configuration */
        EXTI->IMR &= ~((uint32_t)iocurrent);
 8004660:	4b49      	ldr	r3, [pc, #292]	@ (8004788 <HAL_GPIO_DeInit+0x1f4>)
 8004662:	681a      	ldr	r2, [r3, #0]
 8004664:	68fb      	ldr	r3, [r7, #12]
 8004666:	43db      	mvns	r3, r3
 8004668:	4947      	ldr	r1, [pc, #284]	@ (8004788 <HAL_GPIO_DeInit+0x1f4>)
 800466a:	4013      	ands	r3, r2
 800466c:	600b      	str	r3, [r1, #0]
        EXTI->EMR &= ~((uint32_t)iocurrent);
 800466e:	4b46      	ldr	r3, [pc, #280]	@ (8004788 <HAL_GPIO_DeInit+0x1f4>)
 8004670:	685a      	ldr	r2, [r3, #4]
 8004672:	68fb      	ldr	r3, [r7, #12]
 8004674:	43db      	mvns	r3, r3
 8004676:	4944      	ldr	r1, [pc, #272]	@ (8004788 <HAL_GPIO_DeInit+0x1f4>)
 8004678:	4013      	ands	r3, r2
 800467a:	604b      	str	r3, [r1, #4]
        
        /* Clear Rising Falling edge configuration */
        EXTI->FTSR &= ~((uint32_t)iocurrent);
 800467c:	4b42      	ldr	r3, [pc, #264]	@ (8004788 <HAL_GPIO_DeInit+0x1f4>)
 800467e:	68da      	ldr	r2, [r3, #12]
 8004680:	68fb      	ldr	r3, [r7, #12]
 8004682:	43db      	mvns	r3, r3
 8004684:	4940      	ldr	r1, [pc, #256]	@ (8004788 <HAL_GPIO_DeInit+0x1f4>)
 8004686:	4013      	ands	r3, r2
 8004688:	60cb      	str	r3, [r1, #12]
        EXTI->RTSR &= ~((uint32_t)iocurrent);
 800468a:	4b3f      	ldr	r3, [pc, #252]	@ (8004788 <HAL_GPIO_DeInit+0x1f4>)
 800468c:	689a      	ldr	r2, [r3, #8]
 800468e:	68fb      	ldr	r3, [r7, #12]
 8004690:	43db      	mvns	r3, r3
 8004692:	493d      	ldr	r1, [pc, #244]	@ (8004788 <HAL_GPIO_DeInit+0x1f4>)
 8004694:	4013      	ands	r3, r2
 8004696:	608b      	str	r3, [r1, #8]

        /* Configure the External Interrupt or event for the current IO */
        tmp = 0x0FU << (4U * (position & 0x03U));
 8004698:	697b      	ldr	r3, [r7, #20]
 800469a:	f003 0303 	and.w	r3, r3, #3
 800469e:	009b      	lsls	r3, r3, #2
 80046a0:	220f      	movs	r2, #15
 80046a2:	fa02 f303 	lsl.w	r3, r2, r3
 80046a6:	60bb      	str	r3, [r7, #8]
        SYSCFG->EXTICR[position >> 2U] &= ~tmp;
 80046a8:	4a2e      	ldr	r2, [pc, #184]	@ (8004764 <HAL_GPIO_DeInit+0x1d0>)
 80046aa:	697b      	ldr	r3, [r7, #20]
 80046ac:	089b      	lsrs	r3, r3, #2
 80046ae:	3302      	adds	r3, #2
 80046b0:	f852 1023 	ldr.w	r1, [r2, r3, lsl #2]
 80046b4:	68bb      	ldr	r3, [r7, #8]
 80046b6:	43da      	mvns	r2, r3
 80046b8:	482a      	ldr	r0, [pc, #168]	@ (8004764 <HAL_GPIO_DeInit+0x1d0>)
 80046ba:	697b      	ldr	r3, [r7, #20]
 80046bc:	089b      	lsrs	r3, r3, #2
 80046be:	400a      	ands	r2, r1
 80046c0:	3302      	adds	r3, #2
 80046c2:	f840 2023 	str.w	r2, [r0, r3, lsl #2]
      }

      /*------------------------- GPIO Mode Configuration --------------------*/
      /* Configure IO Direction in Input Floating Mode */
      GPIOx->MODER &= ~(GPIO_MODER_MODER0 << (position * 2U));
 80046c6:	687b      	ldr	r3, [r7, #4]
 80046c8:	681a      	ldr	r2, [r3, #0]
 80046ca:	697b      	ldr	r3, [r7, #20]
 80046cc:	005b      	lsls	r3, r3, #1
 80046ce:	2103      	movs	r1, #3
 80046d0:	fa01 f303 	lsl.w	r3, r1, r3
 80046d4:	43db      	mvns	r3, r3
 80046d6:	401a      	ands	r2, r3
 80046d8:	687b      	ldr	r3, [r7, #4]
 80046da:	601a      	str	r2, [r3, #0]

      /* Configure the default Alternate Function in current IO */
      GPIOx->AFR[position >> 3U] &= ~(0xFU << ((uint32_t)(position & 0x07U) * 4U)) ;
 80046dc:	697b      	ldr	r3, [r7, #20]
 80046de:	08da      	lsrs	r2, r3, #3
 80046e0:	687b      	ldr	r3, [r7, #4]
 80046e2:	3208      	adds	r2, #8
 80046e4:	f853 1022 	ldr.w	r1, [r3, r2, lsl #2]
 80046e8:	697b      	ldr	r3, [r7, #20]
 80046ea:	f003 0307 	and.w	r3, r3, #7
 80046ee:	009b      	lsls	r3, r3, #2
 80046f0:	220f      	movs	r2, #15
 80046f2:	fa02 f303 	lsl.w	r3, r2, r3
 80046f6:	43db      	mvns	r3, r3
 80046f8:	697a      	ldr	r2, [r7, #20]
 80046fa:	08d2      	lsrs	r2, r2, #3
 80046fc:	4019      	ands	r1, r3
 80046fe:	687b      	ldr	r3, [r7, #4]
 8004700:	3208      	adds	r2, #8
 8004702:	f843 1022 	str.w	r1, [r3, r2, lsl #2]

      /* Deactivate the Pull-up and Pull-down resistor for the current IO */
      GPIOx->PUPDR &= ~(GPIO_PUPDR_PUPDR0 << (position * 2U));
 8004706:	687b      	ldr	r3, [r7, #4]
 8004708:	68da      	ldr	r2, [r3, #12]
 800470a:	697b      	ldr	r3, [r7, #20]
 800470c:	005b      	lsls	r3, r3, #1
 800470e:	2103      	movs	r1, #3
 8004710:	fa01 f303 	lsl.w	r3, r1, r3
 8004714:	43db      	mvns	r3, r3
 8004716:	401a      	ands	r2, r3
 8004718:	687b      	ldr	r3, [r7, #4]
 800471a:	60da      	str	r2, [r3, #12]

      /* Configure the default value IO Output Type */
      GPIOx->OTYPER  &= ~(GPIO_OTYPER_OT_0 << position) ;
 800471c:	687b      	ldr	r3, [r7, #4]
 800471e:	685a      	ldr	r2, [r3, #4]
 8004720:	2101      	movs	r1, #1
 8004722:	697b      	ldr	r3, [r7, #20]
 8004724:	fa01 f303 	lsl.w	r3, r1, r3
 8004728:	43db      	mvns	r3, r3
 800472a:	401a      	ands	r2, r3
 800472c:	687b      	ldr	r3, [r7, #4]
 800472e:	605a      	str	r2, [r3, #4]

      /* Configure the default value for IO Speed */
      GPIOx->OSPEEDR &= ~(GPIO_OSPEEDER_OSPEEDR0 << (position * 2U));
 8004730:	687b      	ldr	r3, [r7, #4]
 8004732:	689a      	ldr	r2, [r3, #8]
 8004734:	697b      	ldr	r3, [r7, #20]
 8004736:	005b      	lsls	r3, r3, #1
 8004738:	2103      	movs	r1, #3
 800473a:	fa01 f303 	lsl.w	r3, r1, r3
 800473e:	43db      	mvns	r3, r3
 8004740:	401a      	ands	r2, r3
 8004742:	687b      	ldr	r3, [r7, #4]
 8004744:	609a      	str	r2, [r3, #8]
  for(position = 0U; position < GPIO_NUMBER; position++)
 8004746:	697b      	ldr	r3, [r7, #20]
 8004748:	3301      	adds	r3, #1
 800474a:	617b      	str	r3, [r7, #20]
 800474c:	697b      	ldr	r3, [r7, #20]
 800474e:	2b0f      	cmp	r3, #15
 8004750:	f67f af2e 	bls.w	80045b0 <HAL_GPIO_DeInit+0x1c>
    }
  }
}
 8004754:	bf00      	nop
 8004756:	bf00      	nop
 8004758:	371c      	adds	r7, #28
 800475a:	46bd      	mov	sp, r7
 800475c:	f85d 7b04 	ldr.w	r7, [sp], #4
 8004760:	4770      	bx	lr
 8004762:	bf00      	nop
 8004764:	40013800 	.word	0x40013800
 8004768:	40020000 	.word	0x40020000
 800476c:	40020400 	.word	0x40020400
 8004770:	40020800 	.word	0x40020800
 8004774:	40020c00 	.word	0x40020c00
 8004778:	40021000 	.word	0x40021000
 800477c:	40021400 	.word	0x40021400
 8004780:	40021800 	.word	0x40021800
 8004784:	40021c00 	.word	0x40021c00
 8004788:	40013c00 	.word	0x40013c00

0800478c <HAL_RCC_OscConfig>:
  *         supported by this API. User should request a transition to HSE Off
  *         first and then HSE On or HSE Bypass.
  * @retval HAL status
  */
__weak HAL_StatusTypeDef HAL_RCC_OscConfig(const RCC_OscInitTypeDef  *RCC_OscInitStruct)
{
 800478c:	b580      	push	{r7, lr}
 800478e:	b086      	sub	sp, #24
 8004790:	af00      	add	r7, sp, #0
 8004792:	6078      	str	r0, [r7, #4]
  uint32_t tickstart;
  uint32_t pll_config;
  /* Check Null pointer */
  if (RCC_OscInitStruct == NULL)
 8004794:	687b      	ldr	r3, [r7, #4]
 8004796:	2b00      	cmp	r3, #0
 8004798:	d101      	bne.n	800479e <HAL_RCC_OscConfig+0x12>
  {
    return HAL_ERROR;
 800479a:	2301      	movs	r3, #1
 800479c:	e267      	b.n	8004c6e <HAL_RCC_OscConfig+0x4e2>
  }

  /* Check the parameters */
  assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType));
  /*------------------------------- HSE Configuration ------------------------*/
  if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE)
 800479e:	687b      	ldr	r3, [r7, #4]
 80047a0:	681b      	ldr	r3, [r3, #0]
 80047a2:	f003 0301 	and.w	r3, r3, #1
 80047a6:	2b00      	cmp	r3, #0
 80047a8:	d075      	beq.n	8004896 <HAL_RCC_OscConfig+0x10a>
  {
    /* Check the parameters */
    assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState));
    /* When the HSE is used as system clock or clock source for PLL in these cases HSE will not disabled */
    if ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSE) || \
 80047aa:	4b88      	ldr	r3, [pc, #544]	@ (80049cc <HAL_RCC_OscConfig+0x240>)
 80047ac:	689b      	ldr	r3, [r3, #8]
 80047ae:	f003 030c 	and.w	r3, r3, #12
 80047b2:	2b04      	cmp	r3, #4
 80047b4:	d00c      	beq.n	80047d0 <HAL_RCC_OscConfig+0x44>
        ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSE)))
 80047b6:	4b85      	ldr	r3, [pc, #532]	@ (80049cc <HAL_RCC_OscConfig+0x240>)
 80047b8:	689b      	ldr	r3, [r3, #8]
 80047ba:	f003 030c 	and.w	r3, r3, #12
    if ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSE) || \
 80047be:	2b08      	cmp	r3, #8
 80047c0:	d112      	bne.n	80047e8 <HAL_RCC_OscConfig+0x5c>
        ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSE)))
 80047c2:	4b82      	ldr	r3, [pc, #520]	@ (80049cc <HAL_RCC_OscConfig+0x240>)
 80047c4:	685b      	ldr	r3, [r3, #4]
 80047c6:	f403 0380 	and.w	r3, r3, #4194304	@ 0x400000
 80047ca:	f5b3 0f80 	cmp.w	r3, #4194304	@ 0x400000
 80047ce:	d10b      	bne.n	80047e8 <HAL_RCC_OscConfig+0x5c>
    {
      if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF))
 80047d0:	4b7e      	ldr	r3, [pc, #504]	@ (80049cc <HAL_RCC_OscConfig+0x240>)
 80047d2:	681b      	ldr	r3, [r3, #0]
 80047d4:	f403 3300 	and.w	r3, r3, #131072	@ 0x20000
 80047d8:	2b00      	cmp	r3, #0
 80047da:	d05b      	beq.n	8004894 <HAL_RCC_OscConfig+0x108>
 80047dc:	687b      	ldr	r3, [r7, #4]
 80047de:	685b      	ldr	r3, [r3, #4]
 80047e0:	2b00      	cmp	r3, #0
 80047e2:	d157      	bne.n	8004894 <HAL_RCC_OscConfig+0x108>
      {
        return HAL_ERROR;
 80047e4:	2301      	movs	r3, #1
 80047e6:	e242      	b.n	8004c6e <HAL_RCC_OscConfig+0x4e2>
      }
    }
    else
    {
      /* Set the new HSE configuration ---------------------------------------*/
      __HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState);
 80047e8:	687b      	ldr	r3, [r7, #4]
 80047ea:	685b      	ldr	r3, [r3, #4]
 80047ec:	f5b3 3f80 	cmp.w	r3, #65536	@ 0x10000
 80047f0:	d106      	bne.n	8004800 <HAL_RCC_OscConfig+0x74>
 80047f2:	4b76      	ldr	r3, [pc, #472]	@ (80049cc <HAL_RCC_OscConfig+0x240>)
 80047f4:	681b      	ldr	r3, [r3, #0]
 80047f6:	4a75      	ldr	r2, [pc, #468]	@ (80049cc <HAL_RCC_OscConfig+0x240>)
 80047f8:	f443 3380 	orr.w	r3, r3, #65536	@ 0x10000
 80047fc:	6013      	str	r3, [r2, #0]
 80047fe:	e01d      	b.n	800483c <HAL_RCC_OscConfig+0xb0>
 8004800:	687b      	ldr	r3, [r7, #4]
 8004802:	685b      	ldr	r3, [r3, #4]
 8004804:	f5b3 2fa0 	cmp.w	r3, #327680	@ 0x50000
 8004808:	d10c      	bne.n	8004824 <HAL_RCC_OscConfig+0x98>
 800480a:	4b70      	ldr	r3, [pc, #448]	@ (80049cc <HAL_RCC_OscConfig+0x240>)
 800480c:	681b      	ldr	r3, [r3, #0]
 800480e:	4a6f      	ldr	r2, [pc, #444]	@ (80049cc <HAL_RCC_OscConfig+0x240>)
 8004810:	f443 2380 	orr.w	r3, r3, #262144	@ 0x40000
 8004814:	6013      	str	r3, [r2, #0]
 8004816:	4b6d      	ldr	r3, [pc, #436]	@ (80049cc <HAL_RCC_OscConfig+0x240>)
 8004818:	681b      	ldr	r3, [r3, #0]
 800481a:	4a6c      	ldr	r2, [pc, #432]	@ (80049cc <HAL_RCC_OscConfig+0x240>)
 800481c:	f443 3380 	orr.w	r3, r3, #65536	@ 0x10000
 8004820:	6013      	str	r3, [r2, #0]
 8004822:	e00b      	b.n	800483c <HAL_RCC_OscConfig+0xb0>
 8004824:	4b69      	ldr	r3, [pc, #420]	@ (80049cc <HAL_RCC_OscConfig+0x240>)
 8004826:	681b      	ldr	r3, [r3, #0]
 8004828:	4a68      	ldr	r2, [pc, #416]	@ (80049cc <HAL_RCC_OscConfig+0x240>)
 800482a:	f423 3380 	bic.w	r3, r3, #65536	@ 0x10000
 800482e:	6013      	str	r3, [r2, #0]
 8004830:	4b66      	ldr	r3, [pc, #408]	@ (80049cc <HAL_RCC_OscConfig+0x240>)
 8004832:	681b      	ldr	r3, [r3, #0]
 8004834:	4a65      	ldr	r2, [pc, #404]	@ (80049cc <HAL_RCC_OscConfig+0x240>)
 8004836:	f423 2380 	bic.w	r3, r3, #262144	@ 0x40000
 800483a:	6013      	str	r3, [r2, #0]

      /* Check the HSE State */
      if ((RCC_OscInitStruct->HSEState) != RCC_HSE_OFF)
 800483c:	687b      	ldr	r3, [r7, #4]
 800483e:	685b      	ldr	r3, [r3, #4]
 8004840:	2b00      	cmp	r3, #0
 8004842:	d013      	beq.n	800486c <HAL_RCC_OscConfig+0xe0>
      {
        /* Get Start Tick */
        tickstart = HAL_GetTick();
 8004844:	f7fe fc80 	bl	8003148 <HAL_GetTick>
 8004848:	6138      	str	r0, [r7, #16]

        /* Wait till HSE is ready */
        while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
 800484a:	e008      	b.n	800485e <HAL_RCC_OscConfig+0xd2>
        {
          if ((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE)
 800484c:	f7fe fc7c 	bl	8003148 <HAL_GetTick>
 8004850:	4602      	mov	r2, r0
 8004852:	693b      	ldr	r3, [r7, #16]
 8004854:	1ad3      	subs	r3, r2, r3
 8004856:	2b64      	cmp	r3, #100	@ 0x64
 8004858:	d901      	bls.n	800485e <HAL_RCC_OscConfig+0xd2>
          {
            return HAL_TIMEOUT;
 800485a:	2303      	movs	r3, #3
 800485c:	e207      	b.n	8004c6e <HAL_RCC_OscConfig+0x4e2>
        while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
 800485e:	4b5b      	ldr	r3, [pc, #364]	@ (80049cc <HAL_RCC_OscConfig+0x240>)
 8004860:	681b      	ldr	r3, [r3, #0]
 8004862:	f403 3300 	and.w	r3, r3, #131072	@ 0x20000
 8004866:	2b00      	cmp	r3, #0
 8004868:	d0f0      	beq.n	800484c <HAL_RCC_OscConfig+0xc0>
 800486a:	e014      	b.n	8004896 <HAL_RCC_OscConfig+0x10a>
        }
      }
      else
      {
        /* Get Start Tick */
        tickstart = HAL_GetTick();
 800486c:	f7fe fc6c 	bl	8003148 <HAL_GetTick>
 8004870:	6138      	str	r0, [r7, #16]

        /* Wait till HSE is bypassed or disabled */
        while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET)
 8004872:	e008      	b.n	8004886 <HAL_RCC_OscConfig+0xfa>
        {
          if ((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE)
 8004874:	f7fe fc68 	bl	8003148 <HAL_GetTick>
 8004878:	4602      	mov	r2, r0
 800487a:	693b      	ldr	r3, [r7, #16]
 800487c:	1ad3      	subs	r3, r2, r3
 800487e:	2b64      	cmp	r3, #100	@ 0x64
 8004880:	d901      	bls.n	8004886 <HAL_RCC_OscConfig+0xfa>
          {
            return HAL_TIMEOUT;
 8004882:	2303      	movs	r3, #3
 8004884:	e1f3      	b.n	8004c6e <HAL_RCC_OscConfig+0x4e2>
        while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET)
 8004886:	4b51      	ldr	r3, [pc, #324]	@ (80049cc <HAL_RCC_OscConfig+0x240>)
 8004888:	681b      	ldr	r3, [r3, #0]
 800488a:	f403 3300 	and.w	r3, r3, #131072	@ 0x20000
 800488e:	2b00      	cmp	r3, #0
 8004890:	d1f0      	bne.n	8004874 <HAL_RCC_OscConfig+0xe8>
 8004892:	e000      	b.n	8004896 <HAL_RCC_OscConfig+0x10a>
      if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF))
 8004894:	bf00      	nop
        }
      }
    }
  }
  /*----------------------------- HSI Configuration --------------------------*/
  if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI)
 8004896:	687b      	ldr	r3, [r7, #4]
 8004898:	681b      	ldr	r3, [r3, #0]
 800489a:	f003 0302 	and.w	r3, r3, #2
 800489e:	2b00      	cmp	r3, #0
 80048a0:	d063      	beq.n	800496a <HAL_RCC_OscConfig+0x1de>
    /* Check the parameters */
    assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState));
    assert_param(IS_RCC_CALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue));

    /* Check if HSI is used as system clock or as PLL source when PLL is selected as system clock */
    if ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSI) || \
 80048a2:	4b4a      	ldr	r3, [pc, #296]	@ (80049cc <HAL_RCC_OscConfig+0x240>)
 80048a4:	689b      	ldr	r3, [r3, #8]
 80048a6:	f003 030c 	and.w	r3, r3, #12
 80048aa:	2b00      	cmp	r3, #0
 80048ac:	d00b      	beq.n	80048c6 <HAL_RCC_OscConfig+0x13a>
        ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSI)))
 80048ae:	4b47      	ldr	r3, [pc, #284]	@ (80049cc <HAL_RCC_OscConfig+0x240>)
 80048b0:	689b      	ldr	r3, [r3, #8]
 80048b2:	f003 030c 	and.w	r3, r3, #12
    if ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSI) || \
 80048b6:	2b08      	cmp	r3, #8
 80048b8:	d11c      	bne.n	80048f4 <HAL_RCC_OscConfig+0x168>
        ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSI)))
 80048ba:	4b44      	ldr	r3, [pc, #272]	@ (80049cc <HAL_RCC_OscConfig+0x240>)
 80048bc:	685b      	ldr	r3, [r3, #4]
 80048be:	f403 0380 	and.w	r3, r3, #4194304	@ 0x400000
 80048c2:	2b00      	cmp	r3, #0
 80048c4:	d116      	bne.n	80048f4 <HAL_RCC_OscConfig+0x168>
    {
      /* When HSI is used as system clock it will not disabled */
      if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON))
 80048c6:	4b41      	ldr	r3, [pc, #260]	@ (80049cc <HAL_RCC_OscConfig+0x240>)
 80048c8:	681b      	ldr	r3, [r3, #0]
 80048ca:	f003 0302 	and.w	r3, r3, #2
 80048ce:	2b00      	cmp	r3, #0
 80048d0:	d005      	beq.n	80048de <HAL_RCC_OscConfig+0x152>
 80048d2:	687b      	ldr	r3, [r7, #4]
 80048d4:	68db      	ldr	r3, [r3, #12]
 80048d6:	2b01      	cmp	r3, #1
 80048d8:	d001      	beq.n	80048de <HAL_RCC_OscConfig+0x152>
      {
        return HAL_ERROR;
 80048da:	2301      	movs	r3, #1
 80048dc:	e1c7      	b.n	8004c6e <HAL_RCC_OscConfig+0x4e2>
      }
      /* Otherwise, just the calibration is allowed */
      else
      {
        /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
        __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
 80048de:	4b3b      	ldr	r3, [pc, #236]	@ (80049cc <HAL_RCC_OscConfig+0x240>)
 80048e0:	681b      	ldr	r3, [r3, #0]
 80048e2:	f023 02f8 	bic.w	r2, r3, #248	@ 0xf8
 80048e6:	687b      	ldr	r3, [r7, #4]
 80048e8:	691b      	ldr	r3, [r3, #16]
 80048ea:	00db      	lsls	r3, r3, #3
 80048ec:	4937      	ldr	r1, [pc, #220]	@ (80049cc <HAL_RCC_OscConfig+0x240>)
 80048ee:	4313      	orrs	r3, r2
 80048f0:	600b      	str	r3, [r1, #0]
      if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON))
 80048f2:	e03a      	b.n	800496a <HAL_RCC_OscConfig+0x1de>
      }
    }
    else
    {
      /* Check the HSI State */
      if ((RCC_OscInitStruct->HSIState) != RCC_HSI_OFF)
 80048f4:	687b      	ldr	r3, [r7, #4]
 80048f6:	68db      	ldr	r3, [r3, #12]
 80048f8:	2b00      	cmp	r3, #0
 80048fa:	d020      	beq.n	800493e <HAL_RCC_OscConfig+0x1b2>
      {
        /* Enable the Internal High Speed oscillator (HSI). */
        __HAL_RCC_HSI_ENABLE();
 80048fc:	4b34      	ldr	r3, [pc, #208]	@ (80049d0 <HAL_RCC_OscConfig+0x244>)
 80048fe:	2201      	movs	r2, #1
 8004900:	601a      	str	r2, [r3, #0]

        /* Get Start Tick*/
        tickstart = HAL_GetTick();
 8004902:	f7fe fc21 	bl	8003148 <HAL_GetTick>
 8004906:	6138      	str	r0, [r7, #16]

        /* Wait till HSI is ready */
        while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
 8004908:	e008      	b.n	800491c <HAL_RCC_OscConfig+0x190>
        {
          if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE)
 800490a:	f7fe fc1d 	bl	8003148 <HAL_GetTick>
 800490e:	4602      	mov	r2, r0
 8004910:	693b      	ldr	r3, [r7, #16]
 8004912:	1ad3      	subs	r3, r2, r3
 8004914:	2b02      	cmp	r3, #2
 8004916:	d901      	bls.n	800491c <HAL_RCC_OscConfig+0x190>
          {
            return HAL_TIMEOUT;
 8004918:	2303      	movs	r3, #3
 800491a:	e1a8      	b.n	8004c6e <HAL_RCC_OscConfig+0x4e2>
        while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
 800491c:	4b2b      	ldr	r3, [pc, #172]	@ (80049cc <HAL_RCC_OscConfig+0x240>)
 800491e:	681b      	ldr	r3, [r3, #0]
 8004920:	f003 0302 	and.w	r3, r3, #2
 8004924:	2b00      	cmp	r3, #0
 8004926:	d0f0      	beq.n	800490a <HAL_RCC_OscConfig+0x17e>
          }
        }

        /* Adjusts the Internal High Speed oscillator (HSI) calibration value. */
        __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
 8004928:	4b28      	ldr	r3, [pc, #160]	@ (80049cc <HAL_RCC_OscConfig+0x240>)
 800492a:	681b      	ldr	r3, [r3, #0]
 800492c:	f023 02f8 	bic.w	r2, r3, #248	@ 0xf8
 8004930:	687b      	ldr	r3, [r7, #4]
 8004932:	691b      	ldr	r3, [r3, #16]
 8004934:	00db      	lsls	r3, r3, #3
 8004936:	4925      	ldr	r1, [pc, #148]	@ (80049cc <HAL_RCC_OscConfig+0x240>)
 8004938:	4313      	orrs	r3, r2
 800493a:	600b      	str	r3, [r1, #0]
 800493c:	e015      	b.n	800496a <HAL_RCC_OscConfig+0x1de>
      }
      else
      {
        /* Disable the Internal High Speed oscillator (HSI). */
        __HAL_RCC_HSI_DISABLE();
 800493e:	4b24      	ldr	r3, [pc, #144]	@ (80049d0 <HAL_RCC_OscConfig+0x244>)
 8004940:	2200      	movs	r2, #0
 8004942:	601a      	str	r2, [r3, #0]

        /* Get Start Tick*/
        tickstart = HAL_GetTick();
 8004944:	f7fe fc00 	bl	8003148 <HAL_GetTick>
 8004948:	6138      	str	r0, [r7, #16]

        /* Wait till HSI is ready */
        while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET)
 800494a:	e008      	b.n	800495e <HAL_RCC_OscConfig+0x1d2>
        {
          if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE)
 800494c:	f7fe fbfc 	bl	8003148 <HAL_GetTick>
 8004950:	4602      	mov	r2, r0
 8004952:	693b      	ldr	r3, [r7, #16]
 8004954:	1ad3      	subs	r3, r2, r3
 8004956:	2b02      	cmp	r3, #2
 8004958:	d901      	bls.n	800495e <HAL_RCC_OscConfig+0x1d2>
          {
            return HAL_TIMEOUT;
 800495a:	2303      	movs	r3, #3
 800495c:	e187      	b.n	8004c6e <HAL_RCC_OscConfig+0x4e2>
        while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET)
 800495e:	4b1b      	ldr	r3, [pc, #108]	@ (80049cc <HAL_RCC_OscConfig+0x240>)
 8004960:	681b      	ldr	r3, [r3, #0]
 8004962:	f003 0302 	and.w	r3, r3, #2
 8004966:	2b00      	cmp	r3, #0
 8004968:	d1f0      	bne.n	800494c <HAL_RCC_OscConfig+0x1c0>
        }
      }
    }
  }
  /*------------------------------ LSI Configuration -------------------------*/
  if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI)
 800496a:	687b      	ldr	r3, [r7, #4]
 800496c:	681b      	ldr	r3, [r3, #0]
 800496e:	f003 0308 	and.w	r3, r3, #8
 8004972:	2b00      	cmp	r3, #0
 8004974:	d036      	beq.n	80049e4 <HAL_RCC_OscConfig+0x258>
  {
    /* Check the parameters */
    assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState));

    /* Check the LSI State */
    if ((RCC_OscInitStruct->LSIState) != RCC_LSI_OFF)
 8004976:	687b      	ldr	r3, [r7, #4]
 8004978:	695b      	ldr	r3, [r3, #20]
 800497a:	2b00      	cmp	r3, #0
 800497c:	d016      	beq.n	80049ac <HAL_RCC_OscConfig+0x220>
    {
      /* Enable the Internal Low Speed oscillator (LSI). */
      __HAL_RCC_LSI_ENABLE();
 800497e:	4b15      	ldr	r3, [pc, #84]	@ (80049d4 <HAL_RCC_OscConfig+0x248>)
 8004980:	2201      	movs	r2, #1
 8004982:	601a      	str	r2, [r3, #0]

      /* Get Start Tick*/
      tickstart = HAL_GetTick();
 8004984:	f7fe fbe0 	bl	8003148 <HAL_GetTick>
 8004988:	6138      	str	r0, [r7, #16]

      /* Wait till LSI is ready */
      while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET)
 800498a:	e008      	b.n	800499e <HAL_RCC_OscConfig+0x212>
      {
        if ((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE)
 800498c:	f7fe fbdc 	bl	8003148 <HAL_GetTick>
 8004990:	4602      	mov	r2, r0
 8004992:	693b      	ldr	r3, [r7, #16]
 8004994:	1ad3      	subs	r3, r2, r3
 8004996:	2b02      	cmp	r3, #2
 8004998:	d901      	bls.n	800499e <HAL_RCC_OscConfig+0x212>
        {
          return HAL_TIMEOUT;
 800499a:	2303      	movs	r3, #3
 800499c:	e167      	b.n	8004c6e <HAL_RCC_OscConfig+0x4e2>
      while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET)
 800499e:	4b0b      	ldr	r3, [pc, #44]	@ (80049cc <HAL_RCC_OscConfig+0x240>)
 80049a0:	6f5b      	ldr	r3, [r3, #116]	@ 0x74
 80049a2:	f003 0302 	and.w	r3, r3, #2
 80049a6:	2b00      	cmp	r3, #0
 80049a8:	d0f0      	beq.n	800498c <HAL_RCC_OscConfig+0x200>
 80049aa:	e01b      	b.n	80049e4 <HAL_RCC_OscConfig+0x258>
      }
    }
    else
    {
      /* Disable the Internal Low Speed oscillator (LSI). */
      __HAL_RCC_LSI_DISABLE();
 80049ac:	4b09      	ldr	r3, [pc, #36]	@ (80049d4 <HAL_RCC_OscConfig+0x248>)
 80049ae:	2200      	movs	r2, #0
 80049b0:	601a      	str	r2, [r3, #0]

      /* Get Start Tick */
      tickstart = HAL_GetTick();
 80049b2:	f7fe fbc9 	bl	8003148 <HAL_GetTick>
 80049b6:	6138      	str	r0, [r7, #16]

      /* Wait till LSI is ready */
      while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET)
 80049b8:	e00e      	b.n	80049d8 <HAL_RCC_OscConfig+0x24c>
      {
        if ((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE)
 80049ba:	f7fe fbc5 	bl	8003148 <HAL_GetTick>
 80049be:	4602      	mov	r2, r0
 80049c0:	693b      	ldr	r3, [r7, #16]
 80049c2:	1ad3      	subs	r3, r2, r3
 80049c4:	2b02      	cmp	r3, #2
 80049c6:	d907      	bls.n	80049d8 <HAL_RCC_OscConfig+0x24c>
        {
          return HAL_TIMEOUT;
 80049c8:	2303      	movs	r3, #3
 80049ca:	e150      	b.n	8004c6e <HAL_RCC_OscConfig+0x4e2>
 80049cc:	40023800 	.word	0x40023800
 80049d0:	42470000 	.word	0x42470000
 80049d4:	42470e80 	.word	0x42470e80
      while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET)
 80049d8:	4b88      	ldr	r3, [pc, #544]	@ (8004bfc <HAL_RCC_OscConfig+0x470>)
 80049da:	6f5b      	ldr	r3, [r3, #116]	@ 0x74
 80049dc:	f003 0302 	and.w	r3, r3, #2
 80049e0:	2b00      	cmp	r3, #0
 80049e2:	d1ea      	bne.n	80049ba <HAL_RCC_OscConfig+0x22e>
        }
      }
    }
  }
  /*------------------------------ LSE Configuration -------------------------*/
  if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE)
 80049e4:	687b      	ldr	r3, [r7, #4]
 80049e6:	681b      	ldr	r3, [r3, #0]
 80049e8:	f003 0304 	and.w	r3, r3, #4
 80049ec:	2b00      	cmp	r3, #0
 80049ee:	f000 8097 	beq.w	8004b20 <HAL_RCC_OscConfig+0x394>
  {
    FlagStatus       pwrclkchanged = RESET;
 80049f2:	2300      	movs	r3, #0
 80049f4:	75fb      	strb	r3, [r7, #23]
    /* Check the parameters */
    assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState));

    /* Update LSE configuration in Backup Domain control register    */
    /* Requires to enable write access to Backup Domain of necessary */
    if (__HAL_RCC_PWR_IS_CLK_DISABLED())
 80049f6:	4b81      	ldr	r3, [pc, #516]	@ (8004bfc <HAL_RCC_OscConfig+0x470>)
 80049f8:	6c1b      	ldr	r3, [r3, #64]	@ 0x40
 80049fa:	f003 5380 	and.w	r3, r3, #268435456	@ 0x10000000
 80049fe:	2b00      	cmp	r3, #0
 8004a00:	d10f      	bne.n	8004a22 <HAL_RCC_OscConfig+0x296>
    {
      __HAL_RCC_PWR_CLK_ENABLE();
 8004a02:	2300      	movs	r3, #0
 8004a04:	60bb      	str	r3, [r7, #8]
 8004a06:	4b7d      	ldr	r3, [pc, #500]	@ (8004bfc <HAL_RCC_OscConfig+0x470>)
 8004a08:	6c1b      	ldr	r3, [r3, #64]	@ 0x40
 8004a0a:	4a7c      	ldr	r2, [pc, #496]	@ (8004bfc <HAL_RCC_OscConfig+0x470>)
 8004a0c:	f043 5380 	orr.w	r3, r3, #268435456	@ 0x10000000
 8004a10:	6413      	str	r3, [r2, #64]	@ 0x40
 8004a12:	4b7a      	ldr	r3, [pc, #488]	@ (8004bfc <HAL_RCC_OscConfig+0x470>)
 8004a14:	6c1b      	ldr	r3, [r3, #64]	@ 0x40
 8004a16:	f003 5380 	and.w	r3, r3, #268435456	@ 0x10000000
 8004a1a:	60bb      	str	r3, [r7, #8]
 8004a1c:	68bb      	ldr	r3, [r7, #8]
      pwrclkchanged = SET;
 8004a1e:	2301      	movs	r3, #1
 8004a20:	75fb      	strb	r3, [r7, #23]
    }

    if (HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
 8004a22:	4b77      	ldr	r3, [pc, #476]	@ (8004c00 <HAL_RCC_OscConfig+0x474>)
 8004a24:	681b      	ldr	r3, [r3, #0]
 8004a26:	f403 7380 	and.w	r3, r3, #256	@ 0x100
 8004a2a:	2b00      	cmp	r3, #0
 8004a2c:	d118      	bne.n	8004a60 <HAL_RCC_OscConfig+0x2d4>
    {
      /* Enable write access to Backup domain */
      SET_BIT(PWR->CR, PWR_CR_DBP);
 8004a2e:	4b74      	ldr	r3, [pc, #464]	@ (8004c00 <HAL_RCC_OscConfig+0x474>)
 8004a30:	681b      	ldr	r3, [r3, #0]
 8004a32:	4a73      	ldr	r2, [pc, #460]	@ (8004c00 <HAL_RCC_OscConfig+0x474>)
 8004a34:	f443 7380 	orr.w	r3, r3, #256	@ 0x100
 8004a38:	6013      	str	r3, [r2, #0]

      /* Wait for Backup domain Write protection disable */
      tickstart = HAL_GetTick();
 8004a3a:	f7fe fb85 	bl	8003148 <HAL_GetTick>
 8004a3e:	6138      	str	r0, [r7, #16]

      while (HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
 8004a40:	e008      	b.n	8004a54 <HAL_RCC_OscConfig+0x2c8>
      {
        if ((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE)
 8004a42:	f7fe fb81 	bl	8003148 <HAL_GetTick>
 8004a46:	4602      	mov	r2, r0
 8004a48:	693b      	ldr	r3, [r7, #16]
 8004a4a:	1ad3      	subs	r3, r2, r3
 8004a4c:	2b02      	cmp	r3, #2
 8004a4e:	d901      	bls.n	8004a54 <HAL_RCC_OscConfig+0x2c8>
        {
          return HAL_TIMEOUT;
 8004a50:	2303      	movs	r3, #3
 8004a52:	e10c      	b.n	8004c6e <HAL_RCC_OscConfig+0x4e2>
      while (HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
 8004a54:	4b6a      	ldr	r3, [pc, #424]	@ (8004c00 <HAL_RCC_OscConfig+0x474>)
 8004a56:	681b      	ldr	r3, [r3, #0]
 8004a58:	f403 7380 	and.w	r3, r3, #256	@ 0x100
 8004a5c:	2b00      	cmp	r3, #0
 8004a5e:	d0f0      	beq.n	8004a42 <HAL_RCC_OscConfig+0x2b6>
        }
      }
    }

    /* Set the new LSE configuration -----------------------------------------*/
    __HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState);
 8004a60:	687b      	ldr	r3, [r7, #4]
 8004a62:	689b      	ldr	r3, [r3, #8]
 8004a64:	2b01      	cmp	r3, #1
 8004a66:	d106      	bne.n	8004a76 <HAL_RCC_OscConfig+0x2ea>
 8004a68:	4b64      	ldr	r3, [pc, #400]	@ (8004bfc <HAL_RCC_OscConfig+0x470>)
 8004a6a:	6f1b      	ldr	r3, [r3, #112]	@ 0x70
 8004a6c:	4a63      	ldr	r2, [pc, #396]	@ (8004bfc <HAL_RCC_OscConfig+0x470>)
 8004a6e:	f043 0301 	orr.w	r3, r3, #1
 8004a72:	6713      	str	r3, [r2, #112]	@ 0x70
 8004a74:	e01c      	b.n	8004ab0 <HAL_RCC_OscConfig+0x324>
 8004a76:	687b      	ldr	r3, [r7, #4]
 8004a78:	689b      	ldr	r3, [r3, #8]
 8004a7a:	2b05      	cmp	r3, #5
 8004a7c:	d10c      	bne.n	8004a98 <HAL_RCC_OscConfig+0x30c>
 8004a7e:	4b5f      	ldr	r3, [pc, #380]	@ (8004bfc <HAL_RCC_OscConfig+0x470>)
 8004a80:	6f1b      	ldr	r3, [r3, #112]	@ 0x70
 8004a82:	4a5e      	ldr	r2, [pc, #376]	@ (8004bfc <HAL_RCC_OscConfig+0x470>)
 8004a84:	f043 0304 	orr.w	r3, r3, #4
 8004a88:	6713      	str	r3, [r2, #112]	@ 0x70
 8004a8a:	4b5c      	ldr	r3, [pc, #368]	@ (8004bfc <HAL_RCC_OscConfig+0x470>)
 8004a8c:	6f1b      	ldr	r3, [r3, #112]	@ 0x70
 8004a8e:	4a5b      	ldr	r2, [pc, #364]	@ (8004bfc <HAL_RCC_OscConfig+0x470>)
 8004a90:	f043 0301 	orr.w	r3, r3, #1
 8004a94:	6713      	str	r3, [r2, #112]	@ 0x70
 8004a96:	e00b      	b.n	8004ab0 <HAL_RCC_OscConfig+0x324>
 8004a98:	4b58      	ldr	r3, [pc, #352]	@ (8004bfc <HAL_RCC_OscConfig+0x470>)
 8004a9a:	6f1b      	ldr	r3, [r3, #112]	@ 0x70
 8004a9c:	4a57      	ldr	r2, [pc, #348]	@ (8004bfc <HAL_RCC_OscConfig+0x470>)
 8004a9e:	f023 0301 	bic.w	r3, r3, #1
 8004aa2:	6713      	str	r3, [r2, #112]	@ 0x70
 8004aa4:	4b55      	ldr	r3, [pc, #340]	@ (8004bfc <HAL_RCC_OscConfig+0x470>)
 8004aa6:	6f1b      	ldr	r3, [r3, #112]	@ 0x70
 8004aa8:	4a54      	ldr	r2, [pc, #336]	@ (8004bfc <HAL_RCC_OscConfig+0x470>)
 8004aaa:	f023 0304 	bic.w	r3, r3, #4
 8004aae:	6713      	str	r3, [r2, #112]	@ 0x70
    /* Check the LSE State */
    if ((RCC_OscInitStruct->LSEState) != RCC_LSE_OFF)
 8004ab0:	687b      	ldr	r3, [r7, #4]
 8004ab2:	689b      	ldr	r3, [r3, #8]
 8004ab4:	2b00      	cmp	r3, #0
 8004ab6:	d015      	beq.n	8004ae4 <HAL_RCC_OscConfig+0x358>
    {
      /* Get Start Tick*/
      tickstart = HAL_GetTick();
 8004ab8:	f7fe fb46 	bl	8003148 <HAL_GetTick>
 8004abc:	6138      	str	r0, [r7, #16]

      /* Wait till LSE is ready */
      while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
 8004abe:	e00a      	b.n	8004ad6 <HAL_RCC_OscConfig+0x34a>
      {
        if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE)
 8004ac0:	f7fe fb42 	bl	8003148 <HAL_GetTick>
 8004ac4:	4602      	mov	r2, r0
 8004ac6:	693b      	ldr	r3, [r7, #16]
 8004ac8:	1ad3      	subs	r3, r2, r3
 8004aca:	f241 3288 	movw	r2, #5000	@ 0x1388
 8004ace:	4293      	cmp	r3, r2
 8004ad0:	d901      	bls.n	8004ad6 <HAL_RCC_OscConfig+0x34a>
        {
          return HAL_TIMEOUT;
 8004ad2:	2303      	movs	r3, #3
 8004ad4:	e0cb      	b.n	8004c6e <HAL_RCC_OscConfig+0x4e2>
      while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
 8004ad6:	4b49      	ldr	r3, [pc, #292]	@ (8004bfc <HAL_RCC_OscConfig+0x470>)
 8004ad8:	6f1b      	ldr	r3, [r3, #112]	@ 0x70
 8004ada:	f003 0302 	and.w	r3, r3, #2
 8004ade:	2b00      	cmp	r3, #0
 8004ae0:	d0ee      	beq.n	8004ac0 <HAL_RCC_OscConfig+0x334>
 8004ae2:	e014      	b.n	8004b0e <HAL_RCC_OscConfig+0x382>
      }
    }
    else
    {
      /* Get Start Tick */
      tickstart = HAL_GetTick();
 8004ae4:	f7fe fb30 	bl	8003148 <HAL_GetTick>
 8004ae8:	6138      	str	r0, [r7, #16]

      /* Wait till LSE is ready */
      while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET)
 8004aea:	e00a      	b.n	8004b02 <HAL_RCC_OscConfig+0x376>
      {
        if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE)
 8004aec:	f7fe fb2c 	bl	8003148 <HAL_GetTick>
 8004af0:	4602      	mov	r2, r0
 8004af2:	693b      	ldr	r3, [r7, #16]
 8004af4:	1ad3      	subs	r3, r2, r3
 8004af6:	f241 3288 	movw	r2, #5000	@ 0x1388
 8004afa:	4293      	cmp	r3, r2
 8004afc:	d901      	bls.n	8004b02 <HAL_RCC_OscConfig+0x376>
        {
          return HAL_TIMEOUT;
 8004afe:	2303      	movs	r3, #3
 8004b00:	e0b5      	b.n	8004c6e <HAL_RCC_OscConfig+0x4e2>
      while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET)
 8004b02:	4b3e      	ldr	r3, [pc, #248]	@ (8004bfc <HAL_RCC_OscConfig+0x470>)
 8004b04:	6f1b      	ldr	r3, [r3, #112]	@ 0x70
 8004b06:	f003 0302 	and.w	r3, r3, #2
 8004b0a:	2b00      	cmp	r3, #0
 8004b0c:	d1ee      	bne.n	8004aec <HAL_RCC_OscConfig+0x360>
        }
      }
    }

    /* Restore clock configuration if changed */
    if (pwrclkchanged == SET)
 8004b0e:	7dfb      	ldrb	r3, [r7, #23]
 8004b10:	2b01      	cmp	r3, #1
 8004b12:	d105      	bne.n	8004b20 <HAL_RCC_OscConfig+0x394>
    {
      __HAL_RCC_PWR_CLK_DISABLE();
 8004b14:	4b39      	ldr	r3, [pc, #228]	@ (8004bfc <HAL_RCC_OscConfig+0x470>)
 8004b16:	6c1b      	ldr	r3, [r3, #64]	@ 0x40
 8004b18:	4a38      	ldr	r2, [pc, #224]	@ (8004bfc <HAL_RCC_OscConfig+0x470>)
 8004b1a:	f023 5380 	bic.w	r3, r3, #268435456	@ 0x10000000
 8004b1e:	6413      	str	r3, [r2, #64]	@ 0x40
    }
  }
  /*-------------------------------- PLL Configuration -----------------------*/
  /* Check the parameters */
  assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL.PLLState));
  if ((RCC_OscInitStruct->PLL.PLLState) != RCC_PLL_NONE)
 8004b20:	687b      	ldr	r3, [r7, #4]
 8004b22:	699b      	ldr	r3, [r3, #24]
 8004b24:	2b00      	cmp	r3, #0
 8004b26:	f000 80a1 	beq.w	8004c6c <HAL_RCC_OscConfig+0x4e0>
  {
    /* Check if the PLL is used as system clock or not */
    if (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_CFGR_SWS_PLL)
 8004b2a:	4b34      	ldr	r3, [pc, #208]	@ (8004bfc <HAL_RCC_OscConfig+0x470>)
 8004b2c:	689b      	ldr	r3, [r3, #8]
 8004b2e:	f003 030c 	and.w	r3, r3, #12
 8004b32:	2b08      	cmp	r3, #8
 8004b34:	d05c      	beq.n	8004bf0 <HAL_RCC_OscConfig+0x464>
    {
      if ((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_ON)
 8004b36:	687b      	ldr	r3, [r7, #4]
 8004b38:	699b      	ldr	r3, [r3, #24]
 8004b3a:	2b02      	cmp	r3, #2
 8004b3c:	d141      	bne.n	8004bc2 <HAL_RCC_OscConfig+0x436>
        assert_param(IS_RCC_PLLN_VALUE(RCC_OscInitStruct->PLL.PLLN));
        assert_param(IS_RCC_PLLP_VALUE(RCC_OscInitStruct->PLL.PLLP));
        assert_param(IS_RCC_PLLQ_VALUE(RCC_OscInitStruct->PLL.PLLQ));

        /* Disable the main PLL. */
        __HAL_RCC_PLL_DISABLE();
 8004b3e:	4b31      	ldr	r3, [pc, #196]	@ (8004c04 <HAL_RCC_OscConfig+0x478>)
 8004b40:	2200      	movs	r2, #0
 8004b42:	601a      	str	r2, [r3, #0]

        /* Get Start Tick */
        tickstart = HAL_GetTick();
 8004b44:	f7fe fb00 	bl	8003148 <HAL_GetTick>
 8004b48:	6138      	str	r0, [r7, #16]

        /* Wait till PLL is disabled */
        while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
 8004b4a:	e008      	b.n	8004b5e <HAL_RCC_OscConfig+0x3d2>
        {
          if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
 8004b4c:	f7fe fafc 	bl	8003148 <HAL_GetTick>
 8004b50:	4602      	mov	r2, r0
 8004b52:	693b      	ldr	r3, [r7, #16]
 8004b54:	1ad3      	subs	r3, r2, r3
 8004b56:	2b02      	cmp	r3, #2
 8004b58:	d901      	bls.n	8004b5e <HAL_RCC_OscConfig+0x3d2>
          {
            return HAL_TIMEOUT;
 8004b5a:	2303      	movs	r3, #3
 8004b5c:	e087      	b.n	8004c6e <HAL_RCC_OscConfig+0x4e2>
        while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
 8004b5e:	4b27      	ldr	r3, [pc, #156]	@ (8004bfc <HAL_RCC_OscConfig+0x470>)
 8004b60:	681b      	ldr	r3, [r3, #0]
 8004b62:	f003 7300 	and.w	r3, r3, #33554432	@ 0x2000000
 8004b66:	2b00      	cmp	r3, #0
 8004b68:	d1f0      	bne.n	8004b4c <HAL_RCC_OscConfig+0x3c0>
          }
        }

        /* Configure the main PLL clock source, multiplication and division factors. */
        WRITE_REG(RCC->PLLCFGR, (RCC_OscInitStruct->PLL.PLLSource                                            | \
 8004b6a:	687b      	ldr	r3, [r7, #4]
 8004b6c:	69da      	ldr	r2, [r3, #28]
 8004b6e:	687b      	ldr	r3, [r7, #4]
 8004b70:	6a1b      	ldr	r3, [r3, #32]
 8004b72:	431a      	orrs	r2, r3
 8004b74:	687b      	ldr	r3, [r7, #4]
 8004b76:	6a5b      	ldr	r3, [r3, #36]	@ 0x24
 8004b78:	019b      	lsls	r3, r3, #6
 8004b7a:	431a      	orrs	r2, r3
 8004b7c:	687b      	ldr	r3, [r7, #4]
 8004b7e:	6a9b      	ldr	r3, [r3, #40]	@ 0x28
 8004b80:	085b      	lsrs	r3, r3, #1
 8004b82:	3b01      	subs	r3, #1
 8004b84:	041b      	lsls	r3, r3, #16
 8004b86:	431a      	orrs	r2, r3
 8004b88:	687b      	ldr	r3, [r7, #4]
 8004b8a:	6adb      	ldr	r3, [r3, #44]	@ 0x2c
 8004b8c:	061b      	lsls	r3, r3, #24
 8004b8e:	491b      	ldr	r1, [pc, #108]	@ (8004bfc <HAL_RCC_OscConfig+0x470>)
 8004b90:	4313      	orrs	r3, r2
 8004b92:	604b      	str	r3, [r1, #4]
                                 RCC_OscInitStruct->PLL.PLLM                                                 | \
                                 (RCC_OscInitStruct->PLL.PLLN << RCC_PLLCFGR_PLLN_Pos)             | \
                                 (((RCC_OscInitStruct->PLL.PLLP >> 1U) - 1U) << RCC_PLLCFGR_PLLP_Pos) | \
                                 (RCC_OscInitStruct->PLL.PLLQ << RCC_PLLCFGR_PLLQ_Pos)));
        /* Enable the main PLL. */
        __HAL_RCC_PLL_ENABLE();
 8004b94:	4b1b      	ldr	r3, [pc, #108]	@ (8004c04 <HAL_RCC_OscConfig+0x478>)
 8004b96:	2201      	movs	r2, #1
 8004b98:	601a      	str	r2, [r3, #0]

        /* Get Start Tick */
        tickstart = HAL_GetTick();
 8004b9a:	f7fe fad5 	bl	8003148 <HAL_GetTick>
 8004b9e:	6138      	str	r0, [r7, #16]

        /* Wait till PLL is ready */
        while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
 8004ba0:	e008      	b.n	8004bb4 <HAL_RCC_OscConfig+0x428>
        {
          if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
 8004ba2:	f7fe fad1 	bl	8003148 <HAL_GetTick>
 8004ba6:	4602      	mov	r2, r0
 8004ba8:	693b      	ldr	r3, [r7, #16]
 8004baa:	1ad3      	subs	r3, r2, r3
 8004bac:	2b02      	cmp	r3, #2
 8004bae:	d901      	bls.n	8004bb4 <HAL_RCC_OscConfig+0x428>
          {
            return HAL_TIMEOUT;
 8004bb0:	2303      	movs	r3, #3
 8004bb2:	e05c      	b.n	8004c6e <HAL_RCC_OscConfig+0x4e2>
        while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
 8004bb4:	4b11      	ldr	r3, [pc, #68]	@ (8004bfc <HAL_RCC_OscConfig+0x470>)
 8004bb6:	681b      	ldr	r3, [r3, #0]
 8004bb8:	f003 7300 	and.w	r3, r3, #33554432	@ 0x2000000
 8004bbc:	2b00      	cmp	r3, #0
 8004bbe:	d0f0      	beq.n	8004ba2 <HAL_RCC_OscConfig+0x416>
 8004bc0:	e054      	b.n	8004c6c <HAL_RCC_OscConfig+0x4e0>
        }
      }
      else
      {
        /* Disable the main PLL. */
        __HAL_RCC_PLL_DISABLE();
 8004bc2:	4b10      	ldr	r3, [pc, #64]	@ (8004c04 <HAL_RCC_OscConfig+0x478>)
 8004bc4:	2200      	movs	r2, #0
 8004bc6:	601a      	str	r2, [r3, #0]

        /* Get Start Tick */
        tickstart = HAL_GetTick();
 8004bc8:	f7fe fabe 	bl	8003148 <HAL_GetTick>
 8004bcc:	6138      	str	r0, [r7, #16]

        /* Wait till PLL is disabled */
        while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
 8004bce:	e008      	b.n	8004be2 <HAL_RCC_OscConfig+0x456>
        {
          if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
 8004bd0:	f7fe faba 	bl	8003148 <HAL_GetTick>
 8004bd4:	4602      	mov	r2, r0
 8004bd6:	693b      	ldr	r3, [r7, #16]
 8004bd8:	1ad3      	subs	r3, r2, r3
 8004bda:	2b02      	cmp	r3, #2
 8004bdc:	d901      	bls.n	8004be2 <HAL_RCC_OscConfig+0x456>
          {
            return HAL_TIMEOUT;
 8004bde:	2303      	movs	r3, #3
 8004be0:	e045      	b.n	8004c6e <HAL_RCC_OscConfig+0x4e2>
        while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
 8004be2:	4b06      	ldr	r3, [pc, #24]	@ (8004bfc <HAL_RCC_OscConfig+0x470>)
 8004be4:	681b      	ldr	r3, [r3, #0]
 8004be6:	f003 7300 	and.w	r3, r3, #33554432	@ 0x2000000
 8004bea:	2b00      	cmp	r3, #0
 8004bec:	d1f0      	bne.n	8004bd0 <HAL_RCC_OscConfig+0x444>
 8004bee:	e03d      	b.n	8004c6c <HAL_RCC_OscConfig+0x4e0>
      }
    }
    else
    {
      /* Check if there is a request to disable the PLL used as System clock source */
      if ((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF)
 8004bf0:	687b      	ldr	r3, [r7, #4]
 8004bf2:	699b      	ldr	r3, [r3, #24]
 8004bf4:	2b01      	cmp	r3, #1
 8004bf6:	d107      	bne.n	8004c08 <HAL_RCC_OscConfig+0x47c>
      {
        return HAL_ERROR;
 8004bf8:	2301      	movs	r3, #1
 8004bfa:	e038      	b.n	8004c6e <HAL_RCC_OscConfig+0x4e2>
 8004bfc:	40023800 	.word	0x40023800
 8004c00:	40007000 	.word	0x40007000
 8004c04:	42470060 	.word	0x42470060
      }
      else
      {
        /* Do not return HAL_ERROR if request repeats the current configuration */
        pll_config = RCC->PLLCFGR;
 8004c08:	4b1b      	ldr	r3, [pc, #108]	@ (8004c78 <HAL_RCC_OscConfig+0x4ec>)
 8004c0a:	685b      	ldr	r3, [r3, #4]
 8004c0c:	60fb      	str	r3, [r7, #12]
            (READ_BIT(pll_config, RCC_PLLCFGR_PLLN) != (RCC_OscInitStruct->PLL.PLLN) << RCC_PLLCFGR_PLLN_Pos) ||
            (READ_BIT(pll_config, RCC_PLLCFGR_PLLP) != (((RCC_OscInitStruct->PLL.PLLP >> 1U) - 1U)) << RCC_PLLCFGR_PLLP_Pos) ||
            (READ_BIT(pll_config, RCC_PLLCFGR_PLLQ) != (RCC_OscInitStruct->PLL.PLLQ << RCC_PLLCFGR_PLLQ_Pos)) ||
            (READ_BIT(pll_config, RCC_PLLCFGR_PLLR) != (RCC_OscInitStruct->PLL.PLLR << RCC_PLLCFGR_PLLR_Pos)))
#else
        if (((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF) ||
 8004c0e:	687b      	ldr	r3, [r7, #4]
 8004c10:	699b      	ldr	r3, [r3, #24]
 8004c12:	2b01      	cmp	r3, #1
 8004c14:	d028      	beq.n	8004c68 <HAL_RCC_OscConfig+0x4dc>
            (READ_BIT(pll_config, RCC_PLLCFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) ||
 8004c16:	68fb      	ldr	r3, [r7, #12]
 8004c18:	f403 0280 	and.w	r2, r3, #4194304	@ 0x400000
 8004c1c:	687b      	ldr	r3, [r7, #4]
 8004c1e:	69db      	ldr	r3, [r3, #28]
        if (((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF) ||
 8004c20:	429a      	cmp	r2, r3
 8004c22:	d121      	bne.n	8004c68 <HAL_RCC_OscConfig+0x4dc>
            (READ_BIT(pll_config, RCC_PLLCFGR_PLLM) != (RCC_OscInitStruct->PLL.PLLM) << RCC_PLLCFGR_PLLM_Pos) ||
 8004c24:	68fb      	ldr	r3, [r7, #12]
 8004c26:	f003 023f 	and.w	r2, r3, #63	@ 0x3f
 8004c2a:	687b      	ldr	r3, [r7, #4]
 8004c2c:	6a1b      	ldr	r3, [r3, #32]
            (READ_BIT(pll_config, RCC_PLLCFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) ||
 8004c2e:	429a      	cmp	r2, r3
 8004c30:	d11a      	bne.n	8004c68 <HAL_RCC_OscConfig+0x4dc>
            (READ_BIT(pll_config, RCC_PLLCFGR_PLLN) != (RCC_OscInitStruct->PLL.PLLN) << RCC_PLLCFGR_PLLN_Pos) ||
 8004c32:	68fa      	ldr	r2, [r7, #12]
 8004c34:	f647 73c0 	movw	r3, #32704	@ 0x7fc0
 8004c38:	4013      	ands	r3, r2
 8004c3a:	687a      	ldr	r2, [r7, #4]
 8004c3c:	6a52      	ldr	r2, [r2, #36]	@ 0x24
 8004c3e:	0192      	lsls	r2, r2, #6
            (READ_BIT(pll_config, RCC_PLLCFGR_PLLM) != (RCC_OscInitStruct->PLL.PLLM) << RCC_PLLCFGR_PLLM_Pos) ||
 8004c40:	4293      	cmp	r3, r2
 8004c42:	d111      	bne.n	8004c68 <HAL_RCC_OscConfig+0x4dc>
            (READ_BIT(pll_config, RCC_PLLCFGR_PLLP) != (((RCC_OscInitStruct->PLL.PLLP >> 1U) - 1U)) << RCC_PLLCFGR_PLLP_Pos) ||
 8004c44:	68fb      	ldr	r3, [r7, #12]
 8004c46:	f403 3240 	and.w	r2, r3, #196608	@ 0x30000
 8004c4a:	687b      	ldr	r3, [r7, #4]
 8004c4c:	6a9b      	ldr	r3, [r3, #40]	@ 0x28
 8004c4e:	085b      	lsrs	r3, r3, #1
 8004c50:	3b01      	subs	r3, #1
 8004c52:	041b      	lsls	r3, r3, #16
            (READ_BIT(pll_config, RCC_PLLCFGR_PLLN) != (RCC_OscInitStruct->PLL.PLLN) << RCC_PLLCFGR_PLLN_Pos) ||
 8004c54:	429a      	cmp	r2, r3
 8004c56:	d107      	bne.n	8004c68 <HAL_RCC_OscConfig+0x4dc>
            (READ_BIT(pll_config, RCC_PLLCFGR_PLLQ) != (RCC_OscInitStruct->PLL.PLLQ << RCC_PLLCFGR_PLLQ_Pos)))
 8004c58:	68fb      	ldr	r3, [r7, #12]
 8004c5a:	f003 6270 	and.w	r2, r3, #251658240	@ 0xf000000
 8004c5e:	687b      	ldr	r3, [r7, #4]
 8004c60:	6adb      	ldr	r3, [r3, #44]	@ 0x2c
 8004c62:	061b      	lsls	r3, r3, #24
            (READ_BIT(pll_config, RCC_PLLCFGR_PLLP) != (((RCC_OscInitStruct->PLL.PLLP >> 1U) - 1U)) << RCC_PLLCFGR_PLLP_Pos) ||
 8004c64:	429a      	cmp	r2, r3
 8004c66:	d001      	beq.n	8004c6c <HAL_RCC_OscConfig+0x4e0>
#endif /* RCC_PLLCFGR_PLLR */
        {
          return HAL_ERROR;
 8004c68:	2301      	movs	r3, #1
 8004c6a:	e000      	b.n	8004c6e <HAL_RCC_OscConfig+0x4e2>
        }
      }
    }
  }
  return HAL_OK;
 8004c6c:	2300      	movs	r3, #0
}
 8004c6e:	4618      	mov	r0, r3
 8004c70:	3718      	adds	r7, #24
 8004c72:	46bd      	mov	sp, r7
 8004c74:	bd80      	pop	{r7, pc}
 8004c76:	bf00      	nop
 8004c78:	40023800 	.word	0x40023800

08004c7c <HAL_RCC_ClockConfig>:
  *         HPRE[3:0] bits to ensure that HCLK not exceed the maximum allowed frequency
  *         (for more details refer to section above "Initialization/de-initialization functions")
  * @retval None
  */
HAL_StatusTypeDef HAL_RCC_ClockConfig(const RCC_ClkInitTypeDef  *RCC_ClkInitStruct, uint32_t FLatency)
{
 8004c7c:	b580      	push	{r7, lr}
 8004c7e:	b084      	sub	sp, #16
 8004c80:	af00      	add	r7, sp, #0
 8004c82:	6078      	str	r0, [r7, #4]
 8004c84:	6039      	str	r1, [r7, #0]
  uint32_t tickstart;

  /* Check Null pointer */
  if (RCC_ClkInitStruct == NULL)
 8004c86:	687b      	ldr	r3, [r7, #4]
 8004c88:	2b00      	cmp	r3, #0
 8004c8a:	d101      	bne.n	8004c90 <HAL_RCC_ClockConfig+0x14>
  {
    return HAL_ERROR;
 8004c8c:	2301      	movs	r3, #1
 8004c8e:	e0cc      	b.n	8004e2a <HAL_RCC_ClockConfig+0x1ae>
  /* To correctly read data from FLASH memory, the number of wait states (LATENCY)
    must be correctly programmed according to the frequency of the CPU clock
    (HCLK) and the supply voltage of the device. */

  /* Increasing the number of wait states because of higher CPU frequency */
  if (FLatency > __HAL_FLASH_GET_LATENCY())
 8004c90:	4b68      	ldr	r3, [pc, #416]	@ (8004e34 <HAL_RCC_ClockConfig+0x1b8>)
 8004c92:	681b      	ldr	r3, [r3, #0]
 8004c94:	f003 0307 	and.w	r3, r3, #7
 8004c98:	683a      	ldr	r2, [r7, #0]
 8004c9a:	429a      	cmp	r2, r3
 8004c9c:	d90c      	bls.n	8004cb8 <HAL_RCC_ClockConfig+0x3c>
  {
    /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
    __HAL_FLASH_SET_LATENCY(FLatency);
 8004c9e:	4b65      	ldr	r3, [pc, #404]	@ (8004e34 <HAL_RCC_ClockConfig+0x1b8>)
 8004ca0:	683a      	ldr	r2, [r7, #0]
 8004ca2:	b2d2      	uxtb	r2, r2
 8004ca4:	701a      	strb	r2, [r3, #0]

    /* Check that the new number of wait states is taken into account to access the Flash
    memory by reading the FLASH_ACR register */
    if (__HAL_FLASH_GET_LATENCY() != FLatency)
 8004ca6:	4b63      	ldr	r3, [pc, #396]	@ (8004e34 <HAL_RCC_ClockConfig+0x1b8>)
 8004ca8:	681b      	ldr	r3, [r3, #0]
 8004caa:	f003 0307 	and.w	r3, r3, #7
 8004cae:	683a      	ldr	r2, [r7, #0]
 8004cb0:	429a      	cmp	r2, r3
 8004cb2:	d001      	beq.n	8004cb8 <HAL_RCC_ClockConfig+0x3c>
    {
      return HAL_ERROR;
 8004cb4:	2301      	movs	r3, #1
 8004cb6:	e0b8      	b.n	8004e2a <HAL_RCC_ClockConfig+0x1ae>
    }
  }

  /*-------------------------- HCLK Configuration --------------------------*/
  if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK)
 8004cb8:	687b      	ldr	r3, [r7, #4]
 8004cba:	681b      	ldr	r3, [r3, #0]
 8004cbc:	f003 0302 	and.w	r3, r3, #2
 8004cc0:	2b00      	cmp	r3, #0
 8004cc2:	d020      	beq.n	8004d06 <HAL_RCC_ClockConfig+0x8a>
  {
    /* Set the highest APBx dividers in order to ensure that we do not go through
       a non-spec phase whatever we decrease or increase HCLK. */
    if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1)
 8004cc4:	687b      	ldr	r3, [r7, #4]
 8004cc6:	681b      	ldr	r3, [r3, #0]
 8004cc8:	f003 0304 	and.w	r3, r3, #4
 8004ccc:	2b00      	cmp	r3, #0
 8004cce:	d005      	beq.n	8004cdc <HAL_RCC_ClockConfig+0x60>
    {
      MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_HCLK_DIV16);
 8004cd0:	4b59      	ldr	r3, [pc, #356]	@ (8004e38 <HAL_RCC_ClockConfig+0x1bc>)
 8004cd2:	689b      	ldr	r3, [r3, #8]
 8004cd4:	4a58      	ldr	r2, [pc, #352]	@ (8004e38 <HAL_RCC_ClockConfig+0x1bc>)
 8004cd6:	f443 53e0 	orr.w	r3, r3, #7168	@ 0x1c00
 8004cda:	6093      	str	r3, [r2, #8]
    }

    if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2)
 8004cdc:	687b      	ldr	r3, [r7, #4]
 8004cde:	681b      	ldr	r3, [r3, #0]
 8004ce0:	f003 0308 	and.w	r3, r3, #8
 8004ce4:	2b00      	cmp	r3, #0
 8004ce6:	d005      	beq.n	8004cf4 <HAL_RCC_ClockConfig+0x78>
    {
      MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, (RCC_HCLK_DIV16 << 3));
 8004ce8:	4b53      	ldr	r3, [pc, #332]	@ (8004e38 <HAL_RCC_ClockConfig+0x1bc>)
 8004cea:	689b      	ldr	r3, [r3, #8]
 8004cec:	4a52      	ldr	r2, [pc, #328]	@ (8004e38 <HAL_RCC_ClockConfig+0x1bc>)
 8004cee:	f443 4360 	orr.w	r3, r3, #57344	@ 0xe000
 8004cf2:	6093      	str	r3, [r2, #8]
    }

    assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider));
    MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider);
 8004cf4:	4b50      	ldr	r3, [pc, #320]	@ (8004e38 <HAL_RCC_ClockConfig+0x1bc>)
 8004cf6:	689b      	ldr	r3, [r3, #8]
 8004cf8:	f023 02f0 	bic.w	r2, r3, #240	@ 0xf0
 8004cfc:	687b      	ldr	r3, [r7, #4]
 8004cfe:	689b      	ldr	r3, [r3, #8]
 8004d00:	494d      	ldr	r1, [pc, #308]	@ (8004e38 <HAL_RCC_ClockConfig+0x1bc>)
 8004d02:	4313      	orrs	r3, r2
 8004d04:	608b      	str	r3, [r1, #8]
  }

  /*------------------------- SYSCLK Configuration ---------------------------*/
  if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK)
 8004d06:	687b      	ldr	r3, [r7, #4]
 8004d08:	681b      	ldr	r3, [r3, #0]
 8004d0a:	f003 0301 	and.w	r3, r3, #1
 8004d0e:	2b00      	cmp	r3, #0
 8004d10:	d044      	beq.n	8004d9c <HAL_RCC_ClockConfig+0x120>
  {
    assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource));

    /* HSE is selected as System Clock Source */
    if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)
 8004d12:	687b      	ldr	r3, [r7, #4]
 8004d14:	685b      	ldr	r3, [r3, #4]
 8004d16:	2b01      	cmp	r3, #1
 8004d18:	d107      	bne.n	8004d2a <HAL_RCC_ClockConfig+0xae>
    {
      /* Check the HSE ready flag */
      if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
 8004d1a:	4b47      	ldr	r3, [pc, #284]	@ (8004e38 <HAL_RCC_ClockConfig+0x1bc>)
 8004d1c:	681b      	ldr	r3, [r3, #0]
 8004d1e:	f403 3300 	and.w	r3, r3, #131072	@ 0x20000
 8004d22:	2b00      	cmp	r3, #0
 8004d24:	d119      	bne.n	8004d5a <HAL_RCC_ClockConfig+0xde>
      {
        return HAL_ERROR;
 8004d26:	2301      	movs	r3, #1
 8004d28:	e07f      	b.n	8004e2a <HAL_RCC_ClockConfig+0x1ae>
      }
    }
    /* PLL is selected as System Clock Source */
    else if ((RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK)   ||
 8004d2a:	687b      	ldr	r3, [r7, #4]
 8004d2c:	685b      	ldr	r3, [r3, #4]
 8004d2e:	2b02      	cmp	r3, #2
 8004d30:	d003      	beq.n	8004d3a <HAL_RCC_ClockConfig+0xbe>
             (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLRCLK))
 8004d32:	687b      	ldr	r3, [r7, #4]
 8004d34:	685b      	ldr	r3, [r3, #4]
    else if ((RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK)   ||
 8004d36:	2b03      	cmp	r3, #3
 8004d38:	d107      	bne.n	8004d4a <HAL_RCC_ClockConfig+0xce>
    {
      /* Check the PLL ready flag */
      if (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
 8004d3a:	4b3f      	ldr	r3, [pc, #252]	@ (8004e38 <HAL_RCC_ClockConfig+0x1bc>)
 8004d3c:	681b      	ldr	r3, [r3, #0]
 8004d3e:	f003 7300 	and.w	r3, r3, #33554432	@ 0x2000000
 8004d42:	2b00      	cmp	r3, #0
 8004d44:	d109      	bne.n	8004d5a <HAL_RCC_ClockConfig+0xde>
      {
        return HAL_ERROR;
 8004d46:	2301      	movs	r3, #1
 8004d48:	e06f      	b.n	8004e2a <HAL_RCC_ClockConfig+0x1ae>
    }
    /* HSI is selected as System Clock Source */
    else
    {
      /* Check the HSI ready flag */
      if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
 8004d4a:	4b3b      	ldr	r3, [pc, #236]	@ (8004e38 <HAL_RCC_ClockConfig+0x1bc>)
 8004d4c:	681b      	ldr	r3, [r3, #0]
 8004d4e:	f003 0302 	and.w	r3, r3, #2
 8004d52:	2b00      	cmp	r3, #0
 8004d54:	d101      	bne.n	8004d5a <HAL_RCC_ClockConfig+0xde>
      {
        return HAL_ERROR;
 8004d56:	2301      	movs	r3, #1
 8004d58:	e067      	b.n	8004e2a <HAL_RCC_ClockConfig+0x1ae>
      }
    }

    __HAL_RCC_SYSCLK_CONFIG(RCC_ClkInitStruct->SYSCLKSource);
 8004d5a:	4b37      	ldr	r3, [pc, #220]	@ (8004e38 <HAL_RCC_ClockConfig+0x1bc>)
 8004d5c:	689b      	ldr	r3, [r3, #8]
 8004d5e:	f023 0203 	bic.w	r2, r3, #3
 8004d62:	687b      	ldr	r3, [r7, #4]
 8004d64:	685b      	ldr	r3, [r3, #4]
 8004d66:	4934      	ldr	r1, [pc, #208]	@ (8004e38 <HAL_RCC_ClockConfig+0x1bc>)
 8004d68:	4313      	orrs	r3, r2
 8004d6a:	608b      	str	r3, [r1, #8]

    /* Get Start Tick */
    tickstart = HAL_GetTick();
 8004d6c:	f7fe f9ec 	bl	8003148 <HAL_GetTick>
 8004d70:	60f8      	str	r0, [r7, #12]

    while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos))
 8004d72:	e00a      	b.n	8004d8a <HAL_RCC_ClockConfig+0x10e>
    {
      if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE)
 8004d74:	f7fe f9e8 	bl	8003148 <HAL_GetTick>
 8004d78:	4602      	mov	r2, r0
 8004d7a:	68fb      	ldr	r3, [r7, #12]
 8004d7c:	1ad3      	subs	r3, r2, r3
 8004d7e:	f241 3288 	movw	r2, #5000	@ 0x1388
 8004d82:	4293      	cmp	r3, r2
 8004d84:	d901      	bls.n	8004d8a <HAL_RCC_ClockConfig+0x10e>
      {
        return HAL_TIMEOUT;
 8004d86:	2303      	movs	r3, #3
 8004d88:	e04f      	b.n	8004e2a <HAL_RCC_ClockConfig+0x1ae>
    while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos))
 8004d8a:	4b2b      	ldr	r3, [pc, #172]	@ (8004e38 <HAL_RCC_ClockConfig+0x1bc>)
 8004d8c:	689b      	ldr	r3, [r3, #8]
 8004d8e:	f003 020c 	and.w	r2, r3, #12
 8004d92:	687b      	ldr	r3, [r7, #4]
 8004d94:	685b      	ldr	r3, [r3, #4]
 8004d96:	009b      	lsls	r3, r3, #2
 8004d98:	429a      	cmp	r2, r3
 8004d9a:	d1eb      	bne.n	8004d74 <HAL_RCC_ClockConfig+0xf8>
      }
    }
  }

  /* Decreasing the number of wait states because of lower CPU frequency */
  if (FLatency < __HAL_FLASH_GET_LATENCY())
 8004d9c:	4b25      	ldr	r3, [pc, #148]	@ (8004e34 <HAL_RCC_ClockConfig+0x1b8>)
 8004d9e:	681b      	ldr	r3, [r3, #0]
 8004da0:	f003 0307 	and.w	r3, r3, #7
 8004da4:	683a      	ldr	r2, [r7, #0]
 8004da6:	429a      	cmp	r2, r3
 8004da8:	d20c      	bcs.n	8004dc4 <HAL_RCC_ClockConfig+0x148>
  {
    /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
    __HAL_FLASH_SET_LATENCY(FLatency);
 8004daa:	4b22      	ldr	r3, [pc, #136]	@ (8004e34 <HAL_RCC_ClockConfig+0x1b8>)
 8004dac:	683a      	ldr	r2, [r7, #0]
 8004dae:	b2d2      	uxtb	r2, r2
 8004db0:	701a      	strb	r2, [r3, #0]

    /* Check that the new number of wait states is taken into account to access the Flash
    memory by reading the FLASH_ACR register */
    if (__HAL_FLASH_GET_LATENCY() != FLatency)
 8004db2:	4b20      	ldr	r3, [pc, #128]	@ (8004e34 <HAL_RCC_ClockConfig+0x1b8>)
 8004db4:	681b      	ldr	r3, [r3, #0]
 8004db6:	f003 0307 	and.w	r3, r3, #7
 8004dba:	683a      	ldr	r2, [r7, #0]
 8004dbc:	429a      	cmp	r2, r3
 8004dbe:	d001      	beq.n	8004dc4 <HAL_RCC_ClockConfig+0x148>
    {
      return HAL_ERROR;
 8004dc0:	2301      	movs	r3, #1
 8004dc2:	e032      	b.n	8004e2a <HAL_RCC_ClockConfig+0x1ae>
    }
  }

  /*-------------------------- PCLK1 Configuration ---------------------------*/
  if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1)
 8004dc4:	687b      	ldr	r3, [r7, #4]
 8004dc6:	681b      	ldr	r3, [r3, #0]
 8004dc8:	f003 0304 	and.w	r3, r3, #4
 8004dcc:	2b00      	cmp	r3, #0
 8004dce:	d008      	beq.n	8004de2 <HAL_RCC_ClockConfig+0x166>
  {
    assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB1CLKDivider));
    MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_ClkInitStruct->APB1CLKDivider);
 8004dd0:	4b19      	ldr	r3, [pc, #100]	@ (8004e38 <HAL_RCC_ClockConfig+0x1bc>)
 8004dd2:	689b      	ldr	r3, [r3, #8]
 8004dd4:	f423 52e0 	bic.w	r2, r3, #7168	@ 0x1c00
 8004dd8:	687b      	ldr	r3, [r7, #4]
 8004dda:	68db      	ldr	r3, [r3, #12]
 8004ddc:	4916      	ldr	r1, [pc, #88]	@ (8004e38 <HAL_RCC_ClockConfig+0x1bc>)
 8004dde:	4313      	orrs	r3, r2
 8004de0:	608b      	str	r3, [r1, #8]
  }

  /*-------------------------- PCLK2 Configuration ---------------------------*/
  if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2)
 8004de2:	687b      	ldr	r3, [r7, #4]
 8004de4:	681b      	ldr	r3, [r3, #0]
 8004de6:	f003 0308 	and.w	r3, r3, #8
 8004dea:	2b00      	cmp	r3, #0
 8004dec:	d009      	beq.n	8004e02 <HAL_RCC_ClockConfig+0x186>
  {
    assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB2CLKDivider));
    MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, ((RCC_ClkInitStruct->APB2CLKDivider) << 3U));
 8004dee:	4b12      	ldr	r3, [pc, #72]	@ (8004e38 <HAL_RCC_ClockConfig+0x1bc>)
 8004df0:	689b      	ldr	r3, [r3, #8]
 8004df2:	f423 4260 	bic.w	r2, r3, #57344	@ 0xe000
 8004df6:	687b      	ldr	r3, [r7, #4]
 8004df8:	691b      	ldr	r3, [r3, #16]
 8004dfa:	00db      	lsls	r3, r3, #3
 8004dfc:	490e      	ldr	r1, [pc, #56]	@ (8004e38 <HAL_RCC_ClockConfig+0x1bc>)
 8004dfe:	4313      	orrs	r3, r2
 8004e00:	608b      	str	r3, [r1, #8]
  }

  /* Update the SystemCoreClock global variable */
  SystemCoreClock = HAL_RCC_GetSysClockFreq() >> AHBPrescTable[(RCC->CFGR & RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos];
 8004e02:	f000 f821 	bl	8004e48 <HAL_RCC_GetSysClockFreq>
 8004e06:	4602      	mov	r2, r0
 8004e08:	4b0b      	ldr	r3, [pc, #44]	@ (8004e38 <HAL_RCC_ClockConfig+0x1bc>)
 8004e0a:	689b      	ldr	r3, [r3, #8]
 8004e0c:	091b      	lsrs	r3, r3, #4
 8004e0e:	f003 030f 	and.w	r3, r3, #15
 8004e12:	490a      	ldr	r1, [pc, #40]	@ (8004e3c <HAL_RCC_ClockConfig+0x1c0>)
 8004e14:	5ccb      	ldrb	r3, [r1, r3]
 8004e16:	fa22 f303 	lsr.w	r3, r2, r3
 8004e1a:	4a09      	ldr	r2, [pc, #36]	@ (8004e40 <HAL_RCC_ClockConfig+0x1c4>)
 8004e1c:	6013      	str	r3, [r2, #0]

  /* Configure the source of time base considering new system clocks settings */
  HAL_InitTick(uwTickPrio);
 8004e1e:	4b09      	ldr	r3, [pc, #36]	@ (8004e44 <HAL_RCC_ClockConfig+0x1c8>)
 8004e20:	681b      	ldr	r3, [r3, #0]
 8004e22:	4618      	mov	r0, r3
 8004e24:	f7fe f94c 	bl	80030c0 <HAL_InitTick>

  return HAL_OK;
 8004e28:	2300      	movs	r3, #0
}
 8004e2a:	4618      	mov	r0, r3
 8004e2c:	3710      	adds	r7, #16
 8004e2e:	46bd      	mov	sp, r7
 8004e30:	bd80      	pop	{r7, pc}
 8004e32:	bf00      	nop
 8004e34:	40023c00 	.word	0x40023c00
 8004e38:	40023800 	.word	0x40023800
 8004e3c:	080059c0 	.word	0x080059c0
 8004e40:	20000000 	.word	0x20000000
 8004e44:	2000000c 	.word	0x2000000c

08004e48 <HAL_RCC_GetSysClockFreq>:
  *
  *
  * @retval SYSCLK frequency
  */
__weak uint32_t HAL_RCC_GetSysClockFreq(void)
{
 8004e48:	e92d 4fb0 	stmdb	sp!, {r4, r5, r7, r8, r9, sl, fp, lr}
 8004e4c:	b094      	sub	sp, #80	@ 0x50
 8004e4e:	af00      	add	r7, sp, #0
  uint32_t pllm = 0U;
 8004e50:	2300      	movs	r3, #0
 8004e52:	647b      	str	r3, [r7, #68]	@ 0x44
  uint32_t pllvco = 0U;
 8004e54:	2300      	movs	r3, #0
 8004e56:	64fb      	str	r3, [r7, #76]	@ 0x4c
  uint32_t pllp = 0U;
 8004e58:	2300      	movs	r3, #0
 8004e5a:	643b      	str	r3, [r7, #64]	@ 0x40
  uint32_t sysclockfreq = 0U;
 8004e5c:	2300      	movs	r3, #0
 8004e5e:	64bb      	str	r3, [r7, #72]	@ 0x48

  /* Get SYSCLK source -------------------------------------------------------*/
  switch (RCC->CFGR & RCC_CFGR_SWS)
 8004e60:	4b79      	ldr	r3, [pc, #484]	@ (8005048 <HAL_RCC_GetSysClockFreq+0x200>)
 8004e62:	689b      	ldr	r3, [r3, #8]
 8004e64:	f003 030c 	and.w	r3, r3, #12
 8004e68:	2b08      	cmp	r3, #8
 8004e6a:	d00d      	beq.n	8004e88 <HAL_RCC_GetSysClockFreq+0x40>
 8004e6c:	2b08      	cmp	r3, #8
 8004e6e:	f200 80e1 	bhi.w	8005034 <HAL_RCC_GetSysClockFreq+0x1ec>
 8004e72:	2b00      	cmp	r3, #0
 8004e74:	d002      	beq.n	8004e7c <HAL_RCC_GetSysClockFreq+0x34>
 8004e76:	2b04      	cmp	r3, #4
 8004e78:	d003      	beq.n	8004e82 <HAL_RCC_GetSysClockFreq+0x3a>
 8004e7a:	e0db      	b.n	8005034 <HAL_RCC_GetSysClockFreq+0x1ec>
  {
    case RCC_CFGR_SWS_HSI:  /* HSI used as system clock source */
    {
      sysclockfreq = HSI_VALUE;
 8004e7c:	4b73      	ldr	r3, [pc, #460]	@ (800504c <HAL_RCC_GetSysClockFreq+0x204>)
 8004e7e:	64bb      	str	r3, [r7, #72]	@ 0x48
      break;
 8004e80:	e0db      	b.n	800503a <HAL_RCC_GetSysClockFreq+0x1f2>
    }
    case RCC_CFGR_SWS_HSE:  /* HSE used as system clock  source */
    {
      sysclockfreq = HSE_VALUE;
 8004e82:	4b73      	ldr	r3, [pc, #460]	@ (8005050 <HAL_RCC_GetSysClockFreq+0x208>)
 8004e84:	64bb      	str	r3, [r7, #72]	@ 0x48
      break;
 8004e86:	e0d8      	b.n	800503a <HAL_RCC_GetSysClockFreq+0x1f2>
    }
    case RCC_CFGR_SWS_PLL:  /* PLL used as system clock  source */
    {
      /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLLM) * PLLN
      SYSCLK = PLL_VCO / PLLP */
      pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM;
 8004e88:	4b6f      	ldr	r3, [pc, #444]	@ (8005048 <HAL_RCC_GetSysClockFreq+0x200>)
 8004e8a:	685b      	ldr	r3, [r3, #4]
 8004e8c:	f003 033f 	and.w	r3, r3, #63	@ 0x3f
 8004e90:	647b      	str	r3, [r7, #68]	@ 0x44
      if (__HAL_RCC_GET_PLL_OSCSOURCE() != RCC_PLLSOURCE_HSI)
 8004e92:	4b6d      	ldr	r3, [pc, #436]	@ (8005048 <HAL_RCC_GetSysClockFreq+0x200>)
 8004e94:	685b      	ldr	r3, [r3, #4]
 8004e96:	f403 0380 	and.w	r3, r3, #4194304	@ 0x400000
 8004e9a:	2b00      	cmp	r3, #0
 8004e9c:	d063      	beq.n	8004f66 <HAL_RCC_GetSysClockFreq+0x11e>
      {
        /* HSE used as PLL clock source */
        pllvco = (uint32_t)((((uint64_t) HSE_VALUE * ((uint64_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos)))) / (uint64_t)pllm);
 8004e9e:	4b6a      	ldr	r3, [pc, #424]	@ (8005048 <HAL_RCC_GetSysClockFreq+0x200>)
 8004ea0:	685b      	ldr	r3, [r3, #4]
 8004ea2:	099b      	lsrs	r3, r3, #6
 8004ea4:	2200      	movs	r2, #0
 8004ea6:	63bb      	str	r3, [r7, #56]	@ 0x38
 8004ea8:	63fa      	str	r2, [r7, #60]	@ 0x3c
 8004eaa:	6bbb      	ldr	r3, [r7, #56]	@ 0x38
 8004eac:	f3c3 0308 	ubfx	r3, r3, #0, #9
 8004eb0:	633b      	str	r3, [r7, #48]	@ 0x30
 8004eb2:	2300      	movs	r3, #0
 8004eb4:	637b      	str	r3, [r7, #52]	@ 0x34
 8004eb6:	e9d7 450c 	ldrd	r4, r5, [r7, #48]	@ 0x30
 8004eba:	4622      	mov	r2, r4
 8004ebc:	462b      	mov	r3, r5
 8004ebe:	f04f 0000 	mov.w	r0, #0
 8004ec2:	f04f 0100 	mov.w	r1, #0
 8004ec6:	0159      	lsls	r1, r3, #5
 8004ec8:	ea41 61d2 	orr.w	r1, r1, r2, lsr #27
 8004ecc:	0150      	lsls	r0, r2, #5
 8004ece:	4602      	mov	r2, r0
 8004ed0:	460b      	mov	r3, r1
 8004ed2:	4621      	mov	r1, r4
 8004ed4:	1a51      	subs	r1, r2, r1
 8004ed6:	6139      	str	r1, [r7, #16]
 8004ed8:	4629      	mov	r1, r5
 8004eda:	eb63 0301 	sbc.w	r3, r3, r1
 8004ede:	617b      	str	r3, [r7, #20]
 8004ee0:	f04f 0200 	mov.w	r2, #0
 8004ee4:	f04f 0300 	mov.w	r3, #0
 8004ee8:	e9d7 ab04 	ldrd	sl, fp, [r7, #16]
 8004eec:	4659      	mov	r1, fp
 8004eee:	018b      	lsls	r3, r1, #6
 8004ef0:	4651      	mov	r1, sl
 8004ef2:	ea43 6391 	orr.w	r3, r3, r1, lsr #26
 8004ef6:	4651      	mov	r1, sl
 8004ef8:	018a      	lsls	r2, r1, #6
 8004efa:	4651      	mov	r1, sl
 8004efc:	ebb2 0801 	subs.w	r8, r2, r1
 8004f00:	4659      	mov	r1, fp
 8004f02:	eb63 0901 	sbc.w	r9, r3, r1
 8004f06:	f04f 0200 	mov.w	r2, #0
 8004f0a:	f04f 0300 	mov.w	r3, #0
 8004f0e:	ea4f 03c9 	mov.w	r3, r9, lsl #3
 8004f12:	ea43 7358 	orr.w	r3, r3, r8, lsr #29
 8004f16:	ea4f 02c8 	mov.w	r2, r8, lsl #3
 8004f1a:	4690      	mov	r8, r2
 8004f1c:	4699      	mov	r9, r3
 8004f1e:	4623      	mov	r3, r4
 8004f20:	eb18 0303 	adds.w	r3, r8, r3
 8004f24:	60bb      	str	r3, [r7, #8]
 8004f26:	462b      	mov	r3, r5
 8004f28:	eb49 0303 	adc.w	r3, r9, r3
 8004f2c:	60fb      	str	r3, [r7, #12]
 8004f2e:	f04f 0200 	mov.w	r2, #0
 8004f32:	f04f 0300 	mov.w	r3, #0
 8004f36:	e9d7 4502 	ldrd	r4, r5, [r7, #8]
 8004f3a:	4629      	mov	r1, r5
 8004f3c:	024b      	lsls	r3, r1, #9
 8004f3e:	4621      	mov	r1, r4
 8004f40:	ea43 53d1 	orr.w	r3, r3, r1, lsr #23
 8004f44:	4621      	mov	r1, r4
 8004f46:	024a      	lsls	r2, r1, #9
 8004f48:	4610      	mov	r0, r2
 8004f4a:	4619      	mov	r1, r3
 8004f4c:	6c7b      	ldr	r3, [r7, #68]	@ 0x44
 8004f4e:	2200      	movs	r2, #0
 8004f50:	62bb      	str	r3, [r7, #40]	@ 0x28
 8004f52:	62fa      	str	r2, [r7, #44]	@ 0x2c
 8004f54:	e9d7 230a 	ldrd	r2, r3, [r7, #40]	@ 0x28
 8004f58:	f7fb f938 	bl	80001cc <__aeabi_uldivmod>
 8004f5c:	4602      	mov	r2, r0
 8004f5e:	460b      	mov	r3, r1
 8004f60:	4613      	mov	r3, r2
 8004f62:	64fb      	str	r3, [r7, #76]	@ 0x4c
 8004f64:	e058      	b.n	8005018 <HAL_RCC_GetSysClockFreq+0x1d0>
      }
      else
      {
        /* HSI used as PLL clock source */
        pllvco = (uint32_t)((((uint64_t) HSI_VALUE * ((uint64_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos)))) / (uint64_t)pllm);
 8004f66:	4b38      	ldr	r3, [pc, #224]	@ (8005048 <HAL_RCC_GetSysClockFreq+0x200>)
 8004f68:	685b      	ldr	r3, [r3, #4]
 8004f6a:	099b      	lsrs	r3, r3, #6
 8004f6c:	2200      	movs	r2, #0
 8004f6e:	4618      	mov	r0, r3
 8004f70:	4611      	mov	r1, r2
 8004f72:	f3c0 0308 	ubfx	r3, r0, #0, #9
 8004f76:	623b      	str	r3, [r7, #32]
 8004f78:	2300      	movs	r3, #0
 8004f7a:	627b      	str	r3, [r7, #36]	@ 0x24
 8004f7c:	e9d7 8908 	ldrd	r8, r9, [r7, #32]
 8004f80:	4642      	mov	r2, r8
 8004f82:	464b      	mov	r3, r9
 8004f84:	f04f 0000 	mov.w	r0, #0
 8004f88:	f04f 0100 	mov.w	r1, #0
 8004f8c:	0159      	lsls	r1, r3, #5
 8004f8e:	ea41 61d2 	orr.w	r1, r1, r2, lsr #27
 8004f92:	0150      	lsls	r0, r2, #5
 8004f94:	4602      	mov	r2, r0
 8004f96:	460b      	mov	r3, r1
 8004f98:	4641      	mov	r1, r8
 8004f9a:	ebb2 0a01 	subs.w	sl, r2, r1
 8004f9e:	4649      	mov	r1, r9
 8004fa0:	eb63 0b01 	sbc.w	fp, r3, r1
 8004fa4:	f04f 0200 	mov.w	r2, #0
 8004fa8:	f04f 0300 	mov.w	r3, #0
 8004fac:	ea4f 138b 	mov.w	r3, fp, lsl #6
 8004fb0:	ea43 639a 	orr.w	r3, r3, sl, lsr #26
 8004fb4:	ea4f 128a 	mov.w	r2, sl, lsl #6
 8004fb8:	ebb2 040a 	subs.w	r4, r2, sl
 8004fbc:	eb63 050b 	sbc.w	r5, r3, fp
 8004fc0:	f04f 0200 	mov.w	r2, #0
 8004fc4:	f04f 0300 	mov.w	r3, #0
 8004fc8:	00eb      	lsls	r3, r5, #3
 8004fca:	ea43 7354 	orr.w	r3, r3, r4, lsr #29
 8004fce:	00e2      	lsls	r2, r4, #3
 8004fd0:	4614      	mov	r4, r2
 8004fd2:	461d      	mov	r5, r3
 8004fd4:	4643      	mov	r3, r8
 8004fd6:	18e3      	adds	r3, r4, r3
 8004fd8:	603b      	str	r3, [r7, #0]
 8004fda:	464b      	mov	r3, r9
 8004fdc:	eb45 0303 	adc.w	r3, r5, r3
 8004fe0:	607b      	str	r3, [r7, #4]
 8004fe2:	f04f 0200 	mov.w	r2, #0
 8004fe6:	f04f 0300 	mov.w	r3, #0
 8004fea:	e9d7 4500 	ldrd	r4, r5, [r7]
 8004fee:	4629      	mov	r1, r5
 8004ff0:	028b      	lsls	r3, r1, #10
 8004ff2:	4621      	mov	r1, r4
 8004ff4:	ea43 5391 	orr.w	r3, r3, r1, lsr #22
 8004ff8:	4621      	mov	r1, r4
 8004ffa:	028a      	lsls	r2, r1, #10
 8004ffc:	4610      	mov	r0, r2
 8004ffe:	4619      	mov	r1, r3
 8005000:	6c7b      	ldr	r3, [r7, #68]	@ 0x44
 8005002:	2200      	movs	r2, #0
 8005004:	61bb      	str	r3, [r7, #24]
 8005006:	61fa      	str	r2, [r7, #28]
 8005008:	e9d7 2306 	ldrd	r2, r3, [r7, #24]
 800500c:	f7fb f8de 	bl	80001cc <__aeabi_uldivmod>
 8005010:	4602      	mov	r2, r0
 8005012:	460b      	mov	r3, r1
 8005014:	4613      	mov	r3, r2
 8005016:	64fb      	str	r3, [r7, #76]	@ 0x4c
      }
      pllp = ((((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >> RCC_PLLCFGR_PLLP_Pos) + 1U) * 2U);
 8005018:	4b0b      	ldr	r3, [pc, #44]	@ (8005048 <HAL_RCC_GetSysClockFreq+0x200>)
 800501a:	685b      	ldr	r3, [r3, #4]
 800501c:	0c1b      	lsrs	r3, r3, #16
 800501e:	f003 0303 	and.w	r3, r3, #3
 8005022:	3301      	adds	r3, #1
 8005024:	005b      	lsls	r3, r3, #1
 8005026:	643b      	str	r3, [r7, #64]	@ 0x40

      sysclockfreq = pllvco / pllp;
 8005028:	6cfa      	ldr	r2, [r7, #76]	@ 0x4c
 800502a:	6c3b      	ldr	r3, [r7, #64]	@ 0x40
 800502c:	fbb2 f3f3 	udiv	r3, r2, r3
 8005030:	64bb      	str	r3, [r7, #72]	@ 0x48
      break;
 8005032:	e002      	b.n	800503a <HAL_RCC_GetSysClockFreq+0x1f2>
    }
    default:
    {
      sysclockfreq = HSI_VALUE;
 8005034:	4b05      	ldr	r3, [pc, #20]	@ (800504c <HAL_RCC_GetSysClockFreq+0x204>)
 8005036:	64bb      	str	r3, [r7, #72]	@ 0x48
      break;
 8005038:	bf00      	nop
    }
  }
  return sysclockfreq;
 800503a:	6cbb      	ldr	r3, [r7, #72]	@ 0x48
}
 800503c:	4618      	mov	r0, r3
 800503e:	3750      	adds	r7, #80	@ 0x50
 8005040:	46bd      	mov	sp, r7
 8005042:	e8bd 8fb0 	ldmia.w	sp!, {r4, r5, r7, r8, r9, sl, fp, pc}
 8005046:	bf00      	nop
 8005048:	40023800 	.word	0x40023800
 800504c:	00f42400 	.word	0x00f42400
 8005050:	007a1200 	.word	0x007a1200

08005054 <HAL_TIM_Base_Init>:
  *         Ex: call @ref HAL_TIM_Base_DeInit() before HAL_TIM_Base_Init()
  * @param  htim TIM Base handle
  * @retval HAL status
  */
HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim)
{
 8005054:	b580      	push	{r7, lr}
 8005056:	b082      	sub	sp, #8
 8005058:	af00      	add	r7, sp, #0
 800505a:	6078      	str	r0, [r7, #4]
  /* Check the TIM handle allocation */
  if (htim == NULL)
 800505c:	687b      	ldr	r3, [r7, #4]
 800505e:	2b00      	cmp	r3, #0
 8005060:	d101      	bne.n	8005066 <HAL_TIM_Base_Init+0x12>
  {
    return HAL_ERROR;
 8005062:	2301      	movs	r3, #1
 8005064:	e041      	b.n	80050ea <HAL_TIM_Base_Init+0x96>
  assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
  assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
  assert_param(IS_TIM_PERIOD(htim, htim->Init.Period));
  assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));

  if (htim->State == HAL_TIM_STATE_RESET)
 8005066:	687b      	ldr	r3, [r7, #4]
 8005068:	f893 303d 	ldrb.w	r3, [r3, #61]	@ 0x3d
 800506c:	b2db      	uxtb	r3, r3
 800506e:	2b00      	cmp	r3, #0
 8005070:	d106      	bne.n	8005080 <HAL_TIM_Base_Init+0x2c>
  {
    /* Allocate lock resource and initialize it */
    htim->Lock = HAL_UNLOCKED;
 8005072:	687b      	ldr	r3, [r7, #4]
 8005074:	2200      	movs	r2, #0
 8005076:	f883 203c 	strb.w	r2, [r3, #60]	@ 0x3c
    }
    /* Init the low level hardware : GPIO, CLOCK, NVIC */
    htim->Base_MspInitCallback(htim);
#else
    /* Init the low level hardware : GPIO, CLOCK, NVIC */
    HAL_TIM_Base_MspInit(htim);
 800507a:	6878      	ldr	r0, [r7, #4]
 800507c:	f7fc f932 	bl	80012e4 <HAL_TIM_Base_MspInit>
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
  }

  /* Set the TIM state */
  htim->State = HAL_TIM_STATE_BUSY;
 8005080:	687b      	ldr	r3, [r7, #4]
 8005082:	2202      	movs	r2, #2
 8005084:	f883 203d 	strb.w	r2, [r3, #61]	@ 0x3d

  /* Set the Time Base configuration */
  TIM_Base_SetConfig(htim->Instance, &htim->Init);
 8005088:	687b      	ldr	r3, [r7, #4]
 800508a:	681a      	ldr	r2, [r3, #0]
 800508c:	687b      	ldr	r3, [r7, #4]
 800508e:	3304      	adds	r3, #4
 8005090:	4619      	mov	r1, r3
 8005092:	4610      	mov	r0, r2
 8005094:	f000 fa7e 	bl	8005594 <TIM_Base_SetConfig>

  /* Initialize the DMA burst operation state */
  htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
 8005098:	687b      	ldr	r3, [r7, #4]
 800509a:	2201      	movs	r2, #1
 800509c:	f883 2046 	strb.w	r2, [r3, #70]	@ 0x46

  /* Initialize the TIM channels state */
  TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
 80050a0:	687b      	ldr	r3, [r7, #4]
 80050a2:	2201      	movs	r2, #1
 80050a4:	f883 203e 	strb.w	r2, [r3, #62]	@ 0x3e
 80050a8:	687b      	ldr	r3, [r7, #4]
 80050aa:	2201      	movs	r2, #1
 80050ac:	f883 203f 	strb.w	r2, [r3, #63]	@ 0x3f
 80050b0:	687b      	ldr	r3, [r7, #4]
 80050b2:	2201      	movs	r2, #1
 80050b4:	f883 2040 	strb.w	r2, [r3, #64]	@ 0x40
 80050b8:	687b      	ldr	r3, [r7, #4]
 80050ba:	2201      	movs	r2, #1
 80050bc:	f883 2041 	strb.w	r2, [r3, #65]	@ 0x41
  TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
 80050c0:	687b      	ldr	r3, [r7, #4]
 80050c2:	2201      	movs	r2, #1
 80050c4:	f883 2042 	strb.w	r2, [r3, #66]	@ 0x42
 80050c8:	687b      	ldr	r3, [r7, #4]
 80050ca:	2201      	movs	r2, #1
 80050cc:	f883 2043 	strb.w	r2, [r3, #67]	@ 0x43
 80050d0:	687b      	ldr	r3, [r7, #4]
 80050d2:	2201      	movs	r2, #1
 80050d4:	f883 2044 	strb.w	r2, [r3, #68]	@ 0x44
 80050d8:	687b      	ldr	r3, [r7, #4]
 80050da:	2201      	movs	r2, #1
 80050dc:	f883 2045 	strb.w	r2, [r3, #69]	@ 0x45

  /* Initialize the TIM state*/
  htim->State = HAL_TIM_STATE_READY;
 80050e0:	687b      	ldr	r3, [r7, #4]
 80050e2:	2201      	movs	r2, #1
 80050e4:	f883 203d 	strb.w	r2, [r3, #61]	@ 0x3d

  return HAL_OK;
 80050e8:	2300      	movs	r3, #0
}
 80050ea:	4618      	mov	r0, r3
 80050ec:	3708      	adds	r7, #8
 80050ee:	46bd      	mov	sp, r7
 80050f0:	bd80      	pop	{r7, pc}
	...

080050f4 <HAL_TIM_Base_Start_IT>:
  * @brief  Starts the TIM Base generation in interrupt mode.
  * @param  htim TIM Base handle
  * @retval HAL status
  */
HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim)
{
 80050f4:	b480      	push	{r7}
 80050f6:	b085      	sub	sp, #20
 80050f8:	af00      	add	r7, sp, #0
 80050fa:	6078      	str	r0, [r7, #4]

  /* Check the parameters */
  assert_param(IS_TIM_INSTANCE(htim->Instance));

  /* Check the TIM state */
  if (htim->State != HAL_TIM_STATE_READY)
 80050fc:	687b      	ldr	r3, [r7, #4]
 80050fe:	f893 303d 	ldrb.w	r3, [r3, #61]	@ 0x3d
 8005102:	b2db      	uxtb	r3, r3
 8005104:	2b01      	cmp	r3, #1
 8005106:	d001      	beq.n	800510c <HAL_TIM_Base_Start_IT+0x18>
  {
    return HAL_ERROR;
 8005108:	2301      	movs	r3, #1
 800510a:	e04e      	b.n	80051aa <HAL_TIM_Base_Start_IT+0xb6>
  }

  /* Set the TIM state */
  htim->State = HAL_TIM_STATE_BUSY;
 800510c:	687b      	ldr	r3, [r7, #4]
 800510e:	2202      	movs	r2, #2
 8005110:	f883 203d 	strb.w	r2, [r3, #61]	@ 0x3d

  /* Enable the TIM Update interrupt */
  __HAL_TIM_ENABLE_IT(htim, TIM_IT_UPDATE);
 8005114:	687b      	ldr	r3, [r7, #4]
 8005116:	681b      	ldr	r3, [r3, #0]
 8005118:	68da      	ldr	r2, [r3, #12]
 800511a:	687b      	ldr	r3, [r7, #4]
 800511c:	681b      	ldr	r3, [r3, #0]
 800511e:	f042 0201 	orr.w	r2, r2, #1
 8005122:	60da      	str	r2, [r3, #12]

  /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
  if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
 8005124:	687b      	ldr	r3, [r7, #4]
 8005126:	681b      	ldr	r3, [r3, #0]
 8005128:	4a23      	ldr	r2, [pc, #140]	@ (80051b8 <HAL_TIM_Base_Start_IT+0xc4>)
 800512a:	4293      	cmp	r3, r2
 800512c:	d022      	beq.n	8005174 <HAL_TIM_Base_Start_IT+0x80>
 800512e:	687b      	ldr	r3, [r7, #4]
 8005130:	681b      	ldr	r3, [r3, #0]
 8005132:	f1b3 4f80 	cmp.w	r3, #1073741824	@ 0x40000000
 8005136:	d01d      	beq.n	8005174 <HAL_TIM_Base_Start_IT+0x80>
 8005138:	687b      	ldr	r3, [r7, #4]
 800513a:	681b      	ldr	r3, [r3, #0]
 800513c:	4a1f      	ldr	r2, [pc, #124]	@ (80051bc <HAL_TIM_Base_Start_IT+0xc8>)
 800513e:	4293      	cmp	r3, r2
 8005140:	d018      	beq.n	8005174 <HAL_TIM_Base_Start_IT+0x80>
 8005142:	687b      	ldr	r3, [r7, #4]
 8005144:	681b      	ldr	r3, [r3, #0]
 8005146:	4a1e      	ldr	r2, [pc, #120]	@ (80051c0 <HAL_TIM_Base_Start_IT+0xcc>)
 8005148:	4293      	cmp	r3, r2
 800514a:	d013      	beq.n	8005174 <HAL_TIM_Base_Start_IT+0x80>
 800514c:	687b      	ldr	r3, [r7, #4]
 800514e:	681b      	ldr	r3, [r3, #0]
 8005150:	4a1c      	ldr	r2, [pc, #112]	@ (80051c4 <HAL_TIM_Base_Start_IT+0xd0>)
 8005152:	4293      	cmp	r3, r2
 8005154:	d00e      	beq.n	8005174 <HAL_TIM_Base_Start_IT+0x80>
 8005156:	687b      	ldr	r3, [r7, #4]
 8005158:	681b      	ldr	r3, [r3, #0]
 800515a:	4a1b      	ldr	r2, [pc, #108]	@ (80051c8 <HAL_TIM_Base_Start_IT+0xd4>)
 800515c:	4293      	cmp	r3, r2
 800515e:	d009      	beq.n	8005174 <HAL_TIM_Base_Start_IT+0x80>
 8005160:	687b      	ldr	r3, [r7, #4]
 8005162:	681b      	ldr	r3, [r3, #0]
 8005164:	4a19      	ldr	r2, [pc, #100]	@ (80051cc <HAL_TIM_Base_Start_IT+0xd8>)
 8005166:	4293      	cmp	r3, r2
 8005168:	d004      	beq.n	8005174 <HAL_TIM_Base_Start_IT+0x80>
 800516a:	687b      	ldr	r3, [r7, #4]
 800516c:	681b      	ldr	r3, [r3, #0]
 800516e:	4a18      	ldr	r2, [pc, #96]	@ (80051d0 <HAL_TIM_Base_Start_IT+0xdc>)
 8005170:	4293      	cmp	r3, r2
 8005172:	d111      	bne.n	8005198 <HAL_TIM_Base_Start_IT+0xa4>
  {
    tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
 8005174:	687b      	ldr	r3, [r7, #4]
 8005176:	681b      	ldr	r3, [r3, #0]
 8005178:	689b      	ldr	r3, [r3, #8]
 800517a:	f003 0307 	and.w	r3, r3, #7
 800517e:	60fb      	str	r3, [r7, #12]
    if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
 8005180:	68fb      	ldr	r3, [r7, #12]
 8005182:	2b06      	cmp	r3, #6
 8005184:	d010      	beq.n	80051a8 <HAL_TIM_Base_Start_IT+0xb4>
    {
      __HAL_TIM_ENABLE(htim);
 8005186:	687b      	ldr	r3, [r7, #4]
 8005188:	681b      	ldr	r3, [r3, #0]
 800518a:	681a      	ldr	r2, [r3, #0]
 800518c:	687b      	ldr	r3, [r7, #4]
 800518e:	681b      	ldr	r3, [r3, #0]
 8005190:	f042 0201 	orr.w	r2, r2, #1
 8005194:	601a      	str	r2, [r3, #0]
    if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
 8005196:	e007      	b.n	80051a8 <HAL_TIM_Base_Start_IT+0xb4>
    }
  }
  else
  {
    __HAL_TIM_ENABLE(htim);
 8005198:	687b      	ldr	r3, [r7, #4]
 800519a:	681b      	ldr	r3, [r3, #0]
 800519c:	681a      	ldr	r2, [r3, #0]
 800519e:	687b      	ldr	r3, [r7, #4]
 80051a0:	681b      	ldr	r3, [r3, #0]
 80051a2:	f042 0201 	orr.w	r2, r2, #1
 80051a6:	601a      	str	r2, [r3, #0]
  }

  /* Return function status */
  return HAL_OK;
 80051a8:	2300      	movs	r3, #0
}
 80051aa:	4618      	mov	r0, r3
 80051ac:	3714      	adds	r7, #20
 80051ae:	46bd      	mov	sp, r7
 80051b0:	f85d 7b04 	ldr.w	r7, [sp], #4
 80051b4:	4770      	bx	lr
 80051b6:	bf00      	nop
 80051b8:	40010000 	.word	0x40010000
 80051bc:	40000400 	.word	0x40000400
 80051c0:	40000800 	.word	0x40000800
 80051c4:	40000c00 	.word	0x40000c00
 80051c8:	40010400 	.word	0x40010400
 80051cc:	40014000 	.word	0x40014000
 80051d0:	40001800 	.word	0x40001800

080051d4 <HAL_TIM_IRQHandler>:
  * @brief  This function handles TIM interrupts requests.
  * @param  htim TIM  handle
  * @retval None
  */
void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim)
{
 80051d4:	b580      	push	{r7, lr}
 80051d6:	b084      	sub	sp, #16
 80051d8:	af00      	add	r7, sp, #0
 80051da:	6078      	str	r0, [r7, #4]
  uint32_t itsource = htim->Instance->DIER;
 80051dc:	687b      	ldr	r3, [r7, #4]
 80051de:	681b      	ldr	r3, [r3, #0]
 80051e0:	68db      	ldr	r3, [r3, #12]
 80051e2:	60fb      	str	r3, [r7, #12]
  uint32_t itflag   = htim->Instance->SR;
 80051e4:	687b      	ldr	r3, [r7, #4]
 80051e6:	681b      	ldr	r3, [r3, #0]
 80051e8:	691b      	ldr	r3, [r3, #16]
 80051ea:	60bb      	str	r3, [r7, #8]

  /* Capture compare 1 event */
  if ((itflag & (TIM_FLAG_CC1)) == (TIM_FLAG_CC1))
 80051ec:	68bb      	ldr	r3, [r7, #8]
 80051ee:	f003 0302 	and.w	r3, r3, #2
 80051f2:	2b00      	cmp	r3, #0
 80051f4:	d020      	beq.n	8005238 <HAL_TIM_IRQHandler+0x64>
  {
    if ((itsource & (TIM_IT_CC1)) == (TIM_IT_CC1))
 80051f6:	68fb      	ldr	r3, [r7, #12]
 80051f8:	f003 0302 	and.w	r3, r3, #2
 80051fc:	2b00      	cmp	r3, #0
 80051fe:	d01b      	beq.n	8005238 <HAL_TIM_IRQHandler+0x64>
    {
      {
        __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC1);
 8005200:	687b      	ldr	r3, [r7, #4]
 8005202:	681b      	ldr	r3, [r3, #0]
 8005204:	f06f 0202 	mvn.w	r2, #2
 8005208:	611a      	str	r2, [r3, #16]
        htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
 800520a:	687b      	ldr	r3, [r7, #4]
 800520c:	2201      	movs	r2, #1
 800520e:	771a      	strb	r2, [r3, #28]

        /* Input capture event */
        if ((htim->Instance->CCMR1 & TIM_CCMR1_CC1S) != 0x00U)
 8005210:	687b      	ldr	r3, [r7, #4]
 8005212:	681b      	ldr	r3, [r3, #0]
 8005214:	699b      	ldr	r3, [r3, #24]
 8005216:	f003 0303 	and.w	r3, r3, #3
 800521a:	2b00      	cmp	r3, #0
 800521c:	d003      	beq.n	8005226 <HAL_TIM_IRQHandler+0x52>
        {
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
          htim->IC_CaptureCallback(htim);
#else
          HAL_TIM_IC_CaptureCallback(htim);
 800521e:	6878      	ldr	r0, [r7, #4]
 8005220:	f000 f999 	bl	8005556 <HAL_TIM_IC_CaptureCallback>
 8005224:	e005      	b.n	8005232 <HAL_TIM_IRQHandler+0x5e>
        {
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
          htim->OC_DelayElapsedCallback(htim);
          htim->PWM_PulseFinishedCallback(htim);
#else
          HAL_TIM_OC_DelayElapsedCallback(htim);
 8005226:	6878      	ldr	r0, [r7, #4]
 8005228:	f000 f98b 	bl	8005542 <HAL_TIM_OC_DelayElapsedCallback>
          HAL_TIM_PWM_PulseFinishedCallback(htim);
 800522c:	6878      	ldr	r0, [r7, #4]
 800522e:	f000 f99c 	bl	800556a <HAL_TIM_PWM_PulseFinishedCallback>
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
        }
        htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
 8005232:	687b      	ldr	r3, [r7, #4]
 8005234:	2200      	movs	r2, #0
 8005236:	771a      	strb	r2, [r3, #28]
      }
    }
  }
  /* Capture compare 2 event */
  if ((itflag & (TIM_FLAG_CC2)) == (TIM_FLAG_CC2))
 8005238:	68bb      	ldr	r3, [r7, #8]
 800523a:	f003 0304 	and.w	r3, r3, #4
 800523e:	2b00      	cmp	r3, #0
 8005240:	d020      	beq.n	8005284 <HAL_TIM_IRQHandler+0xb0>
  {
    if ((itsource & (TIM_IT_CC2)) == (TIM_IT_CC2))
 8005242:	68fb      	ldr	r3, [r7, #12]
 8005244:	f003 0304 	and.w	r3, r3, #4
 8005248:	2b00      	cmp	r3, #0
 800524a:	d01b      	beq.n	8005284 <HAL_TIM_IRQHandler+0xb0>
    {
      __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC2);
 800524c:	687b      	ldr	r3, [r7, #4]
 800524e:	681b      	ldr	r3, [r3, #0]
 8005250:	f06f 0204 	mvn.w	r2, #4
 8005254:	611a      	str	r2, [r3, #16]
      htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
 8005256:	687b      	ldr	r3, [r7, #4]
 8005258:	2202      	movs	r2, #2
 800525a:	771a      	strb	r2, [r3, #28]
      /* Input capture event */
      if ((htim->Instance->CCMR1 & TIM_CCMR1_CC2S) != 0x00U)
 800525c:	687b      	ldr	r3, [r7, #4]
 800525e:	681b      	ldr	r3, [r3, #0]
 8005260:	699b      	ldr	r3, [r3, #24]
 8005262:	f403 7340 	and.w	r3, r3, #768	@ 0x300
 8005266:	2b00      	cmp	r3, #0
 8005268:	d003      	beq.n	8005272 <HAL_TIM_IRQHandler+0x9e>
      {
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
        htim->IC_CaptureCallback(htim);
#else
        HAL_TIM_IC_CaptureCallback(htim);
 800526a:	6878      	ldr	r0, [r7, #4]
 800526c:	f000 f973 	bl	8005556 <HAL_TIM_IC_CaptureCallback>
 8005270:	e005      	b.n	800527e <HAL_TIM_IRQHandler+0xaa>
      {
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
        htim->OC_DelayElapsedCallback(htim);
        htim->PWM_PulseFinishedCallback(htim);
#else
        HAL_TIM_OC_DelayElapsedCallback(htim);
 8005272:	6878      	ldr	r0, [r7, #4]
 8005274:	f000 f965 	bl	8005542 <HAL_TIM_OC_DelayElapsedCallback>
        HAL_TIM_PWM_PulseFinishedCallback(htim);
 8005278:	6878      	ldr	r0, [r7, #4]
 800527a:	f000 f976 	bl	800556a <HAL_TIM_PWM_PulseFinishedCallback>
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
      }
      htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
 800527e:	687b      	ldr	r3, [r7, #4]
 8005280:	2200      	movs	r2, #0
 8005282:	771a      	strb	r2, [r3, #28]
    }
  }
  /* Capture compare 3 event */
  if ((itflag & (TIM_FLAG_CC3)) == (TIM_FLAG_CC3))
 8005284:	68bb      	ldr	r3, [r7, #8]
 8005286:	f003 0308 	and.w	r3, r3, #8
 800528a:	2b00      	cmp	r3, #0
 800528c:	d020      	beq.n	80052d0 <HAL_TIM_IRQHandler+0xfc>
  {
    if ((itsource & (TIM_IT_CC3)) == (TIM_IT_CC3))
 800528e:	68fb      	ldr	r3, [r7, #12]
 8005290:	f003 0308 	and.w	r3, r3, #8
 8005294:	2b00      	cmp	r3, #0
 8005296:	d01b      	beq.n	80052d0 <HAL_TIM_IRQHandler+0xfc>
    {
      __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC3);
 8005298:	687b      	ldr	r3, [r7, #4]
 800529a:	681b      	ldr	r3, [r3, #0]
 800529c:	f06f 0208 	mvn.w	r2, #8
 80052a0:	611a      	str	r2, [r3, #16]
      htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
 80052a2:	687b      	ldr	r3, [r7, #4]
 80052a4:	2204      	movs	r2, #4
 80052a6:	771a      	strb	r2, [r3, #28]
      /* Input capture event */
      if ((htim->Instance->CCMR2 & TIM_CCMR2_CC3S) != 0x00U)
 80052a8:	687b      	ldr	r3, [r7, #4]
 80052aa:	681b      	ldr	r3, [r3, #0]
 80052ac:	69db      	ldr	r3, [r3, #28]
 80052ae:	f003 0303 	and.w	r3, r3, #3
 80052b2:	2b00      	cmp	r3, #0
 80052b4:	d003      	beq.n	80052be <HAL_TIM_IRQHandler+0xea>
      {
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
        htim->IC_CaptureCallback(htim);
#else
        HAL_TIM_IC_CaptureCallback(htim);
 80052b6:	6878      	ldr	r0, [r7, #4]
 80052b8:	f000 f94d 	bl	8005556 <HAL_TIM_IC_CaptureCallback>
 80052bc:	e005      	b.n	80052ca <HAL_TIM_IRQHandler+0xf6>
      {
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
        htim->OC_DelayElapsedCallback(htim);
        htim->PWM_PulseFinishedCallback(htim);
#else
        HAL_TIM_OC_DelayElapsedCallback(htim);
 80052be:	6878      	ldr	r0, [r7, #4]
 80052c0:	f000 f93f 	bl	8005542 <HAL_TIM_OC_DelayElapsedCallback>
        HAL_TIM_PWM_PulseFinishedCallback(htim);
 80052c4:	6878      	ldr	r0, [r7, #4]
 80052c6:	f000 f950 	bl	800556a <HAL_TIM_PWM_PulseFinishedCallback>
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
      }
      htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
 80052ca:	687b      	ldr	r3, [r7, #4]
 80052cc:	2200      	movs	r2, #0
 80052ce:	771a      	strb	r2, [r3, #28]
    }
  }
  /* Capture compare 4 event */
  if ((itflag & (TIM_FLAG_CC4)) == (TIM_FLAG_CC4))
 80052d0:	68bb      	ldr	r3, [r7, #8]
 80052d2:	f003 0310 	and.w	r3, r3, #16
 80052d6:	2b00      	cmp	r3, #0
 80052d8:	d020      	beq.n	800531c <HAL_TIM_IRQHandler+0x148>
  {
    if ((itsource & (TIM_IT_CC4)) == (TIM_IT_CC4))
 80052da:	68fb      	ldr	r3, [r7, #12]
 80052dc:	f003 0310 	and.w	r3, r3, #16
 80052e0:	2b00      	cmp	r3, #0
 80052e2:	d01b      	beq.n	800531c <HAL_TIM_IRQHandler+0x148>
    {
      __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC4);
 80052e4:	687b      	ldr	r3, [r7, #4]
 80052e6:	681b      	ldr	r3, [r3, #0]
 80052e8:	f06f 0210 	mvn.w	r2, #16
 80052ec:	611a      	str	r2, [r3, #16]
      htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
 80052ee:	687b      	ldr	r3, [r7, #4]
 80052f0:	2208      	movs	r2, #8
 80052f2:	771a      	strb	r2, [r3, #28]
      /* Input capture event */
      if ((htim->Instance->CCMR2 & TIM_CCMR2_CC4S) != 0x00U)
 80052f4:	687b      	ldr	r3, [r7, #4]
 80052f6:	681b      	ldr	r3, [r3, #0]
 80052f8:	69db      	ldr	r3, [r3, #28]
 80052fa:	f403 7340 	and.w	r3, r3, #768	@ 0x300
 80052fe:	2b00      	cmp	r3, #0
 8005300:	d003      	beq.n	800530a <HAL_TIM_IRQHandler+0x136>
      {
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
        htim->IC_CaptureCallback(htim);
#else
        HAL_TIM_IC_CaptureCallback(htim);
 8005302:	6878      	ldr	r0, [r7, #4]
 8005304:	f000 f927 	bl	8005556 <HAL_TIM_IC_CaptureCallback>
 8005308:	e005      	b.n	8005316 <HAL_TIM_IRQHandler+0x142>
      {
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
        htim->OC_DelayElapsedCallback(htim);
        htim->PWM_PulseFinishedCallback(htim);
#else
        HAL_TIM_OC_DelayElapsedCallback(htim);
 800530a:	6878      	ldr	r0, [r7, #4]
 800530c:	f000 f919 	bl	8005542 <HAL_TIM_OC_DelayElapsedCallback>
        HAL_TIM_PWM_PulseFinishedCallback(htim);
 8005310:	6878      	ldr	r0, [r7, #4]
 8005312:	f000 f92a 	bl	800556a <HAL_TIM_PWM_PulseFinishedCallback>
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
      }
      htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
 8005316:	687b      	ldr	r3, [r7, #4]
 8005318:	2200      	movs	r2, #0
 800531a:	771a      	strb	r2, [r3, #28]
    }
  }
  /* TIM Update event */
  if ((itflag & (TIM_FLAG_UPDATE)) == (TIM_FLAG_UPDATE))
 800531c:	68bb      	ldr	r3, [r7, #8]
 800531e:	f003 0301 	and.w	r3, r3, #1
 8005322:	2b00      	cmp	r3, #0
 8005324:	d00c      	beq.n	8005340 <HAL_TIM_IRQHandler+0x16c>
  {
    if ((itsource & (TIM_IT_UPDATE)) == (TIM_IT_UPDATE))
 8005326:	68fb      	ldr	r3, [r7, #12]
 8005328:	f003 0301 	and.w	r3, r3, #1
 800532c:	2b00      	cmp	r3, #0
 800532e:	d007      	beq.n	8005340 <HAL_TIM_IRQHandler+0x16c>
    {
      __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_UPDATE);
 8005330:	687b      	ldr	r3, [r7, #4]
 8005332:	681b      	ldr	r3, [r3, #0]
 8005334:	f06f 0201 	mvn.w	r2, #1
 8005338:	611a      	str	r2, [r3, #16]
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
      htim->PeriodElapsedCallback(htim);
#else
      HAL_TIM_PeriodElapsedCallback(htim);
 800533a:	6878      	ldr	r0, [r7, #4]
 800533c:	f7fb fff8 	bl	8001330 <HAL_TIM_PeriodElapsedCallback>
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
    }
  }
  /* TIM Break input event */
  if ((itflag & (TIM_FLAG_BREAK)) == (TIM_FLAG_BREAK))
 8005340:	68bb      	ldr	r3, [r7, #8]
 8005342:	f003 0380 	and.w	r3, r3, #128	@ 0x80
 8005346:	2b00      	cmp	r3, #0
 8005348:	d00c      	beq.n	8005364 <HAL_TIM_IRQHandler+0x190>
  {
    if ((itsource & (TIM_IT_BREAK)) == (TIM_IT_BREAK))
 800534a:	68fb      	ldr	r3, [r7, #12]
 800534c:	f003 0380 	and.w	r3, r3, #128	@ 0x80
 8005350:	2b00      	cmp	r3, #0
 8005352:	d007      	beq.n	8005364 <HAL_TIM_IRQHandler+0x190>
    {
      __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_BREAK);
 8005354:	687b      	ldr	r3, [r7, #4]
 8005356:	681b      	ldr	r3, [r3, #0]
 8005358:	f06f 0280 	mvn.w	r2, #128	@ 0x80
 800535c:	611a      	str	r2, [r3, #16]
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
      htim->BreakCallback(htim);
#else
      HAL_TIMEx_BreakCallback(htim);
 800535e:	6878      	ldr	r0, [r7, #4]
 8005360:	f000 fade 	bl	8005920 <HAL_TIMEx_BreakCallback>
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
    }
  }
  /* TIM Trigger detection event */
  if ((itflag & (TIM_FLAG_TRIGGER)) == (TIM_FLAG_TRIGGER))
 8005364:	68bb      	ldr	r3, [r7, #8]
 8005366:	f003 0340 	and.w	r3, r3, #64	@ 0x40
 800536a:	2b00      	cmp	r3, #0
 800536c:	d00c      	beq.n	8005388 <HAL_TIM_IRQHandler+0x1b4>
  {
    if ((itsource & (TIM_IT_TRIGGER)) == (TIM_IT_TRIGGER))
 800536e:	68fb      	ldr	r3, [r7, #12]
 8005370:	f003 0340 	and.w	r3, r3, #64	@ 0x40
 8005374:	2b00      	cmp	r3, #0
 8005376:	d007      	beq.n	8005388 <HAL_TIM_IRQHandler+0x1b4>
    {
      __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_TRIGGER);
 8005378:	687b      	ldr	r3, [r7, #4]
 800537a:	681b      	ldr	r3, [r3, #0]
 800537c:	f06f 0240 	mvn.w	r2, #64	@ 0x40
 8005380:	611a      	str	r2, [r3, #16]
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
      htim->TriggerCallback(htim);
#else
      HAL_TIM_TriggerCallback(htim);
 8005382:	6878      	ldr	r0, [r7, #4]
 8005384:	f000 f8fb 	bl	800557e <HAL_TIM_TriggerCallback>
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
    }
  }
  /* TIM commutation event */
  if ((itflag & (TIM_FLAG_COM)) == (TIM_FLAG_COM))
 8005388:	68bb      	ldr	r3, [r7, #8]
 800538a:	f003 0320 	and.w	r3, r3, #32
 800538e:	2b00      	cmp	r3, #0
 8005390:	d00c      	beq.n	80053ac <HAL_TIM_IRQHandler+0x1d8>
  {
    if ((itsource & (TIM_IT_COM)) == (TIM_IT_COM))
 8005392:	68fb      	ldr	r3, [r7, #12]
 8005394:	f003 0320 	and.w	r3, r3, #32
 8005398:	2b00      	cmp	r3, #0
 800539a:	d007      	beq.n	80053ac <HAL_TIM_IRQHandler+0x1d8>
    {
      __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_COM);
 800539c:	687b      	ldr	r3, [r7, #4]
 800539e:	681b      	ldr	r3, [r3, #0]
 80053a0:	f06f 0220 	mvn.w	r2, #32
 80053a4:	611a      	str	r2, [r3, #16]
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
      htim->CommutationCallback(htim);
#else
      HAL_TIMEx_CommutCallback(htim);
 80053a6:	6878      	ldr	r0, [r7, #4]
 80053a8:	f000 fab0 	bl	800590c <HAL_TIMEx_CommutCallback>
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
    }
  }
}
 80053ac:	bf00      	nop
 80053ae:	3710      	adds	r7, #16
 80053b0:	46bd      	mov	sp, r7
 80053b2:	bd80      	pop	{r7, pc}

080053b4 <HAL_TIM_ConfigClockSource>:
  * @param  sClockSourceConfig pointer to a TIM_ClockConfigTypeDef structure that
  *         contains the clock source information for the TIM peripheral.
  * @retval HAL status
  */
HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, const TIM_ClockConfigTypeDef *sClockSourceConfig)
{
 80053b4:	b580      	push	{r7, lr}
 80053b6:	b084      	sub	sp, #16
 80053b8:	af00      	add	r7, sp, #0
 80053ba:	6078      	str	r0, [r7, #4]
 80053bc:	6039      	str	r1, [r7, #0]
  HAL_StatusTypeDef status = HAL_OK;
 80053be:	2300      	movs	r3, #0
 80053c0:	73fb      	strb	r3, [r7, #15]
  uint32_t tmpsmcr;

  /* Process Locked */
  __HAL_LOCK(htim);
 80053c2:	687b      	ldr	r3, [r7, #4]
 80053c4:	f893 303c 	ldrb.w	r3, [r3, #60]	@ 0x3c
 80053c8:	2b01      	cmp	r3, #1
 80053ca:	d101      	bne.n	80053d0 <HAL_TIM_ConfigClockSource+0x1c>
 80053cc:	2302      	movs	r3, #2
 80053ce:	e0b4      	b.n	800553a <HAL_TIM_ConfigClockSource+0x186>
 80053d0:	687b      	ldr	r3, [r7, #4]
 80053d2:	2201      	movs	r2, #1
 80053d4:	f883 203c 	strb.w	r2, [r3, #60]	@ 0x3c

  htim->State = HAL_TIM_STATE_BUSY;
 80053d8:	687b      	ldr	r3, [r7, #4]
 80053da:	2202      	movs	r2, #2
 80053dc:	f883 203d 	strb.w	r2, [r3, #61]	@ 0x3d

  /* Check the parameters */
  assert_param(IS_TIM_CLOCKSOURCE(sClockSourceConfig->ClockSource));

  /* Reset the SMS, TS, ECE, ETPS and ETRF bits */
  tmpsmcr = htim->Instance->SMCR;
 80053e0:	687b      	ldr	r3, [r7, #4]
 80053e2:	681b      	ldr	r3, [r3, #0]
 80053e4:	689b      	ldr	r3, [r3, #8]
 80053e6:	60bb      	str	r3, [r7, #8]
  tmpsmcr &= ~(TIM_SMCR_SMS | TIM_SMCR_TS);
 80053e8:	68bb      	ldr	r3, [r7, #8]
 80053ea:	f023 0377 	bic.w	r3, r3, #119	@ 0x77
 80053ee:	60bb      	str	r3, [r7, #8]
  tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP);
 80053f0:	68bb      	ldr	r3, [r7, #8]
 80053f2:	f423 437f 	bic.w	r3, r3, #65280	@ 0xff00
 80053f6:	60bb      	str	r3, [r7, #8]
  htim->Instance->SMCR = tmpsmcr;
 80053f8:	687b      	ldr	r3, [r7, #4]
 80053fa:	681b      	ldr	r3, [r3, #0]
 80053fc:	68ba      	ldr	r2, [r7, #8]
 80053fe:	609a      	str	r2, [r3, #8]

  switch (sClockSourceConfig->ClockSource)
 8005400:	683b      	ldr	r3, [r7, #0]
 8005402:	681b      	ldr	r3, [r3, #0]
 8005404:	f5b3 5f00 	cmp.w	r3, #8192	@ 0x2000
 8005408:	d03e      	beq.n	8005488 <HAL_TIM_ConfigClockSource+0xd4>
 800540a:	f5b3 5f00 	cmp.w	r3, #8192	@ 0x2000
 800540e:	f200 8087 	bhi.w	8005520 <HAL_TIM_ConfigClockSource+0x16c>
 8005412:	f5b3 5f80 	cmp.w	r3, #4096	@ 0x1000
 8005416:	f000 8086 	beq.w	8005526 <HAL_TIM_ConfigClockSource+0x172>
 800541a:	f5b3 5f80 	cmp.w	r3, #4096	@ 0x1000
 800541e:	d87f      	bhi.n	8005520 <HAL_TIM_ConfigClockSource+0x16c>
 8005420:	2b70      	cmp	r3, #112	@ 0x70
 8005422:	d01a      	beq.n	800545a <HAL_TIM_ConfigClockSource+0xa6>
 8005424:	2b70      	cmp	r3, #112	@ 0x70
 8005426:	d87b      	bhi.n	8005520 <HAL_TIM_ConfigClockSource+0x16c>
 8005428:	2b60      	cmp	r3, #96	@ 0x60
 800542a:	d050      	beq.n	80054ce <HAL_TIM_ConfigClockSource+0x11a>
 800542c:	2b60      	cmp	r3, #96	@ 0x60
 800542e:	d877      	bhi.n	8005520 <HAL_TIM_ConfigClockSource+0x16c>
 8005430:	2b50      	cmp	r3, #80	@ 0x50
 8005432:	d03c      	beq.n	80054ae <HAL_TIM_ConfigClockSource+0xfa>
 8005434:	2b50      	cmp	r3, #80	@ 0x50
 8005436:	d873      	bhi.n	8005520 <HAL_TIM_ConfigClockSource+0x16c>
 8005438:	2b40      	cmp	r3, #64	@ 0x40
 800543a:	d058      	beq.n	80054ee <HAL_TIM_ConfigClockSource+0x13a>
 800543c:	2b40      	cmp	r3, #64	@ 0x40
 800543e:	d86f      	bhi.n	8005520 <HAL_TIM_ConfigClockSource+0x16c>
 8005440:	2b30      	cmp	r3, #48	@ 0x30
 8005442:	d064      	beq.n	800550e <HAL_TIM_ConfigClockSource+0x15a>
 8005444:	2b30      	cmp	r3, #48	@ 0x30
 8005446:	d86b      	bhi.n	8005520 <HAL_TIM_ConfigClockSource+0x16c>
 8005448:	2b20      	cmp	r3, #32
 800544a:	d060      	beq.n	800550e <HAL_TIM_ConfigClockSource+0x15a>
 800544c:	2b20      	cmp	r3, #32
 800544e:	d867      	bhi.n	8005520 <HAL_TIM_ConfigClockSource+0x16c>
 8005450:	2b00      	cmp	r3, #0
 8005452:	d05c      	beq.n	800550e <HAL_TIM_ConfigClockSource+0x15a>
 8005454:	2b10      	cmp	r3, #16
 8005456:	d05a      	beq.n	800550e <HAL_TIM_ConfigClockSource+0x15a>
 8005458:	e062      	b.n	8005520 <HAL_TIM_ConfigClockSource+0x16c>
      assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler));
      assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
      assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));

      /* Configure the ETR Clock source */
      TIM_ETR_SetConfig(htim->Instance,
 800545a:	687b      	ldr	r3, [r7, #4]
 800545c:	6818      	ldr	r0, [r3, #0]
                        sClockSourceConfig->ClockPrescaler,
 800545e:	683b      	ldr	r3, [r7, #0]
 8005460:	6899      	ldr	r1, [r3, #8]
                        sClockSourceConfig->ClockPolarity,
 8005462:	683b      	ldr	r3, [r7, #0]
 8005464:	685a      	ldr	r2, [r3, #4]
                        sClockSourceConfig->ClockFilter);
 8005466:	683b      	ldr	r3, [r7, #0]
 8005468:	68db      	ldr	r3, [r3, #12]
      TIM_ETR_SetConfig(htim->Instance,
 800546a:	f000 f9b3 	bl	80057d4 <TIM_ETR_SetConfig>

      /* Select the External clock mode1 and the ETRF trigger */
      tmpsmcr = htim->Instance->SMCR;
 800546e:	687b      	ldr	r3, [r7, #4]
 8005470:	681b      	ldr	r3, [r3, #0]
 8005472:	689b      	ldr	r3, [r3, #8]
 8005474:	60bb      	str	r3, [r7, #8]
      tmpsmcr |= (TIM_SLAVEMODE_EXTERNAL1 | TIM_CLOCKSOURCE_ETRMODE1);
 8005476:	68bb      	ldr	r3, [r7, #8]
 8005478:	f043 0377 	orr.w	r3, r3, #119	@ 0x77
 800547c:	60bb      	str	r3, [r7, #8]
      /* Write to TIMx SMCR */
      htim->Instance->SMCR = tmpsmcr;
 800547e:	687b      	ldr	r3, [r7, #4]
 8005480:	681b      	ldr	r3, [r3, #0]
 8005482:	68ba      	ldr	r2, [r7, #8]
 8005484:	609a      	str	r2, [r3, #8]
      break;
 8005486:	e04f      	b.n	8005528 <HAL_TIM_ConfigClockSource+0x174>
      assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler));
      assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
      assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));

      /* Configure the ETR Clock source */
      TIM_ETR_SetConfig(htim->Instance,
 8005488:	687b      	ldr	r3, [r7, #4]
 800548a:	6818      	ldr	r0, [r3, #0]
                        sClockSourceConfig->ClockPrescaler,
 800548c:	683b      	ldr	r3, [r7, #0]
 800548e:	6899      	ldr	r1, [r3, #8]
                        sClockSourceConfig->ClockPolarity,
 8005490:	683b      	ldr	r3, [r7, #0]
 8005492:	685a      	ldr	r2, [r3, #4]
                        sClockSourceConfig->ClockFilter);
 8005494:	683b      	ldr	r3, [r7, #0]
 8005496:	68db      	ldr	r3, [r3, #12]
      TIM_ETR_SetConfig(htim->Instance,
 8005498:	f000 f99c 	bl	80057d4 <TIM_ETR_SetConfig>
      /* Enable the External clock mode2 */
      htim->Instance->SMCR |= TIM_SMCR_ECE;
 800549c:	687b      	ldr	r3, [r7, #4]
 800549e:	681b      	ldr	r3, [r3, #0]
 80054a0:	689a      	ldr	r2, [r3, #8]
 80054a2:	687b      	ldr	r3, [r7, #4]
 80054a4:	681b      	ldr	r3, [r3, #0]
 80054a6:	f442 4280 	orr.w	r2, r2, #16384	@ 0x4000
 80054aa:	609a      	str	r2, [r3, #8]
      break;
 80054ac:	e03c      	b.n	8005528 <HAL_TIM_ConfigClockSource+0x174>

      /* Check TI1 input conditioning related parameters */
      assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
      assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));

      TIM_TI1_ConfigInputStage(htim->Instance,
 80054ae:	687b      	ldr	r3, [r7, #4]
 80054b0:	6818      	ldr	r0, [r3, #0]
                               sClockSourceConfig->ClockPolarity,
 80054b2:	683b      	ldr	r3, [r7, #0]
 80054b4:	6859      	ldr	r1, [r3, #4]
                               sClockSourceConfig->ClockFilter);
 80054b6:	683b      	ldr	r3, [r7, #0]
 80054b8:	68db      	ldr	r3, [r3, #12]
      TIM_TI1_ConfigInputStage(htim->Instance,
 80054ba:	461a      	mov	r2, r3
 80054bc:	f000 f910 	bl	80056e0 <TIM_TI1_ConfigInputStage>
      TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1);
 80054c0:	687b      	ldr	r3, [r7, #4]
 80054c2:	681b      	ldr	r3, [r3, #0]
 80054c4:	2150      	movs	r1, #80	@ 0x50
 80054c6:	4618      	mov	r0, r3
 80054c8:	f000 f969 	bl	800579e <TIM_ITRx_SetConfig>
      break;
 80054cc:	e02c      	b.n	8005528 <HAL_TIM_ConfigClockSource+0x174>

      /* Check TI2 input conditioning related parameters */
      assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
      assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));

      TIM_TI2_ConfigInputStage(htim->Instance,
 80054ce:	687b      	ldr	r3, [r7, #4]
 80054d0:	6818      	ldr	r0, [r3, #0]
                               sClockSourceConfig->ClockPolarity,
 80054d2:	683b      	ldr	r3, [r7, #0]
 80054d4:	6859      	ldr	r1, [r3, #4]
                               sClockSourceConfig->ClockFilter);
 80054d6:	683b      	ldr	r3, [r7, #0]
 80054d8:	68db      	ldr	r3, [r3, #12]
      TIM_TI2_ConfigInputStage(htim->Instance,
 80054da:	461a      	mov	r2, r3
 80054dc:	f000 f92f 	bl	800573e <TIM_TI2_ConfigInputStage>
      TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI2);
 80054e0:	687b      	ldr	r3, [r7, #4]
 80054e2:	681b      	ldr	r3, [r3, #0]
 80054e4:	2160      	movs	r1, #96	@ 0x60
 80054e6:	4618      	mov	r0, r3
 80054e8:	f000 f959 	bl	800579e <TIM_ITRx_SetConfig>
      break;
 80054ec:	e01c      	b.n	8005528 <HAL_TIM_ConfigClockSource+0x174>

      /* Check TI1 input conditioning related parameters */
      assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
      assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));

      TIM_TI1_ConfigInputStage(htim->Instance,
 80054ee:	687b      	ldr	r3, [r7, #4]
 80054f0:	6818      	ldr	r0, [r3, #0]
                               sClockSourceConfig->ClockPolarity,
 80054f2:	683b      	ldr	r3, [r7, #0]
 80054f4:	6859      	ldr	r1, [r3, #4]
                               sClockSourceConfig->ClockFilter);
 80054f6:	683b      	ldr	r3, [r7, #0]
 80054f8:	68db      	ldr	r3, [r3, #12]
      TIM_TI1_ConfigInputStage(htim->Instance,
 80054fa:	461a      	mov	r2, r3
 80054fc:	f000 f8f0 	bl	80056e0 <TIM_TI1_ConfigInputStage>
      TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1ED);
 8005500:	687b      	ldr	r3, [r7, #4]
 8005502:	681b      	ldr	r3, [r3, #0]
 8005504:	2140      	movs	r1, #64	@ 0x40
 8005506:	4618      	mov	r0, r3
 8005508:	f000 f949 	bl	800579e <TIM_ITRx_SetConfig>
      break;
 800550c:	e00c      	b.n	8005528 <HAL_TIM_ConfigClockSource+0x174>
    case TIM_CLOCKSOURCE_ITR3:
    {
      /* Check whether or not the timer instance supports internal trigger input */
      assert_param(IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(htim->Instance));

      TIM_ITRx_SetConfig(htim->Instance, sClockSourceConfig->ClockSource);
 800550e:	687b      	ldr	r3, [r7, #4]
 8005510:	681a      	ldr	r2, [r3, #0]
 8005512:	683b      	ldr	r3, [r7, #0]
 8005514:	681b      	ldr	r3, [r3, #0]
 8005516:	4619      	mov	r1, r3
 8005518:	4610      	mov	r0, r2
 800551a:	f000 f940 	bl	800579e <TIM_ITRx_SetConfig>
      break;
 800551e:	e003      	b.n	8005528 <HAL_TIM_ConfigClockSource+0x174>
    }

    default:
      status = HAL_ERROR;
 8005520:	2301      	movs	r3, #1
 8005522:	73fb      	strb	r3, [r7, #15]
      break;
 8005524:	e000      	b.n	8005528 <HAL_TIM_ConfigClockSource+0x174>
      break;
 8005526:	bf00      	nop
  }
  htim->State = HAL_TIM_STATE_READY;
 8005528:	687b      	ldr	r3, [r7, #4]
 800552a:	2201      	movs	r2, #1
 800552c:	f883 203d 	strb.w	r2, [r3, #61]	@ 0x3d

  __HAL_UNLOCK(htim);
 8005530:	687b      	ldr	r3, [r7, #4]
 8005532:	2200      	movs	r2, #0
 8005534:	f883 203c 	strb.w	r2, [r3, #60]	@ 0x3c

  return status;
 8005538:	7bfb      	ldrb	r3, [r7, #15]
}
 800553a:	4618      	mov	r0, r3
 800553c:	3710      	adds	r7, #16
 800553e:	46bd      	mov	sp, r7
 8005540:	bd80      	pop	{r7, pc}

08005542 <HAL_TIM_OC_DelayElapsedCallback>:
  * @brief  Output Compare callback in non-blocking mode
  * @param  htim TIM OC handle
  * @retval None
  */
__weak void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim)
{
 8005542:	b480      	push	{r7}
 8005544:	b083      	sub	sp, #12
 8005546:	af00      	add	r7, sp, #0
 8005548:	6078      	str	r0, [r7, #4]
  UNUSED(htim);

  /* NOTE : This function should not be modified, when the callback is needed,
            the HAL_TIM_OC_DelayElapsedCallback could be implemented in the user file
   */
}
 800554a:	bf00      	nop
 800554c:	370c      	adds	r7, #12
 800554e:	46bd      	mov	sp, r7
 8005550:	f85d 7b04 	ldr.w	r7, [sp], #4
 8005554:	4770      	bx	lr

08005556 <HAL_TIM_IC_CaptureCallback>:
  * @brief  Input Capture callback in non-blocking mode
  * @param  htim TIM IC handle
  * @retval None
  */
__weak void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim)
{
 8005556:	b480      	push	{r7}
 8005558:	b083      	sub	sp, #12
 800555a:	af00      	add	r7, sp, #0
 800555c:	6078      	str	r0, [r7, #4]
  UNUSED(htim);

  /* NOTE : This function should not be modified, when the callback is needed,
            the HAL_TIM_IC_CaptureCallback could be implemented in the user file
   */
}
 800555e:	bf00      	nop
 8005560:	370c      	adds	r7, #12
 8005562:	46bd      	mov	sp, r7
 8005564:	f85d 7b04 	ldr.w	r7, [sp], #4
 8005568:	4770      	bx	lr

0800556a <HAL_TIM_PWM_PulseFinishedCallback>:
  * @brief  PWM Pulse finished callback in non-blocking mode
  * @param  htim TIM handle
  * @retval None
  */
__weak void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim)
{
 800556a:	b480      	push	{r7}
 800556c:	b083      	sub	sp, #12
 800556e:	af00      	add	r7, sp, #0
 8005570:	6078      	str	r0, [r7, #4]
  UNUSED(htim);

  /* NOTE : This function should not be modified, when the callback is needed,
            the HAL_TIM_PWM_PulseFinishedCallback could be implemented in the user file
   */
}
 8005572:	bf00      	nop
 8005574:	370c      	adds	r7, #12
 8005576:	46bd      	mov	sp, r7
 8005578:	f85d 7b04 	ldr.w	r7, [sp], #4
 800557c:	4770      	bx	lr

0800557e <HAL_TIM_TriggerCallback>:
  * @brief  Hall Trigger detection callback in non-blocking mode
  * @param  htim TIM handle
  * @retval None
  */
__weak void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim)
{
 800557e:	b480      	push	{r7}
 8005580:	b083      	sub	sp, #12
 8005582:	af00      	add	r7, sp, #0
 8005584:	6078      	str	r0, [r7, #4]
  UNUSED(htim);

  /* NOTE : This function should not be modified, when the callback is needed,
            the HAL_TIM_TriggerCallback could be implemented in the user file
   */
}
 8005586:	bf00      	nop
 8005588:	370c      	adds	r7, #12
 800558a:	46bd      	mov	sp, r7
 800558c:	f85d 7b04 	ldr.w	r7, [sp], #4
 8005590:	4770      	bx	lr
	...

08005594 <TIM_Base_SetConfig>:
  * @param  TIMx TIM peripheral
  * @param  Structure TIM Base configuration structure
  * @retval None
  */
void TIM_Base_SetConfig(TIM_TypeDef *TIMx, const TIM_Base_InitTypeDef *Structure)
{
 8005594:	b480      	push	{r7}
 8005596:	b085      	sub	sp, #20
 8005598:	af00      	add	r7, sp, #0
 800559a:	6078      	str	r0, [r7, #4]
 800559c:	6039      	str	r1, [r7, #0]
  uint32_t tmpcr1;
  tmpcr1 = TIMx->CR1;
 800559e:	687b      	ldr	r3, [r7, #4]
 80055a0:	681b      	ldr	r3, [r3, #0]
 80055a2:	60fb      	str	r3, [r7, #12]

  /* Set TIM Time Base Unit parameters ---------------------------------------*/
  if (IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx))
 80055a4:	687b      	ldr	r3, [r7, #4]
 80055a6:	4a43      	ldr	r2, [pc, #268]	@ (80056b4 <TIM_Base_SetConfig+0x120>)
 80055a8:	4293      	cmp	r3, r2
 80055aa:	d013      	beq.n	80055d4 <TIM_Base_SetConfig+0x40>
 80055ac:	687b      	ldr	r3, [r7, #4]
 80055ae:	f1b3 4f80 	cmp.w	r3, #1073741824	@ 0x40000000
 80055b2:	d00f      	beq.n	80055d4 <TIM_Base_SetConfig+0x40>
 80055b4:	687b      	ldr	r3, [r7, #4]
 80055b6:	4a40      	ldr	r2, [pc, #256]	@ (80056b8 <TIM_Base_SetConfig+0x124>)
 80055b8:	4293      	cmp	r3, r2
 80055ba:	d00b      	beq.n	80055d4 <TIM_Base_SetConfig+0x40>
 80055bc:	687b      	ldr	r3, [r7, #4]
 80055be:	4a3f      	ldr	r2, [pc, #252]	@ (80056bc <TIM_Base_SetConfig+0x128>)
 80055c0:	4293      	cmp	r3, r2
 80055c2:	d007      	beq.n	80055d4 <TIM_Base_SetConfig+0x40>
 80055c4:	687b      	ldr	r3, [r7, #4]
 80055c6:	4a3e      	ldr	r2, [pc, #248]	@ (80056c0 <TIM_Base_SetConfig+0x12c>)
 80055c8:	4293      	cmp	r3, r2
 80055ca:	d003      	beq.n	80055d4 <TIM_Base_SetConfig+0x40>
 80055cc:	687b      	ldr	r3, [r7, #4]
 80055ce:	4a3d      	ldr	r2, [pc, #244]	@ (80056c4 <TIM_Base_SetConfig+0x130>)
 80055d0:	4293      	cmp	r3, r2
 80055d2:	d108      	bne.n	80055e6 <TIM_Base_SetConfig+0x52>
  {
    /* Select the Counter Mode */
    tmpcr1 &= ~(TIM_CR1_DIR | TIM_CR1_CMS);
 80055d4:	68fb      	ldr	r3, [r7, #12]
 80055d6:	f023 0370 	bic.w	r3, r3, #112	@ 0x70
 80055da:	60fb      	str	r3, [r7, #12]
    tmpcr1 |= Structure->CounterMode;
 80055dc:	683b      	ldr	r3, [r7, #0]
 80055de:	685b      	ldr	r3, [r3, #4]
 80055e0:	68fa      	ldr	r2, [r7, #12]
 80055e2:	4313      	orrs	r3, r2
 80055e4:	60fb      	str	r3, [r7, #12]
  }

  if (IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx))
 80055e6:	687b      	ldr	r3, [r7, #4]
 80055e8:	4a32      	ldr	r2, [pc, #200]	@ (80056b4 <TIM_Base_SetConfig+0x120>)
 80055ea:	4293      	cmp	r3, r2
 80055ec:	d02b      	beq.n	8005646 <TIM_Base_SetConfig+0xb2>
 80055ee:	687b      	ldr	r3, [r7, #4]
 80055f0:	f1b3 4f80 	cmp.w	r3, #1073741824	@ 0x40000000
 80055f4:	d027      	beq.n	8005646 <TIM_Base_SetConfig+0xb2>
 80055f6:	687b      	ldr	r3, [r7, #4]
 80055f8:	4a2f      	ldr	r2, [pc, #188]	@ (80056b8 <TIM_Base_SetConfig+0x124>)
 80055fa:	4293      	cmp	r3, r2
 80055fc:	d023      	beq.n	8005646 <TIM_Base_SetConfig+0xb2>
 80055fe:	687b      	ldr	r3, [r7, #4]
 8005600:	4a2e      	ldr	r2, [pc, #184]	@ (80056bc <TIM_Base_SetConfig+0x128>)
 8005602:	4293      	cmp	r3, r2
 8005604:	d01f      	beq.n	8005646 <TIM_Base_SetConfig+0xb2>
 8005606:	687b      	ldr	r3, [r7, #4]
 8005608:	4a2d      	ldr	r2, [pc, #180]	@ (80056c0 <TIM_Base_SetConfig+0x12c>)
 800560a:	4293      	cmp	r3, r2
 800560c:	d01b      	beq.n	8005646 <TIM_Base_SetConfig+0xb2>
 800560e:	687b      	ldr	r3, [r7, #4]
 8005610:	4a2c      	ldr	r2, [pc, #176]	@ (80056c4 <TIM_Base_SetConfig+0x130>)
 8005612:	4293      	cmp	r3, r2
 8005614:	d017      	beq.n	8005646 <TIM_Base_SetConfig+0xb2>
 8005616:	687b      	ldr	r3, [r7, #4]
 8005618:	4a2b      	ldr	r2, [pc, #172]	@ (80056c8 <TIM_Base_SetConfig+0x134>)
 800561a:	4293      	cmp	r3, r2
 800561c:	d013      	beq.n	8005646 <TIM_Base_SetConfig+0xb2>
 800561e:	687b      	ldr	r3, [r7, #4]
 8005620:	4a2a      	ldr	r2, [pc, #168]	@ (80056cc <TIM_Base_SetConfig+0x138>)
 8005622:	4293      	cmp	r3, r2
 8005624:	d00f      	beq.n	8005646 <TIM_Base_SetConfig+0xb2>
 8005626:	687b      	ldr	r3, [r7, #4]
 8005628:	4a29      	ldr	r2, [pc, #164]	@ (80056d0 <TIM_Base_SetConfig+0x13c>)
 800562a:	4293      	cmp	r3, r2
 800562c:	d00b      	beq.n	8005646 <TIM_Base_SetConfig+0xb2>
 800562e:	687b      	ldr	r3, [r7, #4]
 8005630:	4a28      	ldr	r2, [pc, #160]	@ (80056d4 <TIM_Base_SetConfig+0x140>)
 8005632:	4293      	cmp	r3, r2
 8005634:	d007      	beq.n	8005646 <TIM_Base_SetConfig+0xb2>
 8005636:	687b      	ldr	r3, [r7, #4]
 8005638:	4a27      	ldr	r2, [pc, #156]	@ (80056d8 <TIM_Base_SetConfig+0x144>)
 800563a:	4293      	cmp	r3, r2
 800563c:	d003      	beq.n	8005646 <TIM_Base_SetConfig+0xb2>
 800563e:	687b      	ldr	r3, [r7, #4]
 8005640:	4a26      	ldr	r2, [pc, #152]	@ (80056dc <TIM_Base_SetConfig+0x148>)
 8005642:	4293      	cmp	r3, r2
 8005644:	d108      	bne.n	8005658 <TIM_Base_SetConfig+0xc4>
  {
    /* Set the clock division */
    tmpcr1 &= ~TIM_CR1_CKD;
 8005646:	68fb      	ldr	r3, [r7, #12]
 8005648:	f423 7340 	bic.w	r3, r3, #768	@ 0x300
 800564c:	60fb      	str	r3, [r7, #12]
    tmpcr1 |= (uint32_t)Structure->ClockDivision;
 800564e:	683b      	ldr	r3, [r7, #0]
 8005650:	68db      	ldr	r3, [r3, #12]
 8005652:	68fa      	ldr	r2, [r7, #12]
 8005654:	4313      	orrs	r3, r2
 8005656:	60fb      	str	r3, [r7, #12]
  }

  /* Set the auto-reload preload */
  MODIFY_REG(tmpcr1, TIM_CR1_ARPE, Structure->AutoReloadPreload);
 8005658:	68fb      	ldr	r3, [r7, #12]
 800565a:	f023 0280 	bic.w	r2, r3, #128	@ 0x80
 800565e:	683b      	ldr	r3, [r7, #0]
 8005660:	695b      	ldr	r3, [r3, #20]
 8005662:	4313      	orrs	r3, r2
 8005664:	60fb      	str	r3, [r7, #12]

  /* Set the Autoreload value */
  TIMx->ARR = (uint32_t)Structure->Period ;
 8005666:	683b      	ldr	r3, [r7, #0]
 8005668:	689a      	ldr	r2, [r3, #8]
 800566a:	687b      	ldr	r3, [r7, #4]
 800566c:	62da      	str	r2, [r3, #44]	@ 0x2c

  /* Set the Prescaler value */
  TIMx->PSC = Structure->Prescaler;
 800566e:	683b      	ldr	r3, [r7, #0]
 8005670:	681a      	ldr	r2, [r3, #0]
 8005672:	687b      	ldr	r3, [r7, #4]
 8005674:	629a      	str	r2, [r3, #40]	@ 0x28

  if (IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx))
 8005676:	687b      	ldr	r3, [r7, #4]
 8005678:	4a0e      	ldr	r2, [pc, #56]	@ (80056b4 <TIM_Base_SetConfig+0x120>)
 800567a:	4293      	cmp	r3, r2
 800567c:	d003      	beq.n	8005686 <TIM_Base_SetConfig+0xf2>
 800567e:	687b      	ldr	r3, [r7, #4]
 8005680:	4a10      	ldr	r2, [pc, #64]	@ (80056c4 <TIM_Base_SetConfig+0x130>)
 8005682:	4293      	cmp	r3, r2
 8005684:	d103      	bne.n	800568e <TIM_Base_SetConfig+0xfa>
  {
    /* Set the Repetition Counter value */
    TIMx->RCR = Structure->RepetitionCounter;
 8005686:	683b      	ldr	r3, [r7, #0]
 8005688:	691a      	ldr	r2, [r3, #16]
 800568a:	687b      	ldr	r3, [r7, #4]
 800568c:	631a      	str	r2, [r3, #48]	@ 0x30
  }

  /* Disable Update Event (UEV) with Update Generation (UG)
     by changing Update Request Source (URS) to avoid Update flag (UIF) */
  SET_BIT(TIMx->CR1, TIM_CR1_URS);
 800568e:	687b      	ldr	r3, [r7, #4]
 8005690:	681b      	ldr	r3, [r3, #0]
 8005692:	f043 0204 	orr.w	r2, r3, #4
 8005696:	687b      	ldr	r3, [r7, #4]
 8005698:	601a      	str	r2, [r3, #0]

  /* Generate an update event to reload the Prescaler
     and the repetition counter (only for advanced timer) value immediately */
  TIMx->EGR = TIM_EGR_UG;
 800569a:	687b      	ldr	r3, [r7, #4]
 800569c:	2201      	movs	r2, #1
 800569e:	615a      	str	r2, [r3, #20]

  TIMx->CR1 = tmpcr1;
 80056a0:	687b      	ldr	r3, [r7, #4]
 80056a2:	68fa      	ldr	r2, [r7, #12]
 80056a4:	601a      	str	r2, [r3, #0]
}
 80056a6:	bf00      	nop
 80056a8:	3714      	adds	r7, #20
 80056aa:	46bd      	mov	sp, r7
 80056ac:	f85d 7b04 	ldr.w	r7, [sp], #4
 80056b0:	4770      	bx	lr
 80056b2:	bf00      	nop
 80056b4:	40010000 	.word	0x40010000
 80056b8:	40000400 	.word	0x40000400
 80056bc:	40000800 	.word	0x40000800
 80056c0:	40000c00 	.word	0x40000c00
 80056c4:	40010400 	.word	0x40010400
 80056c8:	40014000 	.word	0x40014000
 80056cc:	40014400 	.word	0x40014400
 80056d0:	40014800 	.word	0x40014800
 80056d4:	40001800 	.word	0x40001800
 80056d8:	40001c00 	.word	0x40001c00
 80056dc:	40002000 	.word	0x40002000

080056e0 <TIM_TI1_ConfigInputStage>:
  * @param  TIM_ICFilter Specifies the Input Capture Filter.
  *          This parameter must be a value between 0x00 and 0x0F.
  * @retval None
  */
static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter)
{
 80056e0:	b480      	push	{r7}
 80056e2:	b087      	sub	sp, #28
 80056e4:	af00      	add	r7, sp, #0
 80056e6:	60f8      	str	r0, [r7, #12]
 80056e8:	60b9      	str	r1, [r7, #8]
 80056ea:	607a      	str	r2, [r7, #4]
  uint32_t tmpccmr1;
  uint32_t tmpccer;

  /* Disable the Channel 1: Reset the CC1E Bit */
  tmpccer = TIMx->CCER;
 80056ec:	68fb      	ldr	r3, [r7, #12]
 80056ee:	6a1b      	ldr	r3, [r3, #32]
 80056f0:	617b      	str	r3, [r7, #20]
  TIMx->CCER &= ~TIM_CCER_CC1E;
 80056f2:	68fb      	ldr	r3, [r7, #12]
 80056f4:	6a1b      	ldr	r3, [r3, #32]
 80056f6:	f023 0201 	bic.w	r2, r3, #1
 80056fa:	68fb      	ldr	r3, [r7, #12]
 80056fc:	621a      	str	r2, [r3, #32]
  tmpccmr1 = TIMx->CCMR1;
 80056fe:	68fb      	ldr	r3, [r7, #12]
 8005700:	699b      	ldr	r3, [r3, #24]
 8005702:	613b      	str	r3, [r7, #16]

  /* Set the filter */
  tmpccmr1 &= ~TIM_CCMR1_IC1F;
 8005704:	693b      	ldr	r3, [r7, #16]
 8005706:	f023 03f0 	bic.w	r3, r3, #240	@ 0xf0
 800570a:	613b      	str	r3, [r7, #16]
  tmpccmr1 |= (TIM_ICFilter << 4U);
 800570c:	687b      	ldr	r3, [r7, #4]
 800570e:	011b      	lsls	r3, r3, #4
 8005710:	693a      	ldr	r2, [r7, #16]
 8005712:	4313      	orrs	r3, r2
 8005714:	613b      	str	r3, [r7, #16]

  /* Select the Polarity and set the CC1E Bit */
  tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP);
 8005716:	697b      	ldr	r3, [r7, #20]
 8005718:	f023 030a 	bic.w	r3, r3, #10
 800571c:	617b      	str	r3, [r7, #20]
  tmpccer |= TIM_ICPolarity;
 800571e:	697a      	ldr	r2, [r7, #20]
 8005720:	68bb      	ldr	r3, [r7, #8]
 8005722:	4313      	orrs	r3, r2
 8005724:	617b      	str	r3, [r7, #20]

  /* Write to TIMx CCMR1 and CCER registers */
  TIMx->CCMR1 = tmpccmr1;
 8005726:	68fb      	ldr	r3, [r7, #12]
 8005728:	693a      	ldr	r2, [r7, #16]
 800572a:	619a      	str	r2, [r3, #24]
  TIMx->CCER = tmpccer;
 800572c:	68fb      	ldr	r3, [r7, #12]
 800572e:	697a      	ldr	r2, [r7, #20]
 8005730:	621a      	str	r2, [r3, #32]
}
 8005732:	bf00      	nop
 8005734:	371c      	adds	r7, #28
 8005736:	46bd      	mov	sp, r7
 8005738:	f85d 7b04 	ldr.w	r7, [sp], #4
 800573c:	4770      	bx	lr

0800573e <TIM_TI2_ConfigInputStage>:
  * @param  TIM_ICFilter Specifies the Input Capture Filter.
  *          This parameter must be a value between 0x00 and 0x0F.
  * @retval None
  */
static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter)
{
 800573e:	b480      	push	{r7}
 8005740:	b087      	sub	sp, #28
 8005742:	af00      	add	r7, sp, #0
 8005744:	60f8      	str	r0, [r7, #12]
 8005746:	60b9      	str	r1, [r7, #8]
 8005748:	607a      	str	r2, [r7, #4]
  uint32_t tmpccmr1;
  uint32_t tmpccer;

  /* Disable the Channel 2: Reset the CC2E Bit */
  tmpccer = TIMx->CCER;
 800574a:	68fb      	ldr	r3, [r7, #12]
 800574c:	6a1b      	ldr	r3, [r3, #32]
 800574e:	617b      	str	r3, [r7, #20]
  TIMx->CCER &= ~TIM_CCER_CC2E;
 8005750:	68fb      	ldr	r3, [r7, #12]
 8005752:	6a1b      	ldr	r3, [r3, #32]
 8005754:	f023 0210 	bic.w	r2, r3, #16
 8005758:	68fb      	ldr	r3, [r7, #12]
 800575a:	621a      	str	r2, [r3, #32]
  tmpccmr1 = TIMx->CCMR1;
 800575c:	68fb      	ldr	r3, [r7, #12]
 800575e:	699b      	ldr	r3, [r3, #24]
 8005760:	613b      	str	r3, [r7, #16]

  /* Set the filter */
  tmpccmr1 &= ~TIM_CCMR1_IC2F;
 8005762:	693b      	ldr	r3, [r7, #16]
 8005764:	f423 4370 	bic.w	r3, r3, #61440	@ 0xf000
 8005768:	613b      	str	r3, [r7, #16]
  tmpccmr1 |= (TIM_ICFilter << 12U);
 800576a:	687b      	ldr	r3, [r7, #4]
 800576c:	031b      	lsls	r3, r3, #12
 800576e:	693a      	ldr	r2, [r7, #16]
 8005770:	4313      	orrs	r3, r2
 8005772:	613b      	str	r3, [r7, #16]

  /* Select the Polarity and set the CC2E Bit */
  tmpccer &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP);
 8005774:	697b      	ldr	r3, [r7, #20]
 8005776:	f023 03a0 	bic.w	r3, r3, #160	@ 0xa0
 800577a:	617b      	str	r3, [r7, #20]
  tmpccer |= (TIM_ICPolarity << 4U);
 800577c:	68bb      	ldr	r3, [r7, #8]
 800577e:	011b      	lsls	r3, r3, #4
 8005780:	697a      	ldr	r2, [r7, #20]
 8005782:	4313      	orrs	r3, r2
 8005784:	617b      	str	r3, [r7, #20]

  /* Write to TIMx CCMR1 and CCER registers */
  TIMx->CCMR1 = tmpccmr1 ;
 8005786:	68fb      	ldr	r3, [r7, #12]
 8005788:	693a      	ldr	r2, [r7, #16]
 800578a:	619a      	str	r2, [r3, #24]
  TIMx->CCER = tmpccer;
 800578c:	68fb      	ldr	r3, [r7, #12]
 800578e:	697a      	ldr	r2, [r7, #20]
 8005790:	621a      	str	r2, [r3, #32]
}
 8005792:	bf00      	nop
 8005794:	371c      	adds	r7, #28
 8005796:	46bd      	mov	sp, r7
 8005798:	f85d 7b04 	ldr.w	r7, [sp], #4
 800579c:	4770      	bx	lr

0800579e <TIM_ITRx_SetConfig>:
  *            @arg TIM_TS_TI2FP2: Filtered Timer Input 2
  *            @arg TIM_TS_ETRF: External Trigger input
  * @retval None
  */
static void TIM_ITRx_SetConfig(TIM_TypeDef *TIMx, uint32_t InputTriggerSource)
{
 800579e:	b480      	push	{r7}
 80057a0:	b085      	sub	sp, #20
 80057a2:	af00      	add	r7, sp, #0
 80057a4:	6078      	str	r0, [r7, #4]
 80057a6:	6039      	str	r1, [r7, #0]
  uint32_t tmpsmcr;

  /* Get the TIMx SMCR register value */
  tmpsmcr = TIMx->SMCR;
 80057a8:	687b      	ldr	r3, [r7, #4]
 80057aa:	689b      	ldr	r3, [r3, #8]
 80057ac:	60fb      	str	r3, [r7, #12]
  /* Reset the TS Bits */
  tmpsmcr &= ~TIM_SMCR_TS;
 80057ae:	68fb      	ldr	r3, [r7, #12]
 80057b0:	f023 0370 	bic.w	r3, r3, #112	@ 0x70
 80057b4:	60fb      	str	r3, [r7, #12]
  /* Set the Input Trigger source and the slave mode*/
  tmpsmcr |= (InputTriggerSource | TIM_SLAVEMODE_EXTERNAL1);
 80057b6:	683a      	ldr	r2, [r7, #0]
 80057b8:	68fb      	ldr	r3, [r7, #12]
 80057ba:	4313      	orrs	r3, r2
 80057bc:	f043 0307 	orr.w	r3, r3, #7
 80057c0:	60fb      	str	r3, [r7, #12]
  /* Write to TIMx SMCR */
  TIMx->SMCR = tmpsmcr;
 80057c2:	687b      	ldr	r3, [r7, #4]
 80057c4:	68fa      	ldr	r2, [r7, #12]
 80057c6:	609a      	str	r2, [r3, #8]
}
 80057c8:	bf00      	nop
 80057ca:	3714      	adds	r7, #20
 80057cc:	46bd      	mov	sp, r7
 80057ce:	f85d 7b04 	ldr.w	r7, [sp], #4
 80057d2:	4770      	bx	lr

080057d4 <TIM_ETR_SetConfig>:
  *          This parameter must be a value between 0x00 and 0x0F
  * @retval None
  */
void TIM_ETR_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ExtTRGPrescaler,
                       uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter)
{
 80057d4:	b480      	push	{r7}
 80057d6:	b087      	sub	sp, #28
 80057d8:	af00      	add	r7, sp, #0
 80057da:	60f8      	str	r0, [r7, #12]
 80057dc:	60b9      	str	r1, [r7, #8]
 80057de:	607a      	str	r2, [r7, #4]
 80057e0:	603b      	str	r3, [r7, #0]
  uint32_t tmpsmcr;

  tmpsmcr = TIMx->SMCR;
 80057e2:	68fb      	ldr	r3, [r7, #12]
 80057e4:	689b      	ldr	r3, [r3, #8]
 80057e6:	617b      	str	r3, [r7, #20]

  /* Reset the ETR Bits */
  tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP);
 80057e8:	697b      	ldr	r3, [r7, #20]
 80057ea:	f423 437f 	bic.w	r3, r3, #65280	@ 0xff00
 80057ee:	617b      	str	r3, [r7, #20]

  /* Set the Prescaler, the Filter value and the Polarity */
  tmpsmcr |= (uint32_t)(TIM_ExtTRGPrescaler | (TIM_ExtTRGPolarity | (ExtTRGFilter << 8U)));
 80057f0:	683b      	ldr	r3, [r7, #0]
 80057f2:	021a      	lsls	r2, r3, #8
 80057f4:	687b      	ldr	r3, [r7, #4]
 80057f6:	431a      	orrs	r2, r3
 80057f8:	68bb      	ldr	r3, [r7, #8]
 80057fa:	4313      	orrs	r3, r2
 80057fc:	697a      	ldr	r2, [r7, #20]
 80057fe:	4313      	orrs	r3, r2
 8005800:	617b      	str	r3, [r7, #20]

  /* Write to TIMx SMCR */
  TIMx->SMCR = tmpsmcr;
 8005802:	68fb      	ldr	r3, [r7, #12]
 8005804:	697a      	ldr	r2, [r7, #20]
 8005806:	609a      	str	r2, [r3, #8]
}
 8005808:	bf00      	nop
 800580a:	371c      	adds	r7, #28
 800580c:	46bd      	mov	sp, r7
 800580e:	f85d 7b04 	ldr.w	r7, [sp], #4
 8005812:	4770      	bx	lr

08005814 <HAL_TIMEx_MasterConfigSynchronization>:
  *         mode.
  * @retval HAL status
  */
HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim,
                                                        const TIM_MasterConfigTypeDef *sMasterConfig)
{
 8005814:	b480      	push	{r7}
 8005816:	b085      	sub	sp, #20
 8005818:	af00      	add	r7, sp, #0
 800581a:	6078      	str	r0, [r7, #4]
 800581c:	6039      	str	r1, [r7, #0]
  assert_param(IS_TIM_MASTER_INSTANCE(htim->Instance));
  assert_param(IS_TIM_TRGO_SOURCE(sMasterConfig->MasterOutputTrigger));
  assert_param(IS_TIM_MSM_STATE(sMasterConfig->MasterSlaveMode));

  /* Check input state */
  __HAL_LOCK(htim);
 800581e:	687b      	ldr	r3, [r7, #4]
 8005820:	f893 303c 	ldrb.w	r3, [r3, #60]	@ 0x3c
 8005824:	2b01      	cmp	r3, #1
 8005826:	d101      	bne.n	800582c <HAL_TIMEx_MasterConfigSynchronization+0x18>
 8005828:	2302      	movs	r3, #2
 800582a:	e05a      	b.n	80058e2 <HAL_TIMEx_MasterConfigSynchronization+0xce>
 800582c:	687b      	ldr	r3, [r7, #4]
 800582e:	2201      	movs	r2, #1
 8005830:	f883 203c 	strb.w	r2, [r3, #60]	@ 0x3c

  /* Change the handler state */
  htim->State = HAL_TIM_STATE_BUSY;
 8005834:	687b      	ldr	r3, [r7, #4]
 8005836:	2202      	movs	r2, #2
 8005838:	f883 203d 	strb.w	r2, [r3, #61]	@ 0x3d

  /* Get the TIMx CR2 register value */
  tmpcr2 = htim->Instance->CR2;
 800583c:	687b      	ldr	r3, [r7, #4]
 800583e:	681b      	ldr	r3, [r3, #0]
 8005840:	685b      	ldr	r3, [r3, #4]
 8005842:	60fb      	str	r3, [r7, #12]

  /* Get the TIMx SMCR register value */
  tmpsmcr = htim->Instance->SMCR;
 8005844:	687b      	ldr	r3, [r7, #4]
 8005846:	681b      	ldr	r3, [r3, #0]
 8005848:	689b      	ldr	r3, [r3, #8]
 800584a:	60bb      	str	r3, [r7, #8]

  /* Reset the MMS Bits */
  tmpcr2 &= ~TIM_CR2_MMS;
 800584c:	68fb      	ldr	r3, [r7, #12]
 800584e:	f023 0370 	bic.w	r3, r3, #112	@ 0x70
 8005852:	60fb      	str	r3, [r7, #12]
  /* Select the TRGO source */
  tmpcr2 |=  sMasterConfig->MasterOutputTrigger;
 8005854:	683b      	ldr	r3, [r7, #0]
 8005856:	681b      	ldr	r3, [r3, #0]
 8005858:	68fa      	ldr	r2, [r7, #12]
 800585a:	4313      	orrs	r3, r2
 800585c:	60fb      	str	r3, [r7, #12]

  /* Update TIMx CR2 */
  htim->Instance->CR2 = tmpcr2;
 800585e:	687b      	ldr	r3, [r7, #4]
 8005860:	681b      	ldr	r3, [r3, #0]
 8005862:	68fa      	ldr	r2, [r7, #12]
 8005864:	605a      	str	r2, [r3, #4]

  if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
 8005866:	687b      	ldr	r3, [r7, #4]
 8005868:	681b      	ldr	r3, [r3, #0]
 800586a:	4a21      	ldr	r2, [pc, #132]	@ (80058f0 <HAL_TIMEx_MasterConfigSynchronization+0xdc>)
 800586c:	4293      	cmp	r3, r2
 800586e:	d022      	beq.n	80058b6 <HAL_TIMEx_MasterConfigSynchronization+0xa2>
 8005870:	687b      	ldr	r3, [r7, #4]
 8005872:	681b      	ldr	r3, [r3, #0]
 8005874:	f1b3 4f80 	cmp.w	r3, #1073741824	@ 0x40000000
 8005878:	d01d      	beq.n	80058b6 <HAL_TIMEx_MasterConfigSynchronization+0xa2>
 800587a:	687b      	ldr	r3, [r7, #4]
 800587c:	681b      	ldr	r3, [r3, #0]
 800587e:	4a1d      	ldr	r2, [pc, #116]	@ (80058f4 <HAL_TIMEx_MasterConfigSynchronization+0xe0>)
 8005880:	4293      	cmp	r3, r2
 8005882:	d018      	beq.n	80058b6 <HAL_TIMEx_MasterConfigSynchronization+0xa2>
 8005884:	687b      	ldr	r3, [r7, #4]
 8005886:	681b      	ldr	r3, [r3, #0]
 8005888:	4a1b      	ldr	r2, [pc, #108]	@ (80058f8 <HAL_TIMEx_MasterConfigSynchronization+0xe4>)
 800588a:	4293      	cmp	r3, r2
 800588c:	d013      	beq.n	80058b6 <HAL_TIMEx_MasterConfigSynchronization+0xa2>
 800588e:	687b      	ldr	r3, [r7, #4]
 8005890:	681b      	ldr	r3, [r3, #0]
 8005892:	4a1a      	ldr	r2, [pc, #104]	@ (80058fc <HAL_TIMEx_MasterConfigSynchronization+0xe8>)
 8005894:	4293      	cmp	r3, r2
 8005896:	d00e      	beq.n	80058b6 <HAL_TIMEx_MasterConfigSynchronization+0xa2>
 8005898:	687b      	ldr	r3, [r7, #4]
 800589a:	681b      	ldr	r3, [r3, #0]
 800589c:	4a18      	ldr	r2, [pc, #96]	@ (8005900 <HAL_TIMEx_MasterConfigSynchronization+0xec>)
 800589e:	4293      	cmp	r3, r2
 80058a0:	d009      	beq.n	80058b6 <HAL_TIMEx_MasterConfigSynchronization+0xa2>
 80058a2:	687b      	ldr	r3, [r7, #4]
 80058a4:	681b      	ldr	r3, [r3, #0]
 80058a6:	4a17      	ldr	r2, [pc, #92]	@ (8005904 <HAL_TIMEx_MasterConfigSynchronization+0xf0>)
 80058a8:	4293      	cmp	r3, r2
 80058aa:	d004      	beq.n	80058b6 <HAL_TIMEx_MasterConfigSynchronization+0xa2>
 80058ac:	687b      	ldr	r3, [r7, #4]
 80058ae:	681b      	ldr	r3, [r3, #0]
 80058b0:	4a15      	ldr	r2, [pc, #84]	@ (8005908 <HAL_TIMEx_MasterConfigSynchronization+0xf4>)
 80058b2:	4293      	cmp	r3, r2
 80058b4:	d10c      	bne.n	80058d0 <HAL_TIMEx_MasterConfigSynchronization+0xbc>
  {
    /* Reset the MSM Bit */
    tmpsmcr &= ~TIM_SMCR_MSM;
 80058b6:	68bb      	ldr	r3, [r7, #8]
 80058b8:	f023 0380 	bic.w	r3, r3, #128	@ 0x80
 80058bc:	60bb      	str	r3, [r7, #8]
    /* Set master mode */
    tmpsmcr |= sMasterConfig->MasterSlaveMode;
 80058be:	683b      	ldr	r3, [r7, #0]
 80058c0:	685b      	ldr	r3, [r3, #4]
 80058c2:	68ba      	ldr	r2, [r7, #8]
 80058c4:	4313      	orrs	r3, r2
 80058c6:	60bb      	str	r3, [r7, #8]

    /* Update TIMx SMCR */
    htim->Instance->SMCR = tmpsmcr;
 80058c8:	687b      	ldr	r3, [r7, #4]
 80058ca:	681b      	ldr	r3, [r3, #0]
 80058cc:	68ba      	ldr	r2, [r7, #8]
 80058ce:	609a      	str	r2, [r3, #8]
  }

  /* Change the htim state */
  htim->State = HAL_TIM_STATE_READY;
 80058d0:	687b      	ldr	r3, [r7, #4]
 80058d2:	2201      	movs	r2, #1
 80058d4:	f883 203d 	strb.w	r2, [r3, #61]	@ 0x3d

  __HAL_UNLOCK(htim);
 80058d8:	687b      	ldr	r3, [r7, #4]
 80058da:	2200      	movs	r2, #0
 80058dc:	f883 203c 	strb.w	r2, [r3, #60]	@ 0x3c

  return HAL_OK;
 80058e0:	2300      	movs	r3, #0
}
 80058e2:	4618      	mov	r0, r3
 80058e4:	3714      	adds	r7, #20
 80058e6:	46bd      	mov	sp, r7
 80058e8:	f85d 7b04 	ldr.w	r7, [sp], #4
 80058ec:	4770      	bx	lr
 80058ee:	bf00      	nop
 80058f0:	40010000 	.word	0x40010000
 80058f4:	40000400 	.word	0x40000400
 80058f8:	40000800 	.word	0x40000800
 80058fc:	40000c00 	.word	0x40000c00
 8005900:	40010400 	.word	0x40010400
 8005904:	40014000 	.word	0x40014000
 8005908:	40001800 	.word	0x40001800

0800590c <HAL_TIMEx_CommutCallback>:
  * @brief  Commutation callback in non-blocking mode
  * @param  htim TIM handle
  * @retval None
  */
__weak void HAL_TIMEx_CommutCallback(TIM_HandleTypeDef *htim)
{
 800590c:	b480      	push	{r7}
 800590e:	b083      	sub	sp, #12
 8005910:	af00      	add	r7, sp, #0
 8005912:	6078      	str	r0, [r7, #4]
  UNUSED(htim);

  /* NOTE : This function should not be modified, when the callback is needed,
            the HAL_TIMEx_CommutCallback could be implemented in the user file
   */
}
 8005914:	bf00      	nop
 8005916:	370c      	adds	r7, #12
 8005918:	46bd      	mov	sp, r7
 800591a:	f85d 7b04 	ldr.w	r7, [sp], #4
 800591e:	4770      	bx	lr

08005920 <HAL_TIMEx_BreakCallback>:
  * @brief  Break detection callback in non-blocking mode
  * @param  htim TIM handle
  * @retval None
  */
__weak void HAL_TIMEx_BreakCallback(TIM_HandleTypeDef *htim)
{
 8005920:	b480      	push	{r7}
 8005922:	b083      	sub	sp, #12
 8005924:	af00      	add	r7, sp, #0
 8005926:	6078      	str	r0, [r7, #4]
  UNUSED(htim);

  /* NOTE : This function should not be modified, when the callback is needed,
            the HAL_TIMEx_BreakCallback could be implemented in the user file
   */
}
 8005928:	bf00      	nop
 800592a:	370c      	adds	r7, #12
 800592c:	46bd      	mov	sp, r7
 800592e:	f85d 7b04 	ldr.w	r7, [sp], #4
 8005932:	4770      	bx	lr

08005934 <memset>:
 8005934:	4402      	add	r2, r0
 8005936:	4603      	mov	r3, r0
 8005938:	4293      	cmp	r3, r2
 800593a:	d100      	bne.n	800593e <memset+0xa>
 800593c:	4770      	bx	lr
 800593e:	f803 1b01 	strb.w	r1, [r3], #1
 8005942:	e7f9      	b.n	8005938 <memset+0x4>

08005944 <__libc_init_array>:
 8005944:	b570      	push	{r4, r5, r6, lr}
 8005946:	4d0d      	ldr	r5, [pc, #52]	@ (800597c <__libc_init_array+0x38>)
 8005948:	4c0d      	ldr	r4, [pc, #52]	@ (8005980 <__libc_init_array+0x3c>)
 800594a:	1b64      	subs	r4, r4, r5
 800594c:	10a4      	asrs	r4, r4, #2
 800594e:	2600      	movs	r6, #0
 8005950:	42a6      	cmp	r6, r4
 8005952:	d109      	bne.n	8005968 <__libc_init_array+0x24>
 8005954:	4d0b      	ldr	r5, [pc, #44]	@ (8005984 <__libc_init_array+0x40>)
 8005956:	4c0c      	ldr	r4, [pc, #48]	@ (8005988 <__libc_init_array+0x44>)
 8005958:	f000 f826 	bl	80059a8 <_init>
 800595c:	1b64      	subs	r4, r4, r5
 800595e:	10a4      	asrs	r4, r4, #2
 8005960:	2600      	movs	r6, #0
 8005962:	42a6      	cmp	r6, r4
 8005964:	d105      	bne.n	8005972 <__libc_init_array+0x2e>
 8005966:	bd70      	pop	{r4, r5, r6, pc}
 8005968:	f855 3b04 	ldr.w	r3, [r5], #4
 800596c:	4798      	blx	r3
 800596e:	3601      	adds	r6, #1
 8005970:	e7ee      	b.n	8005950 <__libc_init_array+0xc>
 8005972:	f855 3b04 	ldr.w	r3, [r5], #4
 8005976:	4798      	blx	r3
 8005978:	3601      	adds	r6, #1
 800597a:	e7f2      	b.n	8005962 <__libc_init_array+0x1e>
 800597c:	08005df8 	.word	0x08005df8
 8005980:	08005df8 	.word	0x08005df8
 8005984:	08005df8 	.word	0x08005df8
 8005988:	08005dfc 	.word	0x08005dfc

0800598c <memcpy>:
 800598c:	440a      	add	r2, r1
 800598e:	4291      	cmp	r1, r2
 8005990:	f100 33ff 	add.w	r3, r0, #4294967295
 8005994:	d100      	bne.n	8005998 <memcpy+0xc>
 8005996:	4770      	bx	lr
 8005998:	b510      	push	{r4, lr}
 800599a:	f811 4b01 	ldrb.w	r4, [r1], #1
 800599e:	f803 4f01 	strb.w	r4, [r3, #1]!
 80059a2:	4291      	cmp	r1, r2
 80059a4:	d1f9      	bne.n	800599a <memcpy+0xe>
 80059a6:	bd10      	pop	{r4, pc}

080059a8 <_init>:
 80059a8:	b5f8      	push	{r3, r4, r5, r6, r7, lr}
 80059aa:	bf00      	nop
 80059ac:	bcf8      	pop	{r3, r4, r5, r6, r7}
 80059ae:	bc08      	pop	{r3}
 80059b0:	469e      	mov	lr, r3
 80059b2:	4770      	bx	lr

080059b4 <_fini>:
 80059b4:	b5f8      	push	{r3, r4, r5, r6, r7, lr}
 80059b6:	bf00      	nop
 80059b8:	bcf8      	pop	{r3, r4, r5, r6, r7}
 80059ba:	bc08      	pop	{r3}
 80059bc:	469e      	mov	lr, r3
 80059be:	4770      	bx	lr